A successive approximation type analog-to-digital converter, an oversampling method and device

Abstract

The present invention provides a successive approximation analog-to-digital converter, an oversampling method and an apparatus. Through the processing scheme of the present invention, the same analog signal generally does not change much during oversampling and the sampling error does not exceed 2 M To address this issue, the SAR ADC integrates an oversampling error range signal, an oversampling enable signal, a previous set of result registers, and control logic to support oversampling. When oversampling is enabled, the SAR ADC uses the highest bits of the previous result register as much as possible, gradually approximating the remaining result bits from a certain middle bit toward the lower bits. This effectively improves the SAR ADC's conversion efficiency for multiple consecutive analog signal sampling conversions without significantly increasing hardware resources, shortening the analog signal oversampling time.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a successive approximation analog-to-digital converter, an oversampling method and a device. Background Art

[0002] A successive approximation register analog-to-digital converter (SAR ADC) is a common analog-to-digital converter that is used to sample analog signals and convert them into digital signals.

[0003] The SAR ADC consists of five main components: a control circuit, a sample-and-hold circuit, an analog comparator, a SAR successive approximation register, and a digital-to-analog converter (DAC). After receiving an external sampling enable signal, the control circuit first samples and holds the analog signal to the input voltage Vin during the sampling phase. It then sequentially changes the digital signal of the DAC digital-to-analog converter from high to low, causing the DAC to output an analog output voltage Vo. The analog comparator sequentially compares Vin and Vo, allowing Vo to eventually approximate Vin. This produces the final DAC digital signal, which serves as the final digital result after the SAR ADC analog-to-digital conversion. During conversion, the DAC defaults to an all-zero input digital signal. The highest bit of the DAC input digital signal is first set to "1," and Vin and Vo are compared. If Vin is not higher than Vo, the DAC input digital signal is set to "0." A similar process continues, moving from high to low, determining one bit of the DAC input digital signal each cycle until all bits have been determined, concluding the conversion. The final DAC input digital signal is the digital signal conversion result of the SAR ADC.

[0004] To reduce analog signal sampling errors, oversampling is often necessary. This involves repeatedly sampling and converting the analog signal, filtering the results, and obtaining the final sampled result. Existing SAR ADCs require both a sampling and conversion phase for each sampling and conversion. The conversion phase requires N clock cycles to convert the digital result from high-order bits to low-order bits. If oversampling is performed X times in a row, the cumulative conversion time for the oversampling process is X*N clock cycles. This results in relatively low oversampling conversion efficiency. To improve this efficiency, SAR ADCs typically employ a pipeline approach. However, the hardware resources required for pipelined SAR ADCs increase with the number of pipeline stages. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a successive approximation analog-to-digital converter, an oversampling method, and an apparatus to at least partially resolve the problems existing in the prior art.

[0006] In a first aspect, an embodiment of the present disclosure provides a successive approximation analog-to-digital converter oversampling method, comprising:

[0007] If an oversampling enable signal is received, an oversampling error index M is obtained;

[0008] Get the conversion data P stored in the previous set of result registers N-1 P N-2 P N-3 ...P1P0, where N is the number of sampling bits, P N-1 The highest bit conversion data, P0 represents the lowest bit conversion data; set the current conversion data to D N-1 D N-2 D N-3 ...D1D0, where N is the number of sampling bits, D N-1 D0 represents the highest bit conversion data, and D1 represents the lowest bit conversion data;

[0009] In order from low to high, the conversion data P N-1 P N-2 P N-3 ...Search for the distance error index bit data P in P1P0 M-1 The most recent bit data P L = bit parameter L when 0;

[0010] Let the approximation parameter K = L;

[0011] Setting D N-1 D N-2 D N-3 …D K+1 =P N-1 P N-2 P N-3 …P K+1 , D K =1,D K-1 ...D1D0=0;

[0012] From D K First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 ...D1D0;

[0013] D N-1 D N-2 D N-3 ...D1D0 is used as the output analog-to-digital conversion data and stored in the result register.

[0014] According to a specific implementation of the embodiment of the present disclosure, the method further includes:

[0015] If the converted data P N-1 P N-2 P N-3 ...The distance error index bit data P cannot be found in P1P0 M The most recent bit data P L =0 when the bit;

[0016] Then let the approximation parameter K = N-1;

[0017] From D K First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 …D1D0.

[0018] According to a specific implementation of the embodiment of the present disclosure, the method further includes:

[0019] If L = N-1, then let the approximation parameter K = N-1;

[0020] From D K First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 …D1D0.

[0021] According to a specific implementation of the embodiment of the present disclosure, the method further includes:

[0022] If the input voltage V in Greater than the output voltage V o , then let the approximation parameter K = N-1;

[0023] From D K First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 …D1D0.

[0024] According to a specific implementation of the embodiment of the present disclosure, the K First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 ...D1D0, including:

[0025] Let D K =1;

[0026] If the input voltage V inNot greater than the output voltage V o , then let D K =0;

[0027] Let K = K-1, and continue to judge the input voltage V in With the output voltage V o The steps are repeated until K=0;

[0028] If the input voltage V in Greater than the output voltage V o , then let K=K-1, and continue to judge the input voltage V in With the output voltage V o The process continues until K=0.

[0029] In a second aspect, an embodiment of the present disclosure provides a successive approximation analog-to-digital converter oversampling device, comprising:

[0030] An enabling module, configured to obtain an oversampling error index M upon receiving an oversampling enabling signal;

[0031] The acquisition module is used to obtain the conversion data P stored in the previous set of result registers N-1 P N-2 P N-3 ...P1P0, where N is the number of sampling bits, P N-1 The highest bit conversion data, P0 represents the lowest bit conversion data; set the current conversion data to D N-1 D N- 2D N-3 ...D1D0, where N is the number of sampling bits, D N-1 D0 represents the highest bit conversion data, and D1 represents the lowest bit conversion data;

[0032] A search module is used to convert the data P from the low bit to the high bit in order. N-1 P N-2 P N-3 ...Search for the distance error index bit data P in P1P0 M-1 The most recent bit data P L = bit parameter L when 0;

[0033] A first setting module is used to set the approximation parameter K=L;

[0034] The second setting module is used to set D N-1 D N-2 D N-3 …D K+1 =P N-1 P N-2 P N-3 …P K+1 , D K =1,DK-1 ...D1D0=0;

[0035] Approximation module for D K First, from high to low, use the successive approximation method to determine D K D K- 1D K-2 ...D1D0;

[0036] Storage module for D N-1 D N-2 D N-3 ...D1D0 is used as the output analog-to-digital conversion data and stored in the result register.

[0037] According to a specific implementation of the embodiment of the present disclosure, the approximation module is specifically configured to:

[0038] Let D K =1;

[0039] If the input voltage V in Not greater than the output voltage V o , then let D K =0;

[0040] Let K = K-1, and continue to judge the input voltage V in With the output voltage V o The steps are repeated until K=0;

[0041] If the input voltage V in Greater than the output voltage V o , then let K=K-1, and continue to judge the input voltage V in With the output voltage V o The process continues until K=0.

[0042] In a third aspect, an embodiment of the present disclosure further provides a successive approximation analog-to-digital converter, comprising:

[0043] The sample-and-hold circuit receives the input voltage V in ;

[0044] DAC digital-to-analog converter, used to convert the reference voltage V ref Converted to output voltage V o ;

[0045] Comparator, used to compare the input voltage V in and the output voltage V o The comparison result is sent to the successive approximation analog-to-digital converter oversampling device;

[0046] The successive approximation analog-to-digital converter oversampling device is used to implement the successive approximation analog-to-digital converter oversampling method described above.

[0047] According to a specific implementation of the embodiment of the present disclosure, the successive approximation analog-to-digital converter oversampling device includes:

[0048] The previous set of result registers is used to store the last conversion data P N-1 P N-2 P N-3 ...P1P0, where N is the number of sampling bits, P N-1 The highest bit conversion data, P0 represents the lowest bit conversion data; set the current conversion data to D N-1 D N-2 D N-3 ...D1D0, where N is the number of sampling bits, D N-1 D0 represents the highest bit conversion data, and D1 represents the lowest bit conversion data;

[0049] Control logic circuit for converting data P from the N-1 P N-2 P N-3 ...Search for the distance error index bit data P in P1P0 M-1 The most recent bit data P L = 0 when the bit parameter L; let the approximation parameter K = L; set D N-1 D N-2 D N-3 …D K+1 =P N-1 P N-2 P N-3 …P K+1 , D K =1,D K-1 ...D1D0=0;

[0050] SAR successive approximation register, used to read from D K First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 ...D1D0;

[0051] The above set of result registers is also used to convert D N-1 D N-2 D N-3 ...D1D0 is used as the output analog-to-digital conversion data and stored.

[0052] In a fourth aspect, an embodiment of the present disclosure further provides an electronic device, the electronic device comprising:

[0053] at least one processor; and,

[0054] a memory communicatively connected to the at least one processor; wherein,

[0055] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the successive approximation analog-to-digital converter oversampling method in the aforementioned first aspect or any implementation of the first aspect.

[0056] In a fourth aspect, an embodiment of the present disclosure further provides a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions are used to enable the computer to execute a successive approximation analog-to-digital converter oversampling method in the aforementioned first aspect or any implementation of the first aspect.

[0057] In a fifth aspect, an embodiment of the present disclosure further provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer executes a successive approximation analog-to-digital converter oversampling method in the aforementioned first aspect or any implementation of the first aspect.

[0058] An oversampling scheme for a successive approximation analog-to-digital converter in an embodiment of the present disclosure includes obtaining an oversampling error index M if an oversampling enable signal is received; obtaining conversion data P stored in a previous set of result registers; N-1 P N-2 P N-3 ...P1P0, where N is the number of sampling bits, P N-1 The highest bit conversion data, P0 represents the lowest bit conversion data; set the current conversion data to D N-1 D N-2 D N-3 ...D1D0, where N is the number of sampling bits, D N-1 The highest bit conversion data, D0 represents the lowest bit conversion data; in order from low to high, from the conversion data P N-1 P N-2 P N-3 ...Search for the distance error index bit data P in P1P0 M-1 The most recent bit data P L = 0 when the bit parameter L; let the approximation parameter K = L; set D N-1 D N-2 D N-3 …D K+1 =P N- 1P N-2 P N-3 …P K+1 , D K=1,D K-1 ...D1D0=0; from D K First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 ...D1D0; D N-1 D N-2 D N-3 ...D1D0 is used as the output analog-to-digital conversion data and stored in the result register. The disclosed solution effectively improves the conversion efficiency of the SAR ADC for multiple consecutive sampling and conversion of analog signals without significantly increasing hardware resources, shortening the analog signal oversampling time. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0060] Figure 1 A schematic diagram of the structure of a successive approximation analog-to-digital converter provided in an embodiment of the present disclosure;

[0061] Figure 2 A schematic flow chart of a first successive approximation analog-to-digital converter oversampling method provided by an embodiment of the present disclosure;

[0062] Figure 3 A flowchart of a second successive approximation analog-to-digital converter oversampling method provided by an embodiment of the present disclosure;

[0063] Figure 4 A schematic flow chart of a third successive approximation analog-to-digital converter oversampling method provided by an embodiment of the present disclosure;

[0064] Figure 5 A schematic flow chart of a fourth successive approximation analog-to-digital converter oversampling method provided by an embodiment of the present disclosure;

[0065] Figure 6 A schematic structural diagram of a successive approximation analog-to-digital converter oversampling device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0067] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0068] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0069] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0070] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples. However, one skilled in the art will appreciate that the aspects described can be practiced without these specific details.

[0071] Figure 1 A schematic diagram of the structure of a successive approximation analog-to-digital converter provided in an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the SAR ADC includes: a sample-and-hold device 110 , a comparator 120 , a DAC digital-to-analog converter 130 and a successive approximation analog-to-digital converter oversampling device 140 .

[0072] The sample-and-hold circuit 110 receives an input voltage V in , where V in The DAC 130 converts the reference voltage Vref Converted to output voltage V o , where the reference voltage V ref is a digital voltage, the output voltage V o is an analog voltage. The comparator 120 compares the input voltage V in and the output voltage V o The comparison result is sent to the successive approximation ADC oversampling device 140. The successive approximation ADC oversampling device 140 includes: a group of result registers 141, a control logic circuit 142, and a SAR successive approximation register 143. The function of the successive approximation ADC oversampling device 140 is described in detail below.

[0073] Figure 2 The first successive approximation analog-to-digital converter oversampling method provided in the embodiment of the present disclosure is a flow chart, which is applied to the successive approximation analog-to-digital converter oversampling device 140. Figure 2 As shown, the method includes:

[0074] Step S21: if an oversampling enable signal is received, obtaining an oversampling error index M;

[0075] Specifically, in the successive approximation analog-to-digital converter oversampling system, an oversampling error range signal 2 is included. M , an oversampling enable signal 3a, a set of result registers 141 and a control logic circuit 142 supporting oversampling and a SAR successive approximation register 143. The oversampling error range signal defines that the sampling error does not exceed 2 M . The oversampling enable signal 3a is an input digital signal. During an analog signal sampling and conversion process, the oversampling enable signal 3a maintains an invalid level or a valid level: when the oversampling enable signal 3a is valid, it indicates that the analog signal of the current sampling conversion and the analog signal of the previous sampling conversion are from the same signal source, and together with the previous sampling conversion, they are a sampling conversion in multiple continuous samplings of the analog signal; when the oversampling enable signal 3a is invalid, it indicates that the analog signal of the current sampling conversion and the analog signal of the previous sampling conversion are not from the same signal source, or the current sampling conversion is not an oversampling of the previous sampling conversion, but a new sampling conversion. The previous set of result registers 141 is a register used to record the digital result of the previous conversion. When the oversampling enable signal 3a received by the control logic circuit 142 is valid, the control logic circuit 142 receives the oversampling error range signal 2 from the control logic circuit 142. M The oversampling error index M is determined in .

[0076] Step S22: Obtain the conversion data P stored in the previous set of result registers N-1 P N-2 P N-3...P1P0, where N is the number of sampling bits, P N-1 The highest bit conversion data, P0 represents the lowest bit conversion data; set the current conversion data to D N-1 D N-2 D N-3 ...D1D0, where N is the number of sampling bits, D N-1 D0 represents the highest bit conversion data, and D1 represents the lowest bit conversion data;

[0077] Specifically, the control logic circuit 142 obtains the conversion data P after the last system conversion from the previous set of result registers 141. N-1 P N-2 P N-3 ...P1P0, where N is the number of sampling bits, P N-1 The highest bit conversion data, P0 represents the lowest bit conversion data, and at the same time, the previous set of result registers 141 sets the current conversion data to D N-1 D N-2 D N-3 ...D1D0, where N is the number of sampling bits, D N-1 D0 represents the highest bit conversion data, and D1 represents the lowest bit conversion data;

[0078] Figure 3 A flow chart of a second successive approximation analog-to-digital converter oversampling method provided in an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, the last set of result registers 141 stores 12-bit conversion data P N-1 P N-2 P N-3 …P1P0=101110111100, oversampling error index M=2.

[0079] Step S23: In order from low to high, convert the data P N-1 P N-2 P N-3 ...Search for the distance error index bit data P in P1P0 M-1 The most recent bit data P L = bit parameter L when 0;

[0080] Specifically, the control logic circuit 142 converts the data P N-1 P N-2 P N-3 ...In P1P0, find the number of bits from P1 to P0 in the order from low to high. M-1 The most recent bit with a value of "0" is P L , and find the bit parameter L. Figure 3 As shown, P M-1 That is, P1=0, from low to high, the bit with the "0" closest to P1=0 is PL =P6, at this time, L=6.

[0081] Step S24, set the approximation parameter K=L;

[0082] Step S25: Set D N-1 D N-2 D N-3 …D K+1 =P N-1 P N-2 P N-3 …P K+1 , D K =1,D K-1 ...D1D0=0;

[0083] Step S26: From D K First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 ...D1D0;

[0084] Step S27: D N-1 D N-2 D N-3 ...D1D0 is used as the output analog-to-digital conversion data and stored in the result register.

[0085] Specifically, let the approximation parameter K = L, set D N-1 D N-2 D N-3 …D K+1 =P N-1 P N-2 P N-3 …P K+1 , D K =1,D K-1 ...D1D0=0, from D K First, in order from high to low, use the successive approximation method to infer the D of the DAC digital signal input L To D0. Figure 3 As shown, K=6, set D N-1 D N-2 D N-3 …D K+1 =10111, starting from D6, in descending order, use the successive approximation method to infer the digital signal input D6 to D0 of the DAC.

[0086] Specifically, Figure 4 A flowchart of a third successive approximation analog-to-digital converter oversampling method according to an embodiment of the present disclosure is shown in FIG. Figure 4 As shown:

[0087] First, let DK =1;

[0088] Determine the input voltage V in Is it not greater than the output voltage V o If so, let D K =0, otherwise D K =1;

[0089] Determine whether K is 0. If not, set K = K-1 and continue to determine the input voltage V in With the output voltage V o The steps are repeated until K=0;

[0090] If the input voltage V in Greater than the output voltage V o , then let K=K-1, and continue to judge the input voltage V in With the output voltage V o The process continues until K=0.

[0091] Finally, the converted data D K-1 D K-2 D K-3 ...D1D0 as the output of analog-to-digital conversion data.

[0092] Complete D N-1 D N-2 D N-3 …After all bits of D1D0 are deduced, the final digital signal input of the DAC is output as the converted digital result of the SAR ADC, and the result is recorded in the previous set of result registers 141.

[0093] In practical applications, if the converted data P N-1 P N-2 P N-3 ...The distance error index bit data P cannot be found in P1P0 M The most recent bit data P L =0 when the bit;

[0094] Then let the approximation parameter K = N-1;

[0095] From D K First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 …D1D0.

[0096] That is, if the converted data P N-1 P N-2 P N-3 ...The distance error index bit data P cannot be found in P1P0 M-1 The most recent bit data PL = 0, the error may cause the high bit to flip continuously, and the high bit result of the previous group of result registers cannot be used as the initial value of the successive comparison. The DAC needs to be in the order from high to low, using the successive approximation method to determine D N-1 D N-2 …D1D0.

[0097] In practical applications, if L = N-1, then let the approximation parameter K = N-1;

[0098] From D K First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 ...D1D0. That is, if L=N-1, the error may cause the high bit to flip continuously. The high bit result of the previous set of result registers cannot be used as the initial value of the successive comparison. The DAC needs to be in the order from high to low, using the successive approximation method to determine D N-1 D N-2 …D1D0.

[0099] In practical applications, if the input voltage V in Greater than the output voltage V o , then let the approximation parameter K = N-1;

[0100] From D K First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 …D1D0.

[0101] That is, if V in Greater than V o , it may mean that the analog signal suddenly becomes larger, P N-1 P N-2 P N-3 …P K+1 , can no longer be used as the initial value of the high bit of successive comparisons, then it is necessary to use the successive approximation method from high to low to determine D N-1 D N-2 …D1D0.

[0102] In addition, if the oversampling enable signal 3a is invalid, it means that the sampling conversion does not meet the oversampling condition, and the DAC needs to N-1 The successive approximation method is used to infer from high to low.

[0103] Excluding the above-mentioned special cases, the high-order data of the previous set of conversion results can be reused in other cases. Although in these special cases, compared with the conventional successive comparison, an extra successive comparison may be performed, which increases the conversion time, the probability of these special cases occurring is low. From a statistical point of view, the present disclosure can effectively improve the oversampling conversion efficiency of SAR ADC analog signals in most cases.

[0104] The oversampling method of the successive approximation analog-to-digital converter provided by the embodiment of the present disclosure utilizes the fact that the same analog signal generally does not change much during the oversampling period and the sampling error does not exceed 2 M To take advantage of the characteristics of a conventional SAR ADC converter, an oversampling error range signal, an oversampling enable signal, a previous set of result registers, and control logic circuitry to support oversampling are added. When oversampling is enabled, the high-order result of the previous result register is used as much as possible, and the remaining result bits are determined by successive approximation starting from a middle bit and working toward the lower bits. During oversampling conversion, since successive approximation is not always performed from the highest bit to the lowest bit, the number of successive approximations is reduced, improving conversion efficiency and, in turn, enhancing the conversion efficiency of the SAR ADC for oversampled analog signals.

[0105] Figure 5 A fourth successive approximation analog-to-digital converter oversampling method flow diagram provided in an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, the method includes:

[0106] 1) Input a valid oversampling enable signal to prove that the signal sampled this time comes from the same signal source as the signal sampled last time, and that it and the previous sampling conversion are one of the multiple continuous samplings of the analog signal. Take out the result P stored in the previous set of result registers. N-1 P N-2 P N-3 ...P1P0;

[0107] 2) Execution Figure 5 In the process of ①, query the distance P from the higher position M-1 Recent P L =0 bit, then L=6;

[0108] 3) Execution Figure 5 In the process of ②, P in the previous set of result registers N-1 P N-2 P N-3 …P L+1 The value of the bit is assigned to D N- 1D N-2 D N-3 …D L+1 ,D L =1,D L-1 ...D0 is set to 0, K=L: If Vin Not greater than V o , then D L =0, K=K-1, execute the process of ③; if V in Greater than V o , it may mean that the analog signal suddenly becomes larger, P N-1 P N-2 P N-3 …P L+1 If it can no longer be used as the high-order initial value for successive comparisons, you need to execute the process in step ③ and compare successively starting from the highest order.

[0109] 4) Execution Figure 5 In the process of ③, compare and determine D one by one N-1 D N-2 D N-3 ...all bits of D0.

[0110] 5)D N-1 D N-2 D N-3 ...After all bits of D0 are compared successively, D N-1 D N-2 D N-3 ...D0 is output as the digital result after SAR ADC conversion, and the result is recorded in the last result register (update P N-1 P N-2 P N-3 …P0).

[0111] in, Figure 5 The process in step 3, where K = N-1, infers the input of all DAC bits by successive approximation from high to low bits. This is applicable to the following situations:

[0112] 1) Oversampling enable signal is invalid, indicating that the sampling conversion does not meet the oversampling conditions, and DAC needs to start from the highest bit D N-1 Use successive approximation method to infer from high to low;

[0113] 2) In P N-1 P N-2 P N-3 …P M-1 Can't find P L = 0, or L = N-1, the use of errors may cause the high-bit continuous flip, the high-bit result of the previous result register cannot be used as the initial value of the successive comparison, the DAC needs to start from the highest bit D N-1 Use successive approximation method to infer from high to low;

[0114] 3) Execution Figure 5 In the process of ②, the P in the last result register N-1 P N-2 PN-3 …P L+1 The value of the bit is assigned to D N- 1D N-2 D N-3 …D L+1 ,D L =1,D L-1 ...D0 is set to 0, if V in Greater than V o , it may mean that the analog signal suddenly becomes larger, P N-1 P N-2 P N-3 …P L+1 It can no longer be used as the high-order initial value for successive comparisons. In this case, the process of step ③ needs to be executed, starting from the highest order and comparing successively.

[0115] Figure 5 The process in step ③ includes:

[0116] Let K = N-1, D K =1,D N-1 D N-2 D N-3 ...D0=0;

[0117] Determine the input voltage V in Is it not greater than the output voltage V o If so, let D K =0, otherwise D K =1;

[0118] Determine whether K is 0. If not, set K = K-1 and continue to determine the input voltage V in With the output voltage V o The steps are repeated until K=0;

[0119] If the input voltage V in Greater than the output voltage V o , then let K=K-1, and continue to judge the input voltage V in With the output voltage V o The process continues until K=0.

[0120] Finally, the converted data D N-1 D N-2 D N-3 ...D1D0 as the output of analog-to-digital conversion data.

[0121] The oversampling method for a successive approximation analog-to-digital converter (SAR ADC) provided in the embodiments of the present disclosure can effectively improve the conversion efficiency of the SAR ADC for multiple consecutive sampling and conversion of analog signals without significantly increasing hardware resources, thereby shortening the oversampling time of the analog signals.

[0122] Based on the same inventive concept, the embodiment of the present disclosure further provides a successive approximation analog-to-digital converter oversampling device, Figure 6 A schematic diagram of a successive approximation analog-to-digital converter oversampling device according to an embodiment of the present disclosure is shown in FIG. Figure 6 As shown, the device includes: an enabling module 61, an acquiring module 62, a searching module 63, a first setting module 64, a second setting module 65, an approximating module 66 and a storing module 67, wherein:

[0123] The enabling module 61 is used to obtain the oversampling error index M if an oversampling enabling signal is received; the obtaining module 62 is used to obtain the conversion data P stored in the previous set of result registers. N-1 P N-2 P N-3 ...P1P0, where N is the number of sampling bits, P N-1 The highest bit conversion data, P0 represents the lowest bit conversion data; set the current conversion data to D N-1 D N-2 D N-3 ...D1D0, where N is the number of sampling bits, D N-1 The search module 63 is used to search the converted data P in the order from low to high. N-1 P N-2 P N-3 ...Search for the distance error index bit data P in P1P0 M-1 The most recent bit data P L = 0 when the bit parameter L; the first setting module 64 is used to set the approximation parameter K = L; the second setting module 65 is used to set D N-1 D N-2 D N-3 …D K+1 =P N-1 P N-2 P N-3 …P K+1 , D K =1,D K-1 ...D1D0=0; the approximation module 66 is used to obtain the value of D K First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 ...D1D0; the storage module 67 is used to store D N- 1D N-2 D N-3 ...D1D0 is used as the output analog-to-digital conversion data and stored in the result register.

[0124] As in the above-mentioned successive approximation analog-to-digital converter oversampling device, optionally, the approximation module 66 is specifically configured to:

[0125] Let D K =1;

[0126] If the input voltage V in Not greater than the output voltage V o , then let D K =0;

[0127] Let K = K-1, and continue to judge the input voltage V in With the output voltage V o The steps are repeated until K=0;

[0128] If the input voltage V in Greater than the output voltage V o , then let K=K-1, and continue to judge the input voltage V in With the output voltage V o The process continues until K=0.

[0129] The successive approximation analog-to-digital converter oversampling device provided in the embodiments of the present disclosure is used to implement the above-mentioned successive approximation analog-to-digital converter oversampling method. Please refer to the above-mentioned method embodiments for details, which will not be repeated here.

[0130] The present disclosure discloses an electronic device, comprising: a processor, a memory, and a bus;

[0131] The processor and the memory communicate with each other via the bus.

[0132] The processor is used to call the program instructions in the memory to execute the methods provided by the above-mentioned method embodiments, for example, including: if an oversampling enable signal is received, obtaining the oversampling error index M; obtaining the conversion data P stored in the previous set of result registers; N-1 P N-2 P N-3 ...P1P0, where N is the number of sampling bits, P N-1 The highest bit conversion data, P0 represents the lowest bit conversion data; set the current conversion data to D N-1 D N-2 D N-3 ...D1D0, where N is the number of sampling bits, D N-1 The highest bit conversion data, D0 represents the lowest bit conversion data; in order from low to high, from the conversion data P N-1 P N-2 P N-3 ...Search for the distance error index bit data P in P1P0 M-1 The most recent bit data P L= 0 when the bit parameter L; let the approximation parameter K = L; set D N-1 D N-2 D N-3 …D K+1 =P N-1 P N-2 P N-3 …P K+1 , D K =1,D K-1 ...D1D0=0; from D K First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 ...D1D0; D N-1 D N-2 D N-3 ...D1D0 is used as the output analog-to-digital conversion data and stored in the result register.

[0133] The present disclosure discloses a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by a computer, the computer can perform the methods provided by the above-mentioned method embodiments, for example, including: if an oversampling enable signal is received, obtaining an oversampling error index M; obtaining conversion data P stored in a previous set of result registers; N-1 P N- 2P N-3 ...P1P0, where N is the number of sampling bits, P N-1 The highest bit conversion data, P0 represents the lowest bit conversion data; set the current conversion data to D N-1 D N-2 D N-3 ...D1D0, where N is the number of sampling bits, D N-1 The highest bit conversion data, D0 represents the lowest bit conversion data; in order from low to high, from the conversion data P N-1 P N-2 P N-3 ...Search for the distance error index bit data P in P1P0 M-1 The most recent bit data P L = 0 when the bit parameter L; let the approximation parameter K = L; set D N-1 D N-2 D N-3 …D K+1 =P N-1 P N-2 P N-3 …P K+1 , D K =1,D K-1 ...D1D0=0; from DK First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 ...D1D0; D N-1 D N-2 D N-3 ...D1D0 is used as the output analog-to-digital conversion data and stored in the result register.

[0134] The present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions enable the computer to execute the methods provided by the above-mentioned method embodiments, for example, including: if an oversampling enable signal is received, obtaining an oversampling error index M; obtaining conversion data P stored in a previous set of result registers; N-1 P N-2 P N-3 ...P1P0, where N is the number of sampling bits, P N-1 The highest bit conversion data, P0 represents the lowest bit conversion data; set the current conversion data to D N-1 D N-2 D N-3 ...D1D0, where N is the number of sampling bits, D N-1 The highest bit conversion data, D0 represents the lowest bit conversion data; in order from low to high, from the conversion data P N-1 P N-2 P N-3 ...Search for the distance error index bit data P in P1P0 M-1 The most recent bit data P L = 0 when the bit parameter L; let the approximation parameter K = L; set D N-1 D N-2 D N-3 …D K+1 =P N-1 P N-2 P N-3 …P K+1 , D K =1,D K-1 ...D1D0=0; from D K First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 ...D1D0; D N-1 D N-2 D N-3 ...D1D0 is used as the output analog-to-digital conversion data and stored in the result register.

[0135] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A successive approximation analog-to-digital converter oversampling method, characterized in that: include: If an oversampling enable signal is received, an oversampling error index M is obtained; Get the conversion data P stored in the previous set of result registers N-1 P N-2 P N-3 ...P1P0, where N is the number of sampling bits, P N-1 P0 represents the highest bit conversion data, and P1 represents the lowest bit conversion data; Set the conversion data to D N-1 D N-2 D N-3 ...D1D0, where N is the number of sampling bits, D N-1 D0 represents the highest bit conversion data, and D1 represents the lowest bit conversion data; In order from low to high, the conversion data P N-1 P N-2 P N-3 ...Search for the distance error index bit data P in P1P0 M-1 The most recent bit data P L = bit parameter L when 0; Let the approximation parameter K = L; Setting D N-1 D N-2 D N-3 …D K+1 =P N-1 P N-2 P N-3 …P K+1 , D K =1,D K-1 ...D1D0=0; From D K First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 ...D1D0; D N-1 D N-2 D N-3 ...D1D0 is used as the output analog-to-digital conversion data and stored in the result register.

2. The successive approximation analog-to-digital converter oversampling method according to claim 1, wherein: Also includes: If the converted data P N-1 P N-2 P N-3 ...The distance error index bit data P cannot be found in P1P0 M The most recent bit data P L =0 when the bit; Then let the approximation parameter K = N-1; From D K First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 …D1D0.

3. The successive approximation analog-to-digital converter oversampling method according to claim 1, wherein: Also includes: If L = N-1, then let the approximation parameter K = N-1; From D K First, in order from high to low, use the successive approximation method to determine D K D K-1 D K-2 …D1D0.

4. The successive approximation analog-to-digital converter oversampling method according to claim 1, wherein: Also includes: If the input voltage V in Greater than the output voltage V o , then let the approximation parameter K = N-1; From D K First, in order from high to low, use the successive approximation method to determine D K D K-1 D K-2 …D1D0.

5. The successive approximation analog-to-digital converter oversampling method according to any one of claims 1 to 4, characterized in that: The D K First, in order from high to low, use the successive approximation method to determine D K D K-1 D K-2 ...D1D0, including: Let D K =1; If the input voltage V in Not greater than the output voltage V o , then let D K =0; Let K = K-1, and continue to judge the input voltage V in With the output voltage V o The steps are repeated until K=0; If the input voltage V in Greater than the output voltage V o , then let K=K-1, and continue to judge the input voltage V in With the output voltage V o The process continues until K=0.

6. A successive approximation analog-to-digital converter oversampling device, characterized in that: include: An enabling module, configured to obtain an oversampling error index M upon receiving an oversampling enabling signal; The acquisition module is used to obtain the conversion data P stored in the previous set of result registers N-1 P N-2 P N-3 ...P1P0, where N is the number of sampling bits, P N-1 The highest bit conversion data, P0 represents the lowest bit conversion data; set the current conversion data to D N-1 D N-2 D N-3 ...D1D0, where N is the number of sampling bits, D N-1 D0 represents the highest bit conversion data, and D1 represents the lowest bit conversion data; A search module is used to convert the data P from the low bit to the high bit in order. N-1 P N-2 P N-3 ...Search for the distance error index bit data P in P1P0 M-1 The most recent bit data P L = bit parameter L when 0; A first setting module is used to set the approximation parameter K=L; The second setting module is used to set D N-1 D N-2 D N-3 …D K+1 =P N-1 P N-2 P N-3 …P K+1 , D K =1,D K-1 ...D1D0=0; Approximation module for D K First, from high to low, use the successive approximation method to determine D K D K-1 D K-2 ...D1D0; Storage module for D N-1 D N-2 D N-3 ...D1D0 is used as the output analog-to-digital conversion data and stored in the result register.

7. The successive approximation analog-to-digital converter oversampling device according to claim 6, wherein: The approximation module is specifically used for: Let D K =1; If the input voltage V in Not greater than the output voltage V o , then let D K =0; Let K = K-1, and continue to judge the input voltage V in With the output voltage V o The steps are repeated until K=0; If the input voltage V in Greater than the output voltage V o , then let K=K-1, and continue to judge the input voltage V in With the output voltage V o The process continues until K=0.

8. A successive approximation analog-to-digital converter, characterized in that include: The sample-and-hold circuit receives the input voltage V in ; DAC digital-to-analog converter, used to convert the reference voltage V ref Converted to output voltage V o ; Comparator, used to compare the input voltage V in and the output voltage V o The comparison result is sent to the successive approximation analog-to-digital converter oversampling device; The successive approximation analog-to-digital converter oversampling device is used to implement the successive approximation analog-to-digital converter oversampling method according to any one of claims 1 to 5.

9. A successive approximation analog-to-digital converter, characterized in that The successive approximation analog-to-digital converter oversampling device comprises: The previous set of result registers is used to store the last conversion data P N-1 P N-2 P N-3 ...P1P0, where N is the number of sampling bits, P N-1 The highest bit conversion data, P0 represents the lowest bit conversion data; set the current conversion data to D N-1 D N-2 D N-3 ...D1D0, where N is the number of sampling bits, D N-1 D0 represents the highest bit conversion data, and D1 represents the lowest bit conversion data; Control logic circuit for converting data P from the N-1 P N-2 P N-3 ...Search for the distance error index bit data P in P1P0 M-1 The most recent bit data P L = 0 when the bit parameter L; let the approximation parameter K = L; set D N-1 D N-2 D N-3 …D K+1 =P N-1 P N-2 P N-3 …P K+1 , D K =1,D K-1 ...D1D0=0; SAR successive approximation register, used to read from D K First, in order from high to low, use the successive approximation method to determine D K D K-1 D K-2 ...D1D0; The above set of result registers is also used to convert D N-1 D N-2 D N-3 ...D1D0 is used as the output analog-to-digital conversion data and stored.

10. A non-transitory computer-readable storage medium storing computer instructions, which, when executed by one or more processors, cause the one or more processors to perform the successive approximation analog-to-digital converter oversampling method according to any one of claims 1 to 5.

Images