Display panel

Abstract

A display panel is provided. The display panel includes a base substrate and a plurality of sub-pixels. Each sub-pixel includes a corresponding light-emitting element and a corresponding pixel driving circuit. The corresponding pixel driving circuit includes: a third transistor; and a storage capacitor including a first capacitor electrode located in a first conductive layer and a second capacitor electrode located in a second conductive layer. The second conductive layer is located on a side of the first conductive layer away from the base substrate. The second capacitor electrode includes an extension extending in a direction away from the electrode body of the second capacitor electrode. The orthographic projection of the extension on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor of the corresponding pixel driving circuit on the base substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a continuation-of U.S. Application No. 17 / 764,479, filed on June 25, 2021, which is a national phase application under 35 U.S.C. §371 of International Application No. PCT / CN2021 / 102249, filed on June 25, 2021. Each of the above applications is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] The present invention relates to display technology, and in particular to a display panel. Background Art

[0004] Organic light-emitting diode (OLED) displays are one of the hot topics in the field of flat panel display research today. Unlike thin-film transistor liquid crystal displays (TFT-LCDs) that use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control illumination. The OLED display panel includes a plurality of pixel units, which are configured with pixel drive circuits arranged in multiple rows and columns. Each pixel drive circuit includes a drive transistor having a gate terminal connected to a gate line for each row and a drain terminal connected to a data line for each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the drive transistor is turned on, and a data voltage is applied from the data line to the drive transistor via the switching transistor, so that the drive transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the Invention

[0005] In one aspect, the present disclosure provides a display panel comprising a base substrate, a plurality of sub-pixels, each sub-pixel comprising a corresponding light-emitting element and a corresponding pixel driving circuit; wherein the corresponding pixel driving circuit comprises: a third transistor; and a storage capacitor comprising a first capacitor electrode located in a first conductive layer and a second capacitor electrode located in a second conductive layer; wherein the second conductive layer is located on a side of the first conductive layer away from the base substrate; the second capacitor electrode comprises an extension portion extending in a direction away from the electrode body of the second capacitor electrode; and the orthographic projection of the extension portion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor of the corresponding pixel driving circuit on the base substrate.

[0006] Optionally, the third transistor includes a first gate and a second gate; the orthographic projection of the first gate on the base substrate overlaps with the orthographic projection of the first channel portion of the active layer of the third transistor on the base substrate; the orthographic projection of the second gate on the base substrate overlaps with the orthographic projection of the second channel portion of the active layer of the third transistor on the base substrate; the active layer of the third transistor also includes a portion connecting the first channel portion and the second channel portion; and the orthographic projection of the extension portion on the base substrate at least partially overlaps with the orthographic projection of the portion connecting the first channel portion and the second channel portion on the base substrate.

[0007] Optionally, the display panel also includes a first signal line layer located on a side of the storage capacitor away from the base substrate; wherein, a plurality of second capacitor electrodes respectively from a plurality of pixel driving circuits are connected to each other in sequence along a first direction; the first signal line layer includes a plurality of first high-voltage signal lines respectively along the first direction; and a corresponding one of the plurality of first high-voltage signal lines is connected to the second capacitor electrode.

[0008] Optionally, the extension portion includes a first extension portion along the second direction and a second extension portion along the first direction; the first extension portion connects the second extension portion and the electrode body of the second capacitor electrode; and the orthographic projection of the second extension portion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor of the corresponding pixel driving circuit on the base substrate.

[0009] Optionally, the second extension portion includes a shielding portion and a non-shielding portion; the orthographic projection of the shielding portion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor of the corresponding pixel driving circuit on the base substrate; the orthographic projection of the non-shielding portion on the base substrate does not overlap with the orthographic projection of the active layer of the third transistor of the corresponding pixel driving circuit on the base substrate; and the line width of the shielding portion is greater than the line width of the non-shielding portion.

[0010] Optionally, the corresponding pixel driving circuit also includes a driving transistor, and a node connection line connecting the drain of the third transistor and the gate of the driving transistor; wherein the drain of the third transistor is connected to the gate of the driving transistor; the source of the third transistor is connected to the drain of the driving transistor; and the positive projection of the first extension portion on the straight line extending along the second direction at least partially overlaps with the positive projection of the node connection line on the straight line.

[0011] Optionally, the display panel further includes a plurality of data lines; wherein the first extension portion is located between the node connection line and a corresponding data line among the plurality of data lines.

[0012] Optionally, the display panel also includes a plurality of gate lines; wherein corresponding gate lines among the plurality of gate lines include a plurality of metal blocks spaced apart from each other and located in a first conductive layer, and metal lines along a first direction and located in a first signal line layer, and the metal lines along the first direction are respectively connected to the plurality of metal blocks through through holes.

[0013] Optionally, the corresponding metal block among the multiple metal blocks has an L shape; the orthographic projection of the first channel portion of the active layer of the third transistor on the base substrate overlaps with the orthographic projection of the first metal portion of the corresponding metal block among the multiple metal blocks on the base substrate; the orthographic projection of the second channel portion of the active layer of the third transistor on the base substrate overlaps with the orthographic projection of the second metal portion of the corresponding metal block among the multiple metal blocks on the base substrate; and the first metal portion and the second metal portion are the first gate and the second gate of the third transistor.

[0014] Optionally, the display panel also includes: a plurality of first reset signal lines, which are respectively along the first direction and located in the semiconductor material layer; and a plurality of second reset signal lines, which are respectively along the second direction and located in the second signal line layer; wherein, the plurality of first reset signal lines respectively cross the plurality of second reset signal lines; a corresponding first reset signal line among the plurality of first reset signal lines is connected to at least a plurality of second reset signal lines among the plurality of second reset signal lines through a through hole; and a corresponding second reset signal line among the plurality of second reset signal lines is connected to at least a plurality of first reset signal lines among the plurality of first reset signal lines through a through hole.

[0015] Optionally, the display panel further comprises a plurality of second low voltage signal lines located in the second signal line layer and respectively extending along the second direction; wherein the plurality of second low voltage signal lines are electrically connected to the cathode of the light emitting element.

[0016] Optionally, the display panel also includes: a plurality of first high voltage signal lines, which extend respectively along the first direction and are located in the first signal line layer; and a plurality of second high voltage signal lines, which extend respectively along the second direction and are located in the second signal line layer; wherein, the plurality of first high voltage signal lines cross the plurality of second high voltage signal lines respectively; a corresponding first high voltage signal line among the plurality of first high voltage signal lines is connected to at least a plurality of second high voltage signal lines among the plurality of second high voltage signal lines through a through hole; and a corresponding second high voltage signal line among the plurality of second high voltage signal lines is connected to at least a plurality of first high voltage signal lines among the plurality of first high voltage signal lines through a through hole.

[0017] Optionally, each of the multiple first high voltage signal lines includes a main body extending along a first direction; a first protrusion protruding away from the main body along a second direction; and a second protrusion protruding away from the first protrusion along the second direction; wherein the second protrusion is connected to the main body through the first protrusion; and the second protrusion is a part of a corresponding one of the multiple second high voltage signal lines, in which part, a corresponding one of the multiple second high voltage signal lines is connected to a corresponding one of the multiple first high voltage signal lines through one or more through holes.

[0018] Optionally, the corresponding pixel driving circuit also includes a driving transistor, and a node connection line connecting the drain of the third transistor and the gate of the driving transistor; wherein the drain of the third transistor is connected to the gate of the driving transistor; the source of the third transistor is connected to the drain of the driving transistor; and the positive projection of the corresponding one of the multiple second high voltage signal lines on the base substrate covers the positive projection of the node connection line on the base substrate.

[0019] Optionally, an orthographic projection of the corresponding one of the plurality of second high voltage signal lines on the base substrate at least partially overlaps with an orthographic projection of at least one gate of the third transistor on the base substrate.

[0020] Optionally, the display panel includes: a plurality of light-emitting elements; and an interconnected first voltage supply network, which is configured to provide a first voltage signal to the cathodes of the plurality of light-emitting elements; wherein the interconnected first voltage supply network includes signal lines located in a display area of ​​the display panel, and the display area is at least partially surrounded by a peripheral area; the signal lines include a plurality of first signal lines located in a first signal line layer and a plurality of second signal lines located in a second signal line layer; the display panel also includes a planarization layer located between the first signal line layer and the second signal line layer; and the plurality of first signal lines are electrically connected to the plurality of second signal lines.

[0021] Optionally, the interconnected first voltage supply network includes: a plurality of first-first voltage signal lines respectively along the first direction; and a plurality of second-first voltage signal lines respectively along the second direction; wherein the plurality of first-first voltage signal lines respectively cross the plurality of second-first voltage signal lines.

[0022] Optionally, the interconnected first voltage supply network includes a first sub-network formed by the plurality of first-first voltage signal lines and a second sub-network formed by the plurality of second-first voltage signal lines.

[0023] Optionally, a corresponding first-first voltage signal line among the multiple first-first voltage signal lines is connected to at least a plurality of second-first voltage signal lines among the multiple second-first voltage signal lines; and a corresponding second-first voltage signal line among the multiple second-first voltage signal lines is connected to at least a plurality of first-first voltage signal lines among the multiple first-first voltage signal lines.

[0024] Optionally, the multiple first-first voltage signal lines and the multiple second-first voltage signal lines are interconnected by first through holes respectively extending through the planarization layer, and at least some of the first through holes are located in the display area; a corresponding one of the multiple first-first voltage signal lines is connected to at least a plurality of second-first voltage signal lines among the multiple second-first voltage signal lines through a plurality of first through holes extending through the planarization layer; and a corresponding one of the multiple second-first voltage signal lines is connected to at least a plurality of first-first voltage signal lines among the multiple first-first voltage signal lines through a plurality of first through holes extending through the planarization layer.

[0025] On the other hand, the present disclosure provides a display panel comprising a plurality of sub-pixels, each sub-pixel comprising a corresponding light-emitting element and a corresponding pixel driving circuit; wherein the display panel comprises a plurality of light-emitting elements; and an interconnected first voltage supply network configured to provide a first voltage signal to the cathodes of the plurality of light-emitting elements; wherein the interconnected first voltage supply network comprises signal lines located in a display area of ​​the display panel, the display area being at least partially surrounded by a peripheral area; the signal lines comprise a plurality of first signal lines located in a first signal line layer and a plurality of second signal lines located in a second signal line layer; the display panel further comprises a planarization layer located between the first signal line layer and the second signal line layer; and the plurality of first signal lines are electrically connected to the plurality of second signal lines.

[0026] Optionally, the interconnected first voltage supply network includes a plurality of first-first voltage signal lines respectively along the first direction; and a plurality of second-first voltage signal lines respectively along the second direction; wherein the plurality of first-first voltage signal lines respectively cross the plurality of second-first voltage signal lines.

[0027] Optionally, the interconnected first voltage supply network includes a first sub-network formed by a plurality of first-first voltage signal lines and a second sub-network formed by a plurality of second-first voltage signal lines.

[0028] Optionally, a corresponding one of the multiple first-first voltage signal lines is connected to at least a plurality of second-first voltage signal lines among the multiple second-first voltage signal lines; and a corresponding one of the multiple second-first voltage signal lines is connected to at least a plurality of first-first voltage signal lines among the multiple first-first voltage signal lines.

[0029] Optionally, the multiple first-first voltage signal lines and the multiple second-first voltage signal lines are interconnected by first through holes respectively extending through the planarization layer, at least some of the first through holes being located in the display area; a corresponding one of the multiple first-first voltage signal lines is connected to at least a plurality of second-first voltage signal lines among the multiple second-first voltage signal lines by a plurality of first through holes respectively extending through the planarization layer; and a corresponding one of the multiple second-first voltage signal lines is connected to at least a plurality of first-first voltage signal lines among the multiple first-first voltage signal lines by a plurality of first through holes respectively extending through the planarization layer.

[0030] Optionally, the display panel further includes an array gate circuit in a peripheral area of ​​the display panel; wherein the interconnected first voltage supply network includes a first peripheral first voltage line in the peripheral area on a first side of the display panel; and an orthographic projection of the first peripheral first voltage line on the base substrate at least partially overlaps with an orthographic projection of the array gate circuit on the base substrate.

[0031] Optionally, the display panel further includes an anode metal layer located on a side of the first peripheral first voltage line away from the array gate circuit; and a cathode layer located on a side of the anode metal layer away from the first peripheral first voltage line; wherein the cathode layer is connected to the anode metal layer through one or more first peripheral through holes in the peripheral region and extending through the third planarization layer, and the anode metal layer is connected to the first peripheral first voltage line through one or more second peripheral through holes in the peripheral region and extending through the second planarization layer, thereby providing the first voltage signal to the cathodes of the plurality of light-emitting elements; the one or more first peripheral through holes connecting the cathode layer and the anode metal layer, and the one or more second peripheral through holes connecting the anode metal layer and the interconnected first voltage supply network are confined to the peripheral region, but not in the display region; and the first peripheral first voltage line and the anode metal layer connected to the first peripheral first voltage line respectively partially surround the display area.

[0032] Optionally, the display panel further includes an interconnected reset signal supply network configured to provide a reset signal to a plurality of pixel driving circuits; wherein the interconnected reset signal supply network includes signal lines in a display area of ​​the display panel.

[0033] Optionally, the interconnected reset signal supply network includes: a plurality of first reset signal lines respectively along a first direction; and a plurality of second reset signal lines respectively along a second direction; wherein the plurality of first reset signal lines respectively intersect with the plurality of second reset signal lines.

[0034] Optionally, a corresponding one of the plurality of first reset signal lines is connected to at least a plurality of the plurality of second reset signal lines; and a corresponding one of the plurality of second reset signal lines is connected to at least a plurality of the plurality of first reset signal lines.

[0035] Optionally, the minimum distance between a corresponding second reset signal line among the multiple second reset signal lines and a corresponding second-first voltage signal line closest to the corresponding second reset signal line among the multiple second-first voltage signal lines is smaller than the minimum distance between the corresponding second reset signal line and a corresponding data line closest to the corresponding second reset signal line among the multiple data lines.

[0036] Alternatively, a total of three data lines and a total of one second-first voltage signal line are between two most adjacent second reset signal lines among the plurality of second reset signal lines.

[0037] Optionally, the display panel includes a base substrate; a semiconductor material layer on the base substrate; a planarization layer located on a side of the semiconductor material layer away from the base substrate; a second signal line layer located on a side of the planarization layer away from the semiconductor material layer; wherein the display panel also includes an interconnected reset signal supply network, the interconnected reset signal supply network is configured to provide a reset signal to a plurality of pixel driving circuits; the interconnected reset signal supply network includes a plurality of first reset signal lines respectively along a first direction and a plurality of second reset signal lines respectively along a second direction; and the semiconductor material layer includes the plurality of first reset signal lines, and the second signal line layer includes the plurality of second reset signal lines.

[0038] Optionally, the plurality of first reset signal lines and the plurality of second reset signal lines are interconnected by second through holes respectively extending through at least the planarization layer; wherein the display panel further comprises: a gate insulation layer located on a side of the semiconductor material layer away from the base substrate; an insulating layer located on a side of the gate insulation layer away from the semiconductor material layer; and an interlayer dielectric layer located on a side of the insulating layer away from the gate insulation layer; wherein the planarization layer is located on a side of the interlayer dielectric layer away from the insulating layer; and the plurality of first reset signal lines and the plurality of second reset signal lines are interconnected by second through holes, each second through hole extending through the planarization layer, the interlayer dielectric layer, the insulating layer and the gate insulation layer.

[0039] Optionally, a corresponding one of the plurality of first reset signal lines is connected to at least a plurality of the plurality of second reset signal lines through a plurality of second through holes extending through at least the planarization layer; and a corresponding one of the plurality of second reset signal lines is connected to at least a plurality of the plurality of first reset signal lines through a plurality of second through holes extending through at least the planarization layer.

[0040] Optionally, the plurality of first reset signal lines comprise semiconductor material; the plurality of second reset signal lines comprise metal material; and the plurality of first reset signal lines and at least active layers of the plurality of thin film transistors are located in the semiconductor material layer and comprise the same semiconductor material.

[0041] Optionally, the display panel also includes an interconnected second voltage supply network, which is configured to provide a second voltage signal to multiple pixel driving circuits; wherein the interconnected second voltage supply network includes: a plurality of first-second voltage signal lines respectively along the first direction; and a plurality of second-second voltage signal lines respectively along the second direction; wherein the plurality of first-second voltage signal lines respectively intersect with the plurality of second-second voltage signal lines.

[0042] Optionally, a corresponding one of the plurality of first-second voltage signal lines is connected to at least a plurality of the plurality of second-second voltage signal lines; and a corresponding one of the plurality of second-second voltage signal lines is connected to at least a plurality of the plurality of first-second voltage signal lines.

[0043] Optionally, the display panel includes: a base substrate; a first signal line layer on the base substrate; a planarization layer located on a side of the first signal line layer away from the base substrate; a second signal line layer located on a side of the planarization layer away from the first signal line layer; wherein the interconnected second voltage supply network includes a plurality of first-second voltage signal lines respectively along the first direction and a plurality of second-second voltage signal lines respectively along the second direction; wherein the first signal line layer includes the plurality of first-second voltage signal lines, and the second signal line layer includes the plurality of second-second voltage signal lines.

[0044] Optionally, the plurality of first-second voltage signal lines and the plurality of second-second voltage signal lines are interconnected by third through-holes respectively extending through the planarization layer; a corresponding one of the plurality of first-second voltage signal lines is connected to at least a plurality of the plurality of second-second voltage signal lines by a plurality of third through-holes respectively extending through the planarization layer; and a corresponding one of the plurality of second-second voltage signal lines is connected to at least a plurality of the plurality of first-second voltage signal lines by a plurality of third through-holes respectively extending through the planarization layer.

[0045] Optionally, a corresponding one of the plurality of first-second voltage signal lines includes: a main body extending in a first direction; a first protrusion protruding away from the main body in a second direction, and a second protrusion protruding away from the first protrusion in the second direction; wherein the second protrusion is connected to the main body through the first protrusion; the first protrusion is a part of the corresponding one of the plurality of first-second voltage signal lines, in which the corresponding one of the plurality of first-second voltage signal lines is connected to the second capacitor electrode; and the second protrusion is a part of the corresponding one of the plurality of first-second voltage signal lines, in which the corresponding one of the plurality of first-second voltage signal lines is connected to the source of the fourth transistor of the corresponding pixel driving circuit, and the drain of the fourth transistor is connected to the source of the driving transistor.

[0046] Optionally, the display panel also includes a plurality of second-second voltage signal lines at least partially in the display area; and a peripheral second voltage signal line in the peripheral area on the second side of the display panel; wherein the interconnected first voltage supply network includes: a plurality of first-first voltage signal lines and a plurality of second-first voltage signal lines at least partially in the display area; and a second peripheral first voltage signal line and a third peripheral first voltage signal line in the peripheral area on the second side of the display panel; wherein one or more of the plurality of second-second voltage signal lines are connected to the peripheral second voltage signal line; one or more of the plurality of second-first voltage signal lines are connected to the second peripheral first voltage signal line; the second peripheral first voltage signal line and the third peripheral first voltage signal line are connected to each other via a plurality of bridges; the plurality of first-first voltage signal lines, the peripheral second voltage signal line and the plurality of bridges are in the first signal line layer; the plurality of second-second voltage signal lines, the second peripheral first voltage signal line are in the second signal line layer; and the third peripheral first voltage signal line includes a first sublayer in the first signal line layer and a second sublayer in the second signal line layer.

[0047] Optionally, the display panel also includes a plurality of gate lines; wherein corresponding gate lines among the plurality of gate lines include a plurality of metal blocks spaced apart from each other in a first conductive layer and metal lines along a first direction in the first signal line layer, and the signal lines along the first direction are respectively connected to the plurality of metal blocks.

[0048] Optionally, the display panel also includes a plurality of first reset control signal lines and a plurality of second reset control signal lines; the corresponding first reset control signal lines and the corresponding second reset control signal lines are respectively configured to reset the gate of the driving transistor and the anode of the corresponding light-emitting element; the corresponding first reset control signal lines include a plurality of first metal blocks spaced apart from each other in the first conductive layer, and a first metal line along a first direction in the first signal line layer, and the first metal lines along the first direction are respectively connected to the plurality of first metal blocks; and the corresponding second reset control signal lines include a plurality of second metal blocks spaced apart from each other in the first conductive layer, and a second metal line along the first direction in the first signal line layer, and the second metal lines along the first direction are respectively connected to the plurality of second metal blocks.

[0049] Optionally, each of the multiple first-first voltage signal lines includes a first linear portion, a second linear portion, and a connecting portion connecting the first linear portion and the second linear portion; the virtual extension portion of the first linear portion intersects with the multiple first metal blocks of the corresponding first reset control signal line; and the orthographic projection of the second linear portion on the base substrate is separated from the orthographic projection of the multiple first metal blocks on the base substrate.

[0050] Optionally, the display panel also includes a second capacitor electrode of a storage capacitor in the second conductive layer; the second capacitor electrode includes an extension portion extending in a direction away from the electrode body of the second capacitor electrode; the orthographic projection of the extension portion on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor of the corresponding pixel driving circuit on the base substrate; and a portion of the extension portion is located between a first node of the corresponding pixel driving circuit and a corresponding data line, and is configured to prevent interference with a signal passing through the corresponding data line to the first node, and the first node is configured to have the same voltage level as the gate of the driving transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The following drawings are examples for illustration purposes only, in accordance with various disclosed embodiments, and are not intended to limit the scope of the invention.

[0052] Figure 1 is a schematic diagram illustrating the structure of a display panel according to some embodiments of the present disclosure.

[0053] Figure 2 is a plan view of a display panel according to some embodiments of the present disclosure.

[0054] Figure 3 is a circuit diagram illustrating a structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0055] Figure 4A is a diagram illustrating the structure of three pixel driving circuits for driving three light-emitting elements of a display panel to emit light according to some embodiments of the present disclosure.

[0056] Figure 4B It shows Figure 4A A diagram showing the structure of semiconductor material layers in a display panel is shown in FIG.

[0057] Figure 4C It shows Figure 4A FIG. 4 is a diagram showing the structure of the first conductive layer in the display panel.

[0058] Figure 4D It shows Figure 4A A diagram showing the structure of the second conductor layer in the display panel is shown in FIG.

[0059] Figure 4E It shows Figure 4A A diagram showing the structure of a first signal line layer in a display panel is shown in FIG.

[0060] Figure 4F It shows Figure 4A A diagram showing the structure of the second signal line layer in the display panel is shown in FIG.

[0061] Figure 4G is a diagram illustrating a structure of a corresponding one of a plurality of first high voltage signal lines according to some embodiments of the present disclosure.

[0062] Figure 4H is a diagram illustrating the layout of an anode of a light-emitting element relative to a pixel driving circuit of a display panel according to some embodiments of the present disclosure.

[0063] Figure 4I is a diagram illustrating the structure of an anode, a first signal line layer, and a second signal line layer in a display panel according to some embodiments of the present disclosure.

[0064] Figure 4J is a diagram illustrating relative positions between a corresponding one of a plurality of first low voltage signal lines and a plurality of first metal blocks of a corresponding first reset control signal line according to some embodiments of the present disclosure.

[0065] Figure 5A It is along Figure 4A Cross-sectional view along line AA'.

[0066] Figure 5B It is along Figure 4A Cross-sectional view along line BB'.

[0067] Figure 5C It is along Figure 4A Cross-sectional view along line CC'.

[0068] Figure 5D It is along Figure 4A Cross-sectional view along line D-D'.

[0069] Figure 5E It is along Figure 4A Cross-sectional view along line EE'.

[0070] Figure 6A is a diagram illustrating the structure of an interconnected low voltage supply network, an interconnected reset signal supply network, and an interconnected high voltage supply network in a display panel according to some embodiments of the present disclosure.

[0071] Figure 6B is a diagram illustrating the structure of an interconnected low voltage supply network in a display panel according to some embodiments of the present disclosure.

[0072] Figure 6C is a diagram illustrating the structure of an interconnected reset signal supply network in a display panel according to some embodiments of the present disclosure.

[0073] Figure 6D is a diagram illustrating the structure of an interconnected high voltage supply network in a display panel according to some embodiments of the present disclosure.

[0074] Figure 7A It shows Figure 1 Schematic diagram of the structure in the first region ZR1.

[0075] Figure 7B It shows Figure 7A FIG. 4 shows a diagram showing a structure of the first signal line layer in the first region ZR1 .

[0076] Figure 7C It shows Figure 7A FIG. 4 shows a diagram showing a structure of the second signal line layer in the first region ZR1 .

[0077] Figure 7D It shows Figure 7A FIG. 4 shows a diagram of a structure of the second planarizing layer in the first region ZR1 .

[0078] Figure 7E It shows Figure 7A FIG. 4 shows a diagram of a structure of the anode layer in the first region ZR1 .

[0079] Figure 7F It shows Figure 7A FIG. 4 is a diagram showing the structure of the third planarization layer in the first region ZR1 .

[0080] Figure 7G It shows Figure 7A FIG. 4 shows a diagram of a structure of a cathode layer in the first region ZR1 .

[0081] Figure 8 It is along Figure 7A Cross-sectional view along the line F-F'.

[0082] Figure 9A IR drop in a display panel according to some embodiments of the present disclosure is shown.

[0083] Figure 9B The IR drop in the associated display panel is shown without an interconnected low voltage supply network.

[0084] Figure 10A It shows Figure 1 Schematic diagram of the structure in the second magnified area ZR2.

[0085] Figure 10B It shows Figure 10A Schematic diagram of the structure of the low-voltage signal line.

[0086] Figure 10C It shows Figure 10A Schematic diagram of the structure of the high-voltage signal line.

[0087] Figure 10D It shows Figure 10A Schematic diagram of the structure of the reset signal line.

[0088] Figure 11A is a diagram illustrating the structure of a first sub-network of an interconnected low voltage supply network in accordance with some embodiments of the present disclosure.

[0089] Figure 11B is a diagram illustrating the structure of a second sub-network of an interconnected low voltage supply network in accordance with some embodiments of the present disclosure.

[0090] Figure 11C is a diagram illustrating the structure of an interconnected low voltage supply network including a first sub-network and a second sub-network according to some embodiments of the present disclosure.

[0091] Figure 12A is a diagram illustrating a structure of a plurality of first low voltage signal lines of an interconnected low voltage supply network according to some embodiments of the present disclosure.

[0092] Figure 12B is a diagram illustrating a structure of a sub-network of a plurality of second low voltage signal lines of an interconnected low voltage supply network according to some embodiments of the present disclosure.

[0093] Figure 12C is a diagram illustrating the structure of an interconnected low voltage supply network in some embodiments according to the present disclosure, the low voltage supply network including a sub-network of a plurality of first low voltage signal lines and a plurality of second low voltage signal lines. DETAILED DESCRIPTION

[0094] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise forms disclosed.

[0095] The present disclosure provides, in particular, a display panel that substantially eliminates one or more problems caused by the limitations and shortcomings of the prior art. In one aspect, the present disclosure provides a display panel comprising a plurality of sub-pixels. Each sub-pixel includes a corresponding light-emitting element and a corresponding pixel driving circuit. In some embodiments, the display panel includes a plurality of light-emitting elements and an interconnected first voltage supply network configured to provide a first voltage signal to the cathodes of the plurality of light-emitting elements. Optionally, the interconnected first voltage supply network includes a signal line in a display area of ​​the display panel. The display area is at least partially surrounded by a peripheral area. The signal line includes a plurality of first signal lines in a first signal line layer and a plurality of second signal lines in a second signal line layer. The display panel also includes a planarization layer located between the first signal line layer and the second signal line layer. The plurality of first signal lines are electrically connected to the plurality of second signal lines. In one example, the first voltage signal line is a low voltage signal line, and the second voltage signal line is a high voltage signal line.

[0096] As used herein, the term "display area" refers to the area of ​​the display panel that actually displays the image. Optionally, the display area may include a sub-pixel area and an inter-sub-pixel area. The sub-pixel area refers to the light-emitting area of ​​the sub-pixel (for example, the area corresponding to the pixel electrode in the liquid crystal display or the area corresponding to the light-emitting layer in the organic light-emitting display). The inter-sub-pixel area refers to the area between adjacent sub-pixel areas, such as the area corresponding to the black matrix in the liquid crystal display or the area corresponding to the pixel defining layer in the organic light-emitting display. Optionally, the inter-sub-pixel area is the area between adjacent sub-pixel areas in the same pixel. Optionally, the inter-sub-pixel area is the area between two adjacent sub-pixel areas in two adjacent pixels.

[0097] As used herein, the term "peripheral area" refers to an area of ​​a display panel where various circuits and wires are provided to transmit signals to the display substrate. To increase the transparency of the display panel, opaque or non-transparent components of the display panel (e.g., a battery, a printed circuit board, a metal frame) may be arranged in the peripheral area rather than in the display area.

[0098] Various suitable light-emitting elements can be used in the array substrate. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes, and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0099] Figure 1 Schematic diagram showing the structure of a display panel according to some embodiments of the present disclosure. Figure 1In some embodiments, the display panel includes an interconnected low-voltage supply network VSSN. The interconnected low-voltage supply network VSSN is configured to provide low-voltage signals to the cathodes of a plurality of light-emitting elements. The interconnected low-voltage supply network VSSN includes signal lines in a display area DA of the display panel. The display panel also includes one or more integrated circuits (e.g., IC1, IC2, IC3, and IC4) in a peripheral area PA. The display panel also includes one or more high-voltage signal lines VDD, one or more reset signal lines VIN, and a gate-on-array circuit GOA.

[0100] In some embodiments, the interconnected low voltage supply network VSSN includes a plurality of first low voltage signal lines Vss1 extending in a first direction DR1 and a plurality of second low voltage signal lines Vss2 extending in a second direction DR2. The first direction DR1 and the second direction DR2 are different from each other. The plurality of first low voltage signal lines Vss1 intersect the plurality of second low voltage signal lines Vss2.

[0101] Figure 2 is a plan view of a display panel according to some embodiments of the present disclosure. Figure 2 , the display panel includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The display panel includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of high-voltage signal lines Vdd. The light emission of each sub-pixel is driven by a corresponding pixel driving circuit PDC. In one example, a high voltage signal is input to a corresponding pixel driving circuit PDC connected to the anode of the light-emitting element through a corresponding one of the plurality of high-voltage signal lines Vdd; a low voltage signal is input to the cathode of the light-emitting element. The voltage difference between the high voltage signal (e.g., VDD signal) and the low voltage signal (e.g., VSS signal) is a driving voltage ΔV, which drives the light emission of the light-emitting element.

[0102] In some embodiments, the display panel includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels include respective first sub-pixels, respective second sub-pixels, respective third sub-pixels, and respective fourth sub-pixels. Optionally, each pixel of the display panel includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. The plurality of sub-pixels in the display panel are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array of an S1-S2-S3-S4 format, where S1 represents each first sub-pixel, S2 represents each second sub-pixel, S3 represents each third sub-pixel, and S4 represents each fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, C3 represents each third sub-pixel of a third color, and C4 represents each fourth sub-pixel of a fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, where C1 represents each first subpixel of a first color, C2 represents each second subpixel of a second color, C3 represents each third subpixel of a third color, and C2' represents each fourth subpixel of the second color. In another example, the C1-C2-C3-C2' format is an RGBG format, where each first subpixel is a red subpixel, each second subpixel is a green subpixel, each third subpixel is a blue subpixel, and each fourth subpixel is a green subpixel.

[0103] In some embodiments, a minimum repeating unit of a plurality of sub-pixels of a display panel includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a driving transistor Td.

[0104] Various suitable pixel drive circuits can be used in this display panel. Examples of suitable drive circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, a corresponding one of the multiple pixel drive circuits is a 7T1C drive circuit. Various suitable light-emitting elements can be used in this display panel. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes, and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0105] Figure 3is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 3 In some embodiments, each pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding first reset control signal line of a plurality of first reset control signal lines rst1, a source connected to a corresponding reset signal line VintN of a current stage of a plurality of reset signal lines, and a drain connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding gate line among a plurality of gate lines GL, a source connected to a corresponding data line among a plurality of data lines DL, and a drain connected to the source of the driving transistor Td; a third transistor T3 having a gate connected to the corresponding gate line, a source connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td. The first transistor T4 has a gate connected to a corresponding light emitting control signal line among the plurality of light emitting control signal lines em, a source connected to a corresponding voltage supply line among the plurality of high voltage signal lines Vdd, and a drain connected to the source of the driving transistor Td and the drain of the second transistor T2. The first transistor T5 has a gate connected to a corresponding light emitting control signal line, a source connected to the drain of the driving transistor Td and the drain of the third transistor T3, and a drain connected to the anode of the light emitting element LE. The sixth transistor T6 has a gate connected to a corresponding second reset control signal line among the plurality of second reset control signal lines rst2, a source connected to a reset signal line Vint(N+1) in the next adjacent stage of the plurality of reset signal lines, and a drain connected to the drain of the fifth transistor and the anode of the light emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the source of the fourth transistor T4.

[0106] refer to Figure 3 In some embodiments, the third transistor T3 is a "dual-gate" transistor, and the first transistor T1 is a "dual-gate" transistor. Optionally, in the "dual-gate" first transistor, the active layer of the first transistor intersects the corresponding reset control signal line twice (alternatively, the corresponding reset control signal line intersects the active layer of the first transistor T1 twice). Similarly, in the "dual-gate" third transistor, the active layer of the third transistor T3 intersects the corresponding gate line among the plurality of gate lines GL twice (alternatively, the corresponding gate line intersects the active layer of the third transistor T3 twice).

[0107] The pixel driving circuit further includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the source of the third transistor T3. The second node N2 is connected to the drain of the fourth transistor T4, the drain of the second transistor T2, and the source of the driving transistor Td. The third node N3 is connected to the drain of the driving transistor Td, the drain of the third transistor T3, and the source of the fifth transistor T5. The fourth node N4 is connected to the drain of the fifth transistor T5, the drain of the sixth transistor T6, and the anode of the light-emitting element LE.

[0108] Figure 4A 1 is a diagram showing the structure of three pixel driving circuits for driving three light emitting elements of a display panel to emit light according to some embodiments of the present disclosure. Figure 4A In some embodiments, the display panel includes a plurality of gate lines GL extending along a first direction DR1, a plurality of data lines DL extending along a second direction DR2, a plurality of first high-voltage signal lines Vdd1 extending along the first direction DR1, a plurality of second high-voltage signal lines Vdd2 extending along the second direction DR2, a plurality of first low-voltage signal lines Vss1 extending along the first direction DR1, a plurality of second low-voltage signal lines Vss2 extending along the second direction DR2, a plurality of first reset signal lines Vint1 extending along the first direction DR1, and a plurality of second reset signal lines Vint2 extending along the second direction DR2. The plurality of first low-voltage signal lines Vss1 intersect with the plurality of second low-voltage signal lines Vss2, respectively. The plurality of first reset signal lines Vint1 intersect with the plurality of second reset signal lines Vint2, respectively. The plurality of first high-voltage signal lines Vdd1 intersect with the plurality of second high-voltage signal lines Vdd2, respectively. Optionally, the display panel further includes a plurality of first reset control signal lines rst1 extending along the first direction DR1; a plurality of second reset control signal lines rst2 extending along the first direction DR1; and a plurality of light emission control signal lines em extending along the first direction DR1. The corresponding positions of the plurality of transistors in each pixel driving circuit are Figure 4A Each pixel driving circuit PDC includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a driving transistor Td.

[0109] Figure 4B It shows Figure 4A A diagram showing the structure of semiconductor material layers in a display panel is shown in FIG. Figure 4C It shows Figure 4A FIG. 4 is a diagram showing the structure of the first conductive layer in the display panel. Figure 4D It shows Figure 4AA diagram showing the structure of the second conductor layer in the display panel is shown in FIG. Figure 4E It shows Figure 4A A diagram showing the structure of a first signal line layer in a display panel is shown in FIG. Figure 4F It shows Figure 4A A diagram showing the structure of the second signal line layer in the display panel is shown in FIG. Figure 5A It is along Figure 4A A cross-sectional view of the line A-A' in the reference Figures 4A to 4F as well as Figure 5A In some embodiments, the display panel includes a base substrate BS, a semiconductor material layer SML on the base substrate BS, a gate insulating layer GI located on a side of the semiconductor material layer SML away from the base substrate BS, a first conductive layer CT1 located on a side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN located on a side of the first conductive layer away from the gate insulating layer GI, a second conductive layer CT2 located on a side of the insulating layer IN away from the first conductive layer CT1, an interlayer dielectric layer ILD located on a side of the second conductive layer CT2 away from the insulating layer IN, a first signal line layer SL1 located on a side of the interlayer dielectric layer ILD away from the second conductive layer CT2, a planarization layer PLN located on a side of the first signal line layer SL1 away from the interlayer dielectric layer ILD, and a second signal line layer SL2 located on a side of the planarization layer PLN away from the first signal line layer SL1.

[0110] Reference Figure 3 、 Figure 4A and Figure 4B In some embodiments, the semiconductor material layer has a unitary structure. Figure 4B, each pixel driving circuit is labeled with a mark indicating the region corresponding to the multiple transistors in each pixel driving circuit, including a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a driving transistor Td. Each pixel driving circuit is also labeled with a mark indicating the components of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a source electrode S1, and a drain electrode D1. The second transistor T2 includes an active layer ACT2, a source electrode S2, and a drain electrode D2. The third transistor T3 includes an active layer ACT3, a source electrode S3, and a drain electrode D3. The fourth transistor T4 includes an active layer ACT4, a source electrode S4, and a drain electrode D4. The fifth transistor T5 includes an active layer ACT5, a source electrode S5, and a drain electrode D5. The sixth transistor T6 includes an active layer ACT6, a source electrode S6, and a drain electrode D6. The driving transistor Td includes an active layer ACTd, a source electrode Sd, and a drain electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of an integral structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), sources (S1, S2, S3, S4, S5, S6, and Sd), and drains (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of an integral structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are in the same layer. In another example, the active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6 and ACTd), sources (S1, S2, S3, S4, S5, S6, Ss and Sd) and drains (D1, D2, D3, D4, D5, D6 and Dd) of the transistors (T1, T2, T3, T4, T5, T6 and Td) are in the same layer.

[0111] Reference Figure 4B In some embodiments, the overall structure of the semiconductor material layer further includes a plurality of first reset signal lines Vint1. The plurality of first reset signal lines Vint1 are located in the same layer as at least active layers (e.g., ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of one or more transistors (e.g., T1, T2, T3, T4, T5, T6, and Td).

[0112] As used herein, an active layer refers to a component of a transistor including at least a portion of a semiconductor material layer, the orthographic projection of at least a portion of the semiconductor material layer on the base substrate overlapping with the orthographic projection of the gate on the base substrate. As used herein, a source refers to a component of a transistor connected to one side of the active layer, and a drain refers to a component of a transistor connected to the other side of the active layer. In the case of a dual-gate transistor (e.g., a third transistor T3), an active layer refers to a component of a transistor including a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first portion and the second portion, the orthographic projection of the first portion of the semiconductor material layer on the base substrate overlapping with the orthographic projection of the first gate on the base substrate, and the orthographic projection of the second portion of the semiconductor material layer on the base substrate overlapping with the orthographic projection of the second gate on the base substrate. In the case of a dual-gate transistor, a source refers to a component of the transistor connected to the first portion on a side away from the third portion, and a drain refers to a component of the transistor connected to the second portion on a side away from the third portion.

[0113] Reference Figure 3 、 Figure 4A and Figure 4C In some embodiments, the first conductive layer includes the gate G1 of the first transistor T1, the gate G3 of the third transistor T3, the gate G6 of the sixth transistor T6, a plurality of light-emitting control signal lines em, and the first capacitor electrode Ce1 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the gate G1 of the first transistor T1, the gate G3 of the third transistor T3, the gate G6 of the sixth transistor T6, the plurality of light-emitting control signal lines em, and the first capacitor electrode Ce1 are in the same layer.

[0114] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when multiple light-emitting control signal lines em and the first capacitor electrode Ce1 are formed by one or more steps of the same patterning process performed in the same material layer, the multiple light-emitting control signal lines em and the first capacitor electrode Ce1 are located in the same layer. In another example, by performing the steps of forming the multiple light-emitting control signal lines em and forming the first capacitor electrode Ce1 simultaneously, the multiple light-emitting control signal lines em and the first capacitor electrode Ce1 can be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same.

[0115] In some embodiments, a corresponding gate line of the plurality of gate lines includes a plurality of metal blocks (eg, Figure 4C G3 in ), and metal lines along the first direction in the first signal line layer (eg, Figure 4E The gate lines along the first direction are connected to the plurality of metal blocks. The metal lines in the first signal line layer can be made of a metal material having a relatively low resistance compared to the metal material in the first conductive layer. This design can reduce the total resistance of the gate lines.

[0116] In some embodiments, reference Figures 4A to 4C and Figure 5A Each metal block in the plurality of metal blocks G3 has an L-shape. The orthographic projection of the first channel portion of the active layer ACT3 of the third transistor T3 on the base substrate BS overlaps with the orthographic projection of the first metal portion of the corresponding metal block in the plurality of metal blocks G3 on the base substrate BS. The orthographic projection of the second channel portion of the active layer ACT3 of the third transistor T3 on the base substrate BS overlaps with the orthographic projection of the second metal portion of the corresponding metal block in the plurality of metal blocks G3 on the base substrate BS. The first metal portion and the second metal portion serve as the first and second gate electrodes of the third transistor T3.

[0117] Reference Figure 3 、 Figure 4A and Figure 4D In some embodiments, the second conductive layer includes a second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc.

[0118] refer to Figure 3 、 Figure 4A and Figure 4E In some embodiments, the first signal line layer includes a plurality of first low voltage signal lines Vss1, a plurality of first reset control signal lines rst1, a plurality of gate lines GL, a plurality of first high voltage signal lines Vdd1, a plurality of second reset control signal lines rst2 and a node connection line Cln. Figure 5A, the node connection line Cln connects the first capacitor electrode Ce1 in each pixel driving circuit to the source electrode S3 of the third transistor T3. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, multiple first low voltage signal lines Vss1, multiple first reset control signal lines rst1, multiple gate lines GL, multiple first high voltage signal lines Vdd1, multiple second reset control signal lines rs2 and the node connection line Cln are in the same layer.

[0119] In some embodiments, each first reset control signal line rst1 includes a plurality of first metal blocks spaced apart from one another in a first conductive layer, and first metal wires along a first direction in a first signal line layer, wherein the first metal wires along the first direction are respectively connected to the plurality of first metal blocks. In some embodiments, each second reset control signal line includes a plurality of second metal blocks spaced apart from one another in the first conductive layer, and second metal wires along the first direction in the first signal line layer, wherein the second metal wires along the first direction are respectively connected to the plurality of second metal blocks.

[0120] In some embodiments, each of the plurality of first low voltage signal lines Vss1 includes a first linear portion, a second linear portion, and a connecting portion connecting the first linear portion and the second linear portion. The virtual extension portion of the first linear portion is connected to the plurality of first metal blocks (e.g., Figure 4C The virtual extension portion of the second linear portion is spaced apart from the plurality of first metal blocks, for example, not intersecting with the plurality of first metal blocks (for example, Figure 4C The orthographic projection of the second linear portion on the base substrate is spaced apart from the orthographic projections of the plurality of first metal blocks. Figure 4J FIG2 is a diagram illustrating relative positions between a corresponding one of a plurality of first low voltage signal lines and a plurality of first metal blocks of a corresponding first reset control signal line according to some embodiments of the present disclosure. Figure 4JEach of the plurality of first low-voltage signal lines Vss1 includes a first linear portion LP1, a second linear portion LP2, and a connection portion CP connecting the first linear portion LP1 and the second linear portion LP2. A dummy extension portion VE of the first linear portion LP1 intersects with the plurality of first metal blocks (G1) of each first reset control signal line rst1. A dummy extension portion of the second linear portion LP2 is spaced apart from the plurality of first metal blocks, for example, does not intersect with the plurality of first metal blocks (G1) of each first reset control signal line rst1.

[0121] Reference Figure 3 、 Figure 4A and Figure 4F In some embodiments, the second signal line layer includes a plurality of data lines DL, a plurality of second low voltage signal lines Vss2, a plurality of second reset signal lines Vint2, and a plurality of second high voltage signal lines Vdd2. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the plurality of data lines DL, the plurality of second low voltage signal lines Vss2, the plurality of second reset signal lines Vint2, and the plurality of second high voltage signal lines Vdd2 are in the same layer.

[0122] See Figure 4F In some embodiments, the minimum distance between a corresponding second reset signal line of the plurality of second reset signal lines Vint2 and the corresponding second low-voltage signal line closest to the corresponding second reset signal line among the plurality of second low-voltage signal lines Vss2 is less than the minimum distance between the corresponding second reset signal line and the corresponding data line closest to the corresponding second reset signal line among the plurality of data lines DL. In some embodiments, a total of three data lines and a total of one second low-voltage signal line are located between the two closest second reset signal lines among the plurality of second reset signal lines Vint2. Alternatively, a total of three data lines, a total of one second low-voltage signal line, and a total of three second high-voltage signal lines are located between the two closest second reset signal lines among the plurality of second reset signal lines Vint2.

[0123] Reference Figure 3 、 Figure 4D 、 Figure 4E and Figure 5AIn some embodiments, the orthographic projection of the second capacitor electrode Ce2 on the base substrate BS completely covers the orthographic projection of the first capacitor electrode Ce1 on the base substrate BS, leaving a margin, except for the hole region H where a portion of the second capacitor electrode Ce2 is absent. In some embodiments, the first signal line layer includes a node connection line Cln located on a side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The node connection line Cln is located in the same layer as the plurality of first low voltage signal lines Vss1, the plurality of first reset control signal lines rst1, the plurality of gate lines GL, the plurality of first high voltage signal lines Vdd1, and the plurality of second reset control signal lines rst2. Optionally, the display panel further includes a first connection via cv1 located in the hole region H and extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first connection via cv1. In some embodiments, the first capacitor electrode Ce1 is located on a side of the gate insulating layer GI away from the base substrate BS. Optionally, the display panel further includes a first connection through hole cv1 and a second connection through hole cv2. The first connection through hole cv1 is located in the hole area H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second connection through hole cv2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first connection through hole cv1, and the node connection line Cln is connected to the semiconductor material layer SML through the second connection through hole cv2. Optionally, the node connection line Cln is connected to the source S3 of the third transistor T3, as shown in FIG. Figure 5A shown.

[0124] In some embodiments, reference Figure 4D , the second capacitor electrode Ce2 includes an extension portion E, which extends away from the electrode body emb of the second capacitor electrode Ce2. Figure 4A The orthographic projection of the extension E on the base substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor T3 of the corresponding pixel driving circuit. A portion of the extension E is located between the first node N1 of the corresponding pixel driving circuit and a corresponding data line among the plurality of data lines DL, and is configured to prevent interference with the first node N1 by a signal passing through the corresponding data line. A portion of the extension E is located between the node connection line Cln and a corresponding data line among the plurality of data lines DL.

[0125] The active layer of the third transistor can be protected from radiation by providing the extension E. Since the extension E is part of the second capacitor electrode, the extension E has a stable voltage level and does not need to be electrically connected to a signal line having a stable voltage level.

[0126] Reference Figures 4A to 4FThe third transistor T3 includes a first gate and a second gate. The orthographic projection of the first gate on the base substrate overlaps with the orthographic projection of the first channel portion of the active layer ACT3 of the third transistor T3 on the base substrate. The orthographic projection of the second gate on the base substrate overlaps with the orthographic projection of the second channel portion of the active layer ACT3 of the third transistor T3 on the base substrate. The active layer ACT3 of the third transistor T3 also includes a portion connecting the first channel portion and the second channel portion. The orthographic projection of the extension E on the base substrate at least partially overlaps with the orthographic projection of the portion connecting the first channel portion and the second channel portion on the base substrate.

[0127] In some embodiments, the extension portion E includes a first extension portion extending along the first direction DR1 and a second extension portion extending along the second direction DR2. The first extension portion connects the second extension portion to the electrode body emb of the second capacitor electrode Ce2. In some embodiments, an orthographic projection of the second extension portion on the base substrate at least partially overlaps with an orthographic projection of the active layer ACT3 of the third transistor T3 of each pixel driving circuit on the base substrate.

[0128] In some embodiments, the second extending portion includes a shielding portion and a non-shielding portion. The orthographic projection of the shielding portion on the base substrate at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 of each pixel driving circuit on the base substrate. The orthographic projection of the non-shielding portion on the base substrate does not overlap with the orthographic projection of the active layer ACT3 of the third transistor T3 of each pixel driving circuit on the base substrate. The line width of the shielding portion is greater than the line width of the non-shielding portion to ensure that the active layer ACT3 of the third transistor T3 of each pixel driving circuit is shielded.

[0129] In some embodiments, the first extension portion is located between the node connection line Cln and a corresponding data line among the plurality of data lines DL. The first extension portion located between the node connection line Cln and the corresponding data line is configured to prevent a signal passing through the corresponding data line from interfering with the first node N1.

[0130] In some embodiments, an orthographic projection of the first extension portion on a line extending in the second direction at least partially overlaps an orthographic projection of the node connection line on the line. The first extension portion is configured to prevent interference of a signal transmitted in the first direction on the first node N1.

[0131] In some embodiments, an orthographic projection of a corresponding one of the plurality of second high-voltage signal lines Vdd2 on the base substrate overlaps an orthographic projection of the node connection line Cln on the base substrate. By shielding the node connection line Cln with the corresponding one of the plurality of second high-voltage signal lines Vdd2, the voltage level at the node N1 can be stabilized because a constant voltage level is provided to the corresponding one of the plurality of second high-voltage signal lines Vdd2.

[0132] In some embodiments, an orthographic projection of a corresponding one of the plurality of second high-voltage signal lines Vdd2 on the base substrate at least partially overlaps an orthographic projection of at least one gate of the third transistor T3 on the base substrate. By shielding at least one gate of the third transistor T3 with a corresponding one of the plurality of second high-voltage signal lines Vdd2, the voltage level at the node N1 can be further stabilized.

[0133] Figure 6A is a diagram showing the structure of an interconnected low voltage supply network, an interconnected reset signal supply network, and an interconnected high voltage supply network in a display panel according to some embodiments of the present disclosure. The interconnected low voltage supply network includes a signal line in the display area of ​​the display panel. The interconnected low voltage supply network is configured to provide a low voltage signal to the cathodes of a plurality of light emitting elements. The interconnected reset signal supply network is configured to provide a reset signal to a plurality of pixel drive circuits. The interconnected reset signal supply network includes a signal line in the display area of ​​the display panel. The interconnected high voltage supply network is configured to provide a high voltage signal to a plurality of pixel drive circuits. The interconnected high voltage supply network includes a signal line in the display area of ​​the display panel. In one example, the first voltage signal line is a low voltage signal line, and the second voltage signal line is a high voltage signal line.

[0134] Figure 6B is a diagram illustrating the structure of an interconnected low voltage supply network in a display panel according to some embodiments of the present disclosure. Figure 6A and Figure 6B In some embodiments, the interconnected low-voltage supply network includes a plurality of first low-voltage signal lines Vss1 extending along a first direction DR1 and a plurality of second low-voltage signal lines Vss2 extending along a second direction DR2. The plurality of first low-voltage signal lines Vss1 intersect with the plurality of second low-voltage signal lines Vss2. A corresponding one of the plurality of first low-voltage signal lines Vss1 is connected to at least multiple of the plurality of second low-voltage signal lines Vss2. A corresponding one of the plurality of second low-voltage signal lines Vss2 is connected to at least multiple of the plurality of first low-voltage signal lines Vss1.

[0135] Figure 5B It is along Figure 4A Cross-sectional view of line BB' in FIG. Figure 5B 、 Figure 6A and Figure 6BIn some embodiments, the first signal line layer SL1 includes a plurality of first low-voltage signal lines Vss1, and the second signal line layer SL2 includes a plurality of second low-voltage signal lines Vss2. The plurality of first low-voltage signal lines Vss1 and the plurality of second low-voltage signal lines Vss2 are interconnected through first through-holes v1s respectively extending through the planarization layer PLN. At least some of the first through-holes are in the display area. A corresponding one of the plurality of first low-voltage signal lines Vss1 is connected to at least a plurality of the plurality of second low-voltage signal lines Vss2 through a plurality of first through-holes respectively extending through the planarization layer PLN. A corresponding one of the plurality of second low-voltage signal lines Vss2 is connected to at least a plurality of the plurality of first low-voltage signal lines Vss1 through a plurality of first through-holes respectively extending through the planarization layer PLN.

[0136] Figure 6C FIG. 1 is a diagram illustrating the structure of an interconnected reset signal supply network in a display panel according to some embodiments of the present disclosure. Figure 6A and Figure 6C In some embodiments, the interconnected reset signal supply network includes a plurality of first reset signal lines Vint1 extending along a first direction DR1 and a plurality of second reset signal lines Vint2 extending along a second direction DR2. The plurality of first reset signal lines Vint1 intersect the plurality of second reset signal lines Vint2. A corresponding one of the plurality of first reset signal lines Vint1 is connected to at least a plurality of the plurality of second reset signal lines Vint2. A corresponding one of the plurality of second reset signal lines Vint2 is connected to at least a plurality of the plurality of first reset signal lines Vint1.

[0137] Figure 5C It is along Figure 4A Cross-sectional view of line C-C' in FIG. Figure 5C 、 Figure 6A and Figure 6CIn some embodiments, the semiconductor material layer SML includes a plurality of first reset signal lines Vint1, and the second signal line layer SL2 includes a plurality of second reset signal lines Vint2. The plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2 are interconnected via second vias v2s, each extending through at least the planarization layer PLN. In one example, the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2 are interconnected via second vias v2s, each of which extends through the planarization layer PLN, the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. A corresponding one of the plurality of first reset signal lines Vint1 is connected to at least a plurality of the plurality of second reset signal lines Vint2 via a plurality of second vias extending through at least the planarization layer PLN. A corresponding one of the plurality of second reset signal lines Vint2 is connected to at least a plurality of the plurality of first reset signal lines Vint1 via a plurality of second vias extending through at least the planarization layer PLN.

[0138] Optionally, the plurality of first reset signal lines Vint1 include a semiconductor material; and the plurality of second reset signal lines Vint2 include a metal material. Optionally, the plurality of first reset signal lines Vint1 and at least active layers (e.g., ACTd and ACT1 to ACT6) of the plurality of thin film transistors (e.g., Td and T1 to T6) are located in the semiconductor material layer SML and include the same semiconductor material.

[0139] Alternatively, the reset signal line (one or both of the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2) may be provided in the first conductive layer. Alternatively, the reset signal line (one or both of the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2) may be provided in the first signal line layer. Alternatively, the reset signal line (one or both of the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2) may be provided in the second conductive layer. Alternatively, the reset signal line (one or both of the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2) may be provided in the second signal line layer. Alternatively, the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2 are located in the same layer and are interconnected to form a network.

[0140] Figure 6D FIG is a diagram showing the structure of an interconnected high voltage supply network in a display panel according to some embodiments of the present disclosure. Figure 6A and Figure 6DIn some embodiments, the interconnected high voltage supply network includes a plurality of first high voltage signal lines Vdd1 extending along a first direction DR1 and a plurality of second high voltage signal lines Vdd2 extending along a second direction DR2. The plurality of first high voltage signal lines Vdd1 intersect the plurality of second high voltage signal lines Vdd2. A corresponding one of the plurality of first high voltage signal lines Vdd1 is connected to at least a plurality of the plurality of second high voltage signal lines Vdd2. A corresponding one of the plurality of second high voltage signal lines Vdd2 is connected to at least a plurality of the plurality of first high voltage signal lines Vdd1.

[0141] Figure 5D It is along Figure 4A Cross-sectional view of line D-D' in FIG. Figure 5D 、 Figure 6A and Figure 6D In some embodiments, the first signal line layer SL1 includes a plurality of first high-voltage signal lines Vdd1, and the second signal line layer SL2 includes a plurality of second high-voltage signal lines Vdd2. A corresponding one of the plurality of first high-voltage signal lines Vdd1 is connected to the second capacitor electrode via one or more third vias v3s extending through the interlayer dielectric layer ILD. A corresponding one of the plurality of first high-voltage signal lines Vdd1 is connected to at least a plurality of the plurality of second high-voltage signal lines Vdd2 via a plurality of third vias extending through the planarization layer PLN. A corresponding one of the plurality of second high-voltage signal lines Vdd2 is connected to at least a plurality of the plurality of first high-voltage signal lines Vdd1 via a plurality of third vias extending through the planarization layer PLN. By connecting the second capacitor electrode to a corresponding one of the plurality of first high-voltage signal lines Vdd1, the resistance of the corresponding one of the plurality of first high-voltage signal lines Vdd1 can be reduced.

[0142] Figure 5E It is along Figure 4A Cross-sectional view of line E-E' in FIG. Figure 5E 、 Figure 6A and Figure 6DIn some embodiments, the first signal line layer SL1 includes a plurality of first high-voltage signal lines Vdd1, and the second signal line layer SL2 includes a plurality of second high-voltage signal lines Vdd2. A corresponding one of the plurality of first high-voltage signal lines Vdd1 is connected to the second capacitor electrode via one or more third vias v3s extending through the interlayer dielectric layer ILD, respectively. A corresponding one of the plurality of second high-voltage signal lines Vdd2 is connected to a corresponding one of the plurality of first high-voltage signal lines Vdd1 via one or more fourth vias v4s extending through the planarization layer PLN, respectively. A corresponding one of the plurality of first high-voltage signal lines Vdd1 is connected to the source S4 of the fourth transistor via a third connection via cv4 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0143] Figure 4G FIG. 1 is a diagram illustrating a structure of a corresponding one of a plurality of first high voltage signal lines according to some embodiments of the present disclosure. Figure 4G In some embodiments, a corresponding one of the plurality of first high-voltage signal lines Vdd1 includes a body md extending in a first direction DR1, a first protrusion pd1 protruding away from the body md in a second direction DR2, and a second protrusion pd2 protruding away from the first protrusion pd1 in the second direction DR2. The second protrusion pd2 is connected to the body md via the first protrusion pd1. The first protrusion pd1 is a portion of the corresponding one of the plurality of first high-voltage signal lines Vdd1, where the corresponding one of the plurality of first high-voltage signal lines Vdd1 is connected to the second capacitor electrode. The second protrusion pd2 is a portion of the corresponding one of the plurality of first high-voltage signal lines Vdd1, where the corresponding one of the plurality of first high-voltage signal lines Vdd1 is connected to the source of the fourth transistor. The second protrusion pd2 is a portion of the corresponding one of the plurality of second high-voltage signal lines Vdd2, where the corresponding one of the plurality of second high-voltage signal lines Vdd2 is connected to the corresponding one of the plurality of first high-voltage signal lines Vdd1 via one or more vias. The drain of the fourth transistor is connected to the source of the driver transistor.

[0144] Figure 4H is a diagram illustrating the layout of an anode of a light-emitting element relative to a pixel driving circuit of a display panel according to some embodiments of the present disclosure. Figure 4I 1 is a diagram showing the structure of an anode, a first signal line layer, and a second signal line layer in a display panel according to some embodiments of the present disclosure. Figure 4H and Figure 4I ,In some embodiments, the display panel further includes a plurality of anodes of a plurality of light emitting elements, e.g. Figure 4HAs shown in FIG, a first anode AD1, a second anode AD2 and a third anode AD3. Each anode extends through the second planarization layer (eg, Figures 5A to 5E The anode contact pad is connected to the anode contact pad by a through hole extending through the planarization layer (e.g., Figures 5A to 5E The relay electrode is connected to the N4 node (eg, the drain of the fifth transistor) through a via extending through the interlayer dielectric layer.

[0145] refer to Figure 4H 、 Figure 4I 、 Figure 4E and Figure 4F In one example, the first anode AD1 is connected to the first anode contact pad ACP1 through a through hole extending through the second planarization layer, and the first anode contact pad ACP1 is connected to the first relay electrode RE1 through a through hole extending through the planarization layer; the second anode AD2 is connected to the second anode contact pad ACP2 through a through hole extending through the second planarization layer, and the second anode contact pad ACP2 is connected to the second relay electrode RE2 through a through hole extending through the planarization layer; the third anode AD3 is connected to the third anode contact pad ACP3 through a through hole extending through the second planarization layer, and the third anode contact pad ACP3 is connected to the third relay electrode RE3 through a through hole extending through the planarization layer.

[0146] In some embodiments, reference Figure 1 The display panel further comprises an array gate circuit GOA located in the peripheral area PA of the display panel. The interconnected low voltage supply network VSSN comprises a first peripheral low voltage line pvss1 in the peripheral area PA on a first side S1 of the display panel. Figure 7A It shows Figure 1 Schematic diagram of the structure in the first region ZR1. Figure 7B It shows Figure 7A FIG. 4 shows a diagram showing a structure of the first signal line layer in the first region ZR1 . Figure 7C It shows Figure 7A FIG. 4 shows a diagram showing a structure of the second signal line layer in the first region ZR1 . Figure 7D It shows Figure 7A FIG. 4 shows a diagram of a structure of the second planarizing layer in the first region ZR1 . Figure 7E It shows Figure 7A FIG. 4 shows a diagram of a structure of the anode layer in the first region ZR1 .

[0147] Figure 7F It shows Figure 7A A diagram showing the structure of the third planarization layer in the first region ZR1. Figure 7G It shows Figure 7AThe structure of the cathode layer in the first region ZR1 is shown in FIG. Figures 7A to 7G as well as Figure 1 , in the peripheral area PA on the first side S1 of the display panel, the display panel includes an array gate circuit GOA located in a first signal line layer on a base substrate, a first peripheral low voltage line pvss1 located in a second signal line layer on a side of the array gate circuit GOA away from the base substrate, a second planarization layer PLN2 located on a side of the first peripheral low voltage line pvss1 away from the array gate circuit GOA, an anode metal layer AML located in the anode layer on a side of the second planarization layer PLN2 away from the first peripheral low voltage line pvss1, a third planarization layer PLN3 located on a side of the anode metal layer AML away from the second planarization layer PLN2, and a cathode layer CDL located on a side of the third planarization layer PLN3 away from the anode metal layer AML.

[0148] Figure 8 It is along Figure 7A Cross-sectional view of line F-F' in FIG. Figure 1 、 Figure 7A and Figure 8 In some embodiments, the orthographic projection of the first peripheral low-voltage line pvss1 on the base substrate BS at least partially overlaps with the orthographic projection of the array gate circuit GOA on the base substrate BS. Optionally, the orthographic projection of the first peripheral low-voltage line pvss1 on the base substrate BS overlaps with the orthographic projection of the array gate circuit GOA on the base substrate BS by at least 80% (e.g., at least 85%, at least 90%, at least 95%, at least 99%).

[0149] refer to Figure 8 , the cathode layer CDL is connected to the anode metal layer AML through one or more first peripheral through holes pv1 in the peripheral area and extending through the third planarization layer PLN3, and the anode metal layer AML is connected to the first peripheral first voltage line pvss1 through one or more second peripheral through holes pv2 in the peripheral area and extending through the second planarization layer PLN2, thereby providing a first voltage signal to the cathodes of the plurality of light emitting elements. The display panel includes a plurality of first gas release through holes grv1 extending through the first peripheral first voltage line pvss1 for releasing gas in the underlying insulating layer (e.g., the planarization layer PLN) during the manufacturing process of the display panel. The display panel also includes a plurality of second gas release through holes grv2 extending through the anode metal layer AML to release gas in the underlying insulating layer (e.g., the second planarization layer PLN2) during the manufacturing process of the display panel.

[0150] In some embodiments, the cathode layer CDL is a unitary cathode layer extending substantially across the entire display panel and serves as the cathode for multiple light-emitting elements. Optionally, one or more vias connecting the cathode layer CDL and the anode metal layer AML are confined to the peripheral area PA and not the display area DA. The cathode layer CDL is connected to the interconnected low-voltage supply network VSSN only through the anode metal layer AML.

[0151] In this display panel, the low-voltage lines share the same space as the array gate circuit GOA. The display panel can be manufactured with a very narrow bezel. In one example, the display panel has a bezel width of approximately 1.5 mm on the first side S1 (or the side opposite to the first side S1), compared to 2.5 mm in related display panels.

[0152] Furthermore, in the present display panel, the connection between the low voltage line and the cathode layer CDL (via the anode metal layer) can be made only in the peripheral area PA (e.g., in the GOA area), thereby eliminating the need to manufacture through-holes (or any process) in the display area DA to connect the low voltage line and the cathode layer CDL. The display panel can be manufactured with much lower complexity, significantly reducing the occurrence of defects in the display panel.

[0153] The inventors of the present disclosure have discovered that, surprisingly and unexpectedly, the implementation of an interconnected low voltage supply network significantly reduces the extent of voltage drops in low voltage signals (eg, VSS signals) across the display panel. Figure 9A IR drop in a display panel according to some embodiments of the present disclosure is shown. Figure 9B The IR drop in the relevant display panel is shown without an interconnected low voltage supply network. Figure 9A and Figure 9B The darkness indicates the degree of IR drop in the local area. Figure 9A and Figure 9B Compared to the voltage drop in a related display panel without an interconnected low voltage supply network, the voltage drop in the embodiment of the present disclosure is significantly reduced. Overall, the IR drop is reduced from 1.5641V to 1.2337V (a reduction of more than 20%). The advantages of the present display panel are particularly significant for large-sized display panels. In a related display panel without an interconnected low voltage supply network, such as Figure 9B As shown, VSS current is concentrated at the two outermost ports, leading to problems such as high current burns. For example, in a related display panel without an interconnected low-voltage supply network, the VSS current at the outermost ports is approximately 26.6% of the total VSS current. In display panels according to some embodiments of the present disclosure, the VSS current at any port is less than 11% of the total VSS current, avoiding the problem of high current burns.

[0154] In order to adapt to the implementation of the interconnected network in this display panel, the layers and signal lines in the peripheral area adopt a novel and unique structure, which is conducive to further reducing the border width, improving the voltage uniformity of the entire display panel, and minimizing the occurrence of defects in the display panel. Figure 10A It shows Figure 1 Schematic diagram of the structure in the second magnified area ZR2. Figure 10B It shows Figure 10A Schematic diagram of the structure of medium and low voltage signal lines. Figure 10C It shows Figure 10A Schematic diagram of the structure of the high voltage signal line in. Figure 1 、 Figure 10A 、 Figure 10B as well as Figure 10C In some embodiments, the display panel includes a peripheral high voltage signal line pvdd, a second peripheral low voltage signal line pvss2, and a third peripheral low voltage signal line pvss3 located in the peripheral area PA on the second side S2 of the display panel. One or more of the plurality of second high voltage signal lines Vdd2 are connected to the peripheral high voltage signal line pvdd. One or more of the plurality of second low voltage signal lines Vss2 are connected to the second peripheral low voltage signal line pvss2. The second peripheral low voltage signal line pvss2 and the third peripheral low voltage signal line pvss3 are connected to each other by a plurality of bridges bg. Optionally, the plurality of first low voltage signal lines, the peripheral high voltage signal line pvdd, and the plurality of bridges are located within the first signal line layer SL1 (for example, reference Figure 5A (Optionally, a plurality of second high voltage signal lines Vdd2 and second peripheral low voltage signal lines pvss2 are located in the second signal line layer SL2. Optionally, a third peripheral low voltage signal line pvss3 includes a first sublayer in the first signal line layer SL1 and a second sublayer in the second signal line layer SL2.)

[0155] Figure 10D It shows Figure 10A Schematic diagram of the reset signal line structure in . Figure 1 、 Figure 10A and Figure 10DIn some embodiments, the display panel includes a peripheral reset signal line pvint located in the peripheral area PA on the second side S2 of the display panel. One or more of the plurality of second reset signal lines Vint2 are connected to the peripheral reset signal line pvint. Optionally, the peripheral reset signal line pvint is located in a different layer from the peripheral high voltage signal line pvdd and the peripheral low voltage signal line pvss2. Optionally, the peripheral reset signal line pvint is located in the same layer as the plurality of second reset signal lines Vint2. Optionally, the peripheral reset signal line pvint is located in a different layer from the plurality of second reset signal lines Vint2. In some embodiments, the peripheral reset signal line pvint includes a first portion p1 and a second portion p2. Optionally, the first portion p1 includes a single layer of conductive material in the same layer as the second signal line layer. Optionally, the second portion has a double-layer structure, and the double-layer structure includes conductive materials located in the first signal line layer and the second signal line layer, respectively.

[0156] Reference Figure 10A In some embodiments, the display panel further comprises an anode metal layer AML. In some embodiments, the anode metal layer AML is connected to the peripheral low voltage signal line pvss2 via a via extending through one or more insulating layers.

[0157] Various suitable implementations of interconnected low voltage supply networks may be practiced in accordance with the present disclosure. Figure 11A is a diagram illustrating the structure of a first sub-network of an interconnected low voltage supply network in accordance with some embodiments of the present disclosure. Figure 11B is a diagram illustrating the structure of a second sub-network of an interconnected low voltage supply network in accordance with some embodiments of the present disclosure. Figure 11C is a diagram illustrating the structure of an interconnected low voltage supply network including a first sub-network and a second sub-network according to some embodiments of the present disclosure. Figures 11A to 11C In some embodiments, the interconnected low-voltage supply network includes a first sub-network formed by a plurality of first low-voltage signal lines Vss1 and a second sub-network formed by a plurality of second low-voltage signal lines Vss2. Optionally, the first sub-network is located in a first signal line layer, and the second sub-network is located in a second signal line layer. The plurality of first signal lines Vss1 are electrically connected to the plurality of second signal lines Vss2.

[0158] In some embodiments, the plurality of first low voltage signal lines Vss1 form a subnet, while the plurality of second low voltage signal lines Vss2 do not form a subnet. In some embodiments, the plurality of second low voltage signal lines Vss2 form a subnet, while the plurality of first low voltage signal lines Vss1 do not form a subnet.

[0159] Figure 12Ais a diagram illustrating a structure of a plurality of first low voltage signal lines of an interconnected low voltage supply network according to some embodiments of the present disclosure. Figure 12B is a diagram illustrating a structure of a sub-network of a plurality of second low voltage signal lines of an interconnected low voltage supply network according to some embodiments of the present disclosure. Figure 12C is a diagram illustrating a structure of an interconnected low voltage supply network according to some embodiments of the present disclosure, the low voltage supply network including a sub-network of a plurality of first low voltage signal lines and a plurality of second low voltage signal lines. 12A to 12C The plurality of first low voltage signal lines Vss1 are separated from each other and do not form a sub-network, while the plurality of second low voltage signal lines Vss2 form a sub-network. The plurality of first signal lines Vss1 are electrically connected to the plurality of second signal lines Vss2.

[0160] In another aspect, the present invention provides a display device comprising a display panel as described herein or manufactured by the methods described herein, and one or more integrated circuits connected to the display panel. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptops, digital photo albums, GPS devices, and the like. Optionally, the display device is an organic light-emitting diode display device. Optionally, the display device is a liquid crystal display device.

[0161] In another aspect, the present invention provides a method for manufacturing a display panel. In some embodiments, the method includes forming a plurality of light-emitting elements; and forming an interconnected low-voltage supply network configured to provide a low-voltage signal to cathodes of the plurality of light-emitting elements. Optionally, forming the interconnected low-voltage supply network includes forming a signal line in a display area of ​​the display panel.

[0162] The foregoing description of the embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and various modifications as are suited to the particular use or implementation contemplated. The scope of the present invention is intended to be defined by the appended claims and their equivalents, in which all terms are to be used in their broadest reasonable sense unless otherwise indicated. Therefore, the terms "the invention," "the present invention," etc. do not necessarily limit the scope of the claims to specific embodiments, and reference to exemplary embodiments of the present invention is not intended to limit the invention, and no such limitation should be inferred. The present invention is limited solely by the spirit and scope of the appended claims. Furthermore, the claims may use the terms "first," "second," etc., followed by a noun or element. These terms should be understood as nomenclature and should not be construed as limiting the number of elements to which they refer unless a specific number is provided. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, no element or component in this disclosure is intended to be dedicated to the public, regardless of whether the element or component is explicitly stated in the appended claims.

Claims

1. A display panel comprising a base substrate and a plurality of sub-pixels, each sub-pixel comprising a corresponding light-emitting element and a corresponding pixel driving circuit; in, The corresponding pixel driving circuit includes: a third transistor; the third transistor including a first gate and a second gate; an orthographic projection of the first gate on the base substrate overlapping with an orthographic projection of a first channel portion of an active layer of the third transistor on the base substrate; an orthographic projection of the second gate on the base substrate overlapping with an orthographic projection of a second channel portion of an active layer of the third transistor on the base substrate; the active layer of the third transistor further including a portion connecting the first channel portion and the second channel portion; a storage capacitor including a first capacitor electrode located in the first conductive layer and a second capacitor electrode located in the second conductive layer; Wherein, the second conductive layer is located on a side of the first conductive layer away from the base substrate; the second capacitor electrode including an extension portion extending in a direction away from an electrode body of the second capacitor electrode; and An orthographic projection of the extending portion on the base substrate at least partially overlaps with an orthographic projection of an active layer of the third transistor of the corresponding pixel driving circuit on the base substrate; Furthermore, an orthographic projection of the extension portion on the base substrate at least partially overlaps with an orthographic projection of the portion connecting the first channel portion and the second channel portion on the base substrate.

2. The display panel according to claim 1, wherein Also comprising a first signal line layer located on a side of the storage capacitor away from the base substrate; A plurality of second capacitor electrodes respectively from a plurality of pixel driving circuits are sequentially connected to each other along a first direction; The first signal line layer includes a plurality of first high voltage signal lines respectively extending along a first direction; and A corresponding one of the plurality of first high voltage signal lines is connected to the second capacitor electrode.

3. The display panel according to claim 1, wherein: The extending portion includes a first extending portion along the second direction and a second extending portion along the first direction; The first extension portion connects the second extension portion and the electrode body of the second capacitor electrode; as well as, An orthographic projection of the second extension portion on the base substrate at least partially overlaps with an orthographic projection of the active layer of the third transistor of the corresponding pixel driving circuit on the base substrate.

4. The display panel according to claim 3, wherein: The second extension portion includes a shielding portion and a non-shielding portion; An orthographic projection of the shielding portion on the base substrate at least partially overlaps with an orthographic projection of the active layer of the third transistor of the corresponding pixel driving circuit on the base substrate; An orthographic projection of the non-shielding portion on the base substrate does not overlap with an orthographic projection of the active layer of the third transistor of the corresponding pixel driving circuit on the base substrate; as well as, The line width of the shielding portion is greater than the line width of the non-shielding portion.

5. The display panel according to claim 3, wherein: The corresponding pixel driving circuit further includes a driving transistor, and a node connection line connecting the drain of the third transistor and the gate of the driving transistor; Wherein, the drain of the third transistor is connected to the gate of the driving transistor; The source of the third transistor is connected to the drain of the driving transistor; and An orthographic projection of the first extending portion on a straight line extending along the second direction at least partially overlaps with an orthographic projection of the node connection line on the straight line. The display panel according to claim 5 , wherein: Also includes multiple data lines; The first extension portion is located between the node connection line and a corresponding data line among the plurality of data lines.

7. The display panel according to claim 1, wherein: Also included are a plurality of grid lines; Corresponding gate lines among the plurality of gate lines include a plurality of metal blocks spaced apart from each other and located in a first conductive layer, and metal lines along a first direction and located in a first signal line layer, wherein the metal lines along the first direction are respectively connected to the plurality of metal blocks through through holes.

8. The display panel according to claim 7, wherein: A corresponding metal block among the plurality of metal blocks has an L shape; An orthographic projection of a first channel portion of the active layer of the third transistor on the base substrate overlaps with an orthographic projection of a first metal portion of a corresponding metal block among the plurality of metal blocks on the base substrate; An orthographic projection of a second channel portion of the active layer of the third transistor on the base substrate overlaps with an orthographic projection of a second metal portion of a corresponding metal block among the plurality of metal blocks on the base substrate; as well as, The first metal portion and the second metal portion are a first gate and a second gate of the third transistor.

9. The display panel according to claim 1, wherein: Also includes: a plurality of first reset signal lines, each of which is along a first direction and located in the semiconductor material layer; as well as, a plurality of second reset signal lines, each of which is along a second direction and located in the second signal line layer; The plurality of first reset signal lines respectively cross the plurality of second reset signal lines; A corresponding one of the plurality of first reset signal lines is connected to at least a plurality of second reset signal lines of the plurality of second reset signal lines through a through-hole; and A corresponding one of the plurality of second reset signal lines is connected to at least a plurality of first reset signal lines of the plurality of first reset signal lines through a via.

10. The display panel according to claim 1, wherein Also included are a plurality of second low voltage signal lines located in the second signal line layer and respectively along the second direction; The plurality of second low voltage signal lines are electrically connected to cathodes of the light emitting elements.

11. The display panel according to claim 1, wherein: Also includes: a plurality of first high-voltage signal lines, each extending along a first direction and located in the first signal line layer; as well as, a plurality of second high-voltage signal lines, each extending along a second direction and located in the second signal line layer; The plurality of first high voltage signal lines respectively cross the plurality of second high voltage signal lines; A corresponding one of the plurality of first high voltage signal lines is connected to at least a plurality of second high voltage signal lines of the plurality of second high voltage signal lines through a via; and A corresponding one of the plurality of second high voltage signal lines is connected to at least a plurality of first high voltage signal lines of the plurality of first high voltage signal lines through a via.

12. The display panel according to claim 11, wherein: A corresponding one of the plurality of first high voltage signal lines comprises: a main body extending along a first direction; a protrusion protruding away from the main body in a second direction, and The protrusion is a portion where the corresponding one of the plurality of second high voltage signal lines is connected to the corresponding one of the plurality of first high voltage signal lines through one or more through holes.

13. The display panel according to claim 11, wherein: The corresponding pixel driving circuit further includes a driving transistor, and a node connection line connecting the drain of the third transistor and the gate of the driving transistor; The drain of the third transistor is connected to the gate of the driving transistor; The source of the third transistor is connected to the drain of the driving transistor; as well as, An orthographic projection of the corresponding one of the plurality of second high voltage signal lines on the base substrate covers an orthographic projection of the node connection line on the base substrate.

14. The display panel according to claim 11, wherein: An orthographic projection of the corresponding one of the plurality of second high voltage signal lines on the base substrate at least partially overlaps with an orthographic projection of at least one gate of the third transistor on the base substrate.

15. The display panel according to claim 1, wherein The display panel includes: a plurality of light emitting elements; and an interconnected first voltage supply network configured to provide a first voltage signal to cathodes of the plurality of light emitting elements; The interconnected first voltage supply network includes signal lines located in a display area of ​​the display panel, the display area being at least partially surrounded by a peripheral area; The signal lines include a plurality of first signal lines located in a first signal line layer and a plurality of second signal lines located in a second signal line layer; The display panel further includes a planarization layer located between the first signal line layer and the second signal line layer; and The plurality of first signal lines are electrically connected to the plurality of second signal lines.

16. The display panel according to claim 15, wherein: The interconnected first voltage supply network comprises: a plurality of first-first voltage signal lines respectively along a first direction; and a plurality of second-first voltage signal lines respectively along the second direction; The plurality of first-first voltage signal lines respectively cross the plurality of second-first voltage signal lines.

17. The display panel according to claim 16, wherein: The interconnected first voltage supply network includes a first sub-network formed by the plurality of first-first voltage signal lines and a second sub-network formed by the plurality of second-first voltage signal lines.

18. The display panel according to claim 16, wherein: A corresponding one of the plurality of first-first voltage signal lines is connected to at least a plurality of second-first voltage signal lines of the plurality of second-first voltage signal lines; and, A corresponding one of the plurality of second-first voltage signal lines is connected to at least a plurality of first-first voltage signal lines of the plurality of first-first voltage signal lines.

19. The display panel according to claim 16, wherein: The plurality of first-first voltage signal lines and the plurality of second-first voltage signal lines are interconnected by first through holes respectively extending through the planarization layer, at least some of the first through holes being located in the display area; A corresponding one of the plurality of first-first voltage signal lines is connected to at least a plurality of second-first voltage signal lines of the plurality of second-first voltage signal lines through a plurality of first through holes extending through the planarization layer; and A corresponding one of the plurality of second-first voltage signal lines is connected to at least a plurality of first-first voltage signal lines of the plurality of first-first voltage signal lines through a plurality of first through holes extending through the planarization layer.

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