Display panel and method of manufacturing the same

Abstract

The application discloses a display panel and a manufacturing method thereof, and belongs to the field of display panels. The display panel has a non-display area, the non-display area comprises a first area, a second area and a third area connected in sequence, a first conductive layer comprises a first conductive part and a second conductive part arranged in the first area and the third area, a second conductive layer comprises a third conductive part and a fourth conductive part arranged in the first area and the third area, the fourth conductive part is isolated from the second conductive part by a first planarization layer, the third conductive part is arranged on the first conductive part in a laminated mode, and a side surface of the first conductive part facing the second conductive part is in contact with the third conductive part and / or a second planarization layer; the second area is provided with a groove; and in the second area, at least part of the third conductive layer is in contact with a substrate. In the application, the second conductive layer is prevented from being warped upward during film formation, the distance between the second conductive layer and the third conductive layer is increased, and short circuit is less likely to occur.

Description

Technical Field

[0001] This invention relates to the field of display panels, and in particular to a display panel and a method for manufacturing the same. Background Technology

[0002] Currently, ultra-narrow bezels are a major trend in mobile phone product design. As bezels shrink, the space for wiring within the phone's bezel becomes increasingly limited. This reduced space leads to a continuous decrease in the width and spacing of metal lines, a reduction in the distance between adjacent slots, and a closer proximity between the metal traces and the conductive layer on the surface. Furthermore, residual material remains between the two slots in the planarization layer. Therefore, during the metal trace film formation process, the metal trace layer may lift up when it encounters this residual material. Consequently, during the aging process of the display panel, two metal lines carrying different signals (such as the anode and the metal trace) are prone to short-circuiting, causing damage and resulting in display abnormalities. Summary of the Invention

[0003] This application provides a display panel to reduce the probability of short circuits between two conductive layers, which could cause damage from explosions. The display panel includes a substrate, a first conductive layer, a first planarization layer, a second conductive layer, a second planarization layer, and a third conductive layer sequentially disposed on the substrate. The display panel has a display area and a non-display area. The non-display area includes a first region, a second region, and a third region connected sequentially. The first conductive layer includes a first conductive portion and a second conductive portion disposed in the first region and the third region, respectively. The second conductive layer includes a third conductive portion and a fourth conductive portion disposed in the first region and the third region, respectively. The fourth conductive portion is isolated from the second conductive portion by the first planarization layer. The third conductive portion is stacked on top of the first conductive portion. The surface of the first conductive portion facing the second conductive portion is in contact with the third conductive portion and / or the second planarization layer. The second region has a groove. In the second region, at least a portion of the third conductive layer is in contact with the substrate.

[0004] In some embodiments, a first through groove is formed on the first conductive layer, the first through groove being partially located in the second region and partially extending into the first region and the third region; and / or the side surface of the second conductive portion facing the first conductive portion is in contact with the first planarization layer; and / or in the third region, at least a portion of the structure of the second planarization layer covers the first planarization layer.

[0005] In some embodiments, the first planarization layer has a second through slot located in the first region and the second region; and / or the second planarization layer has a third through slot located in the second region.

[0006] In some embodiments, within the first region, the side surface of the first conductive portion facing the second conductive portion is in contact with the third conductive portion, and the side surface of the third conductive portion facing the second conductive portion is in contact with the second planarization layer.

[0007] In some embodiments, within the first region, the second planarization layer is located above the third conductive portion, and a portion of the second planarization layer is in contact with the substrate.

[0008] In some embodiments, the width of the second region in the direction from the first region to the third region is 5-7 μm; and / or the width of the first conductive layer located in the first region in the direction from the first region to the third region is 5-7 μm; and / or the maximum distance between the second conductive layer and the substrate in the first region is 2-4 μm.

[0009] In some embodiments, the third conductive layer is a continuous layer in the first region, the second region, and the third region; in the first region and the third region, the third conductive layer covers the second planarization layer.

[0010] Another aspect of this application provides a method for manufacturing a display panel. In the non-display area, the method includes: providing a substrate and forming a first conductive film layer on the substrate; patterning the first conductive film layer to form a first conductive portion and a second conductive portion separated by a first through-groove; forming a first planarization film layer on the substrate and the first and second conductive portions; patterning the first planarization film layer to remove at least a first portion of the first planarization film layer located within the first through-groove and at least a second portion of the first planarization film layer connected to the first portion and located on the first conductive portion, thereby forming a first planarization layer at least partially located on the second conductive portion; and forming a second conductive film layer on the substrate, the first planarization layer, and the first conductive portion.

[0011] In some embodiments, the method further includes: patterning the second conductive film layer to form a third conductive portion on the first conductive portion and a fourth conductive portion on the first planarization layer, wherein the fourth conductive portion is isolated from the second conductive portion through the first planarization layer; forming a second planarization film layer on the substrate, the first planarization layer, the third conductive portion, and the fourth conductive portion; patterning the second planarization film layer to expose a portion of the substrate corresponding to the first through-slot, thereby forming a second planarization layer; a first portion of the second planarization layer is located on the third conductive portion, and a second portion of the second planarization layer is located on the fourth conductive portion; wherein the side surface of the first conductive portion facing the second conductive portion is in contact with the third conductive portion and / or the second planarization layer; and forming a third conductive layer on the substrate and the second planarization layer, wherein at least a portion of the third conductive layer is in contact with a portion of the substrate corresponding to the first through-slot.

[0012] In some embodiments, during the step of patterning the first planarization film layer, the side surface of the second conductive portion facing the first conductive portion is brought into contact with the first planarization layer.

[0013] In some embodiments, during the step of patterning the second planarization film layer, at least a portion of the structure of the second planarization layer covers the first planarization layer; and / or during the step of patterning the second planarization film layer, the side surface of the first conductive portion facing the second conductive portion contacts the third conductive portion, and the side surface of the third conductive portion facing the second conductive portion contacts the second planarization layer; and / or during the step of patterning the second planarization film layer, a first portion of the second planarization layer is positioned above the third conductive portion, and the first portion of the second planarization layer also contacts the substrate.

[0014] This application provides a display panel and its manufacturing method. Because the display panel has a groove in the second region, the third conductive layer covering the groove surface is too close to the third conductive portion, making it prone to short circuits and potential damage. Unlike existing technologies, this application directly contacts the third conductive portion or the second planarization layer with the side of the first conductive portion in the first region closest to the third region. Since the third conductive portion is formed on the first conductive portion during fabrication, it is less prone to warping upwards, thus avoiding excessive proximity between the third conductive portion and the third conductive layer, reducing the probability of short circuits and potential damage. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0016] Figure 1 This is a schematic diagram of the structure of a display device in one embodiment of this application;

[0017] Figure 2 This is a cross-sectional view of the display panel bezel position in one embodiment of this application;

[0018] Figure 3 This is a cross-sectional view of the display panel bezel position in the comparative embodiment of this application;

[0019] Figure 4 This is a flowchart illustrating a method for manufacturing a display panel according to one embodiment of this application;

[0020] Figures 5a-5e This is a schematic diagram of the structure of each step in the manufacturing method of the display panel in one embodiment of this application;

[0021] Figure 6 This is a flowchart illustrating a method for manufacturing a display panel according to another embodiment of this application;

[0022] Figures 7a-7d This is a structural schematic diagram of the steps in the manufacturing method of the display panel in another embodiment of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0024] Currently, in the process of increasing the screen ratio of display panels such as OLED (Organic Light-Emitting Diode), the bezel area of ​​the display panel is getting smaller and smaller, which makes the spacing between metal traces smaller and smaller. Therefore, short circuits are more likely to occur between closely spaced metal traces, resulting in damage.

[0025] Please see Figure 1 , Figure 1This is a schematic diagram of the structure of a display device according to an embodiment of this application. The display device 10 provided in this embodiment includes a display panel 100. The display device 10 provided in this embodiment can be a mobile phone, tablet computer, laptop computer, television, digital camera, smartwatch, navigator, or other product or component with display function.

[0026] Please see Figure 2 , Figure 2 This is a cross-sectional view of the display panel bezel position in one embodiment of this application. The present invention provides a display panel 100, which includes a substrate 101 and a first conductive layer 102, a first planarization layer 103, a second conductive layer 104, a second planarization layer 105, and a third conductive layer 106 sequentially disposed on the substrate 101. The display panel 100 has a display area (not shown) and a non-display area. The non-display area includes a first region A, a second region B, and a third region C sequentially connected. The first conductive layer 102 includes a first conductive portion 1021 and a second conductive portion 1022 respectively disposed in the first region A and the third region C. The second conductive layer 104 includes a third conductive portion 1041 and a fourth conductive portion 1042 respectively disposed in the first region A and the third region C. The fourth conductive portion 1042 is isolated from the second conductive portion 1022 by a first planarization layer 103. The third conductive portion 1041 is stacked on the first conductive portion 1021, and the side surface of the first conductive portion 1021 facing the second conductive portion 1022 is in contact with the third conductive portion 1041. A groove is provided in the second region B. In the second region B, at least a portion of the third conductive layer 106 is in contact with the substrate 101. In other embodiments, the side surface of the first conductive portion 1021 facing the second conductive portion 1022 may also be in contact with the second planarization layer 105, or simultaneously in contact with the third conductive portion 1041 and the second planarization layer 105.

[0027] Specifically, the display panel 100 has a third conductive layer 106 on the surface away from the substrate 101. This third conductive layer 106 is used for grounding and can be connected to other structures to connect to the ground terminal. Because the display panel 100 has a groove 107 in the second region B, the third conductive layer 106 covering the surface of the groove 107 is close to the third conductive portion 1041, making it prone to short circuits and potential damage. This application addresses this by placing the first conductive portion 1021 in the first region A closer to the third region C. Figure 2 The left side of the third conductive part 1041 (or the second planarization layer 105) is in direct contact with the third conductive part 1041 (or the second planarization layer 105). Since the left side of the third conductive part 1041 is formed on the first conductive part 1021 during the preparation of the third conductive part 1041, it is not easy to be warped upwards. This avoids the distance between the third conductive part 1041 and the third conductive layer 106 being too close, and reduces the probability of short circuit and explosion between the two.

[0028] Specifically, the first conductive layer 102 and the second conductive layer 104 are metal traces. The first conductive layer 102 and the second conductive layer 104 can be made of aluminum wire, or copper wire, silver wire, gold-plated wire or other suitable materials, without specific limitations here.

[0029] Specifically, the substrate 101 can be formed of any insulating material. For example, the substrate 101 can be formed of polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyaryl compounds (PAR), glass fiber reinforced plastic (FRP), or combinations of these polymer materials. In addition, the substrate 101 can be transparent, translucent, or opaque, without specific limitations. It is understood that, considering the general structure of the substrate 101 in an OLED-type display panel, in an optional embodiment, the substrate 101 may include a substrate, a buffer layer, an active layer, a gate insulating layer, a gate, and an insulating layer stacked sequentially; a first conductive layer 102 is formed on the surface of the insulating layer facing away from the gate. In this embodiment, substrate 101 includes a substrate and a thin-film transistor driving the OLED. The thin-film transistor includes various functional film layers, such as an active layer, a gate insulating layer, a gate electrode, and an insulating layer. The first conductive layer 102 in the above embodiment is the source or drain of the thin-film transistor, and the source and drain are formed on the interlayer insulating layer. It should be noted that this application does not limit the film layer structure of substrate 101. Those skilled in the art should select an appropriate film layer structure according to actual application requirements, which will not be elaborated here.

[0030] Specifically, both the first planarization layer 103 and the second planarization layer 105 can be made of polyimide. The function of the first planarization layer 103 and the second planarization layer 105 is to align the thicknesses of the first conductive layer 102 and the second conductive layer 104 using the difference in their thicknesses, thereby ensuring the flatness of the third conductive layer 106 formed on the second planarization layer 105. That is, the third conductive layer 106 will not have unevenness due to the presence of the first conductive layer 102 and the second conductive layer 104 at its bottom. Therefore, the pixels of the substrate 101 will not experience uneven brightness due to the unevenness of the third conductive layer 106 at its bottom, thus avoiding the color shift problem present in existing display devices and improving the display effect of the display device.

[0031] Optionally, in this embodiment, a first through-groove 102a is formed on the first conductive layer 102. The first through-groove 102a is partially located in the second region B and partially extends into the first region A and the third region C. That is, the range of the first through-groove 102a is larger than the range of the second region B. By forming the first through-groove 102a on the first conductive layer 102, the first conductive layer 102 can be divided into a first conductive portion 1021 and a second conductive portion 1022 located in the first region A and the third region C, respectively. Specifically, the first conductive layer 102 can be formed by film deposition on the substrate 101, and the first through-groove 102a can be formed by etching on the first conductive layer 102.

[0032] Optionally, in this embodiment, the surface of the second conductive portion 1022 facing the first conductive portion 1021 is in contact with the first planarization layer 103. Since the display panel 100 has a groove 107 in the second region B, the third conductive layer 106 covering the surface of the groove 107 is too close to the side of the second conductive portion 1022 facing the first conductive portion 1021, which can easily cause a short circuit and lead to damage. By making the first planarization layer 103 contact the side of the second conductive portion 1022 facing the first conductive portion 1021, the distance between the second conductive portion 1022 and the third conductive layer 106 is avoided, reducing the probability of a short circuit and damage. Specifically, the first planarization layer 103 fills the first through-groove 102a within the third region C.

[0033] Optionally, within the third region C, at least a portion of the structure of the second planarization layer 105 covers the first planarization layer 103. This ensures that the second conductive portion 1022 and the third conductive layer 106 are simultaneously connected by the first planarization layer 103 and the second planarization layer 105, preventing short circuits.

[0034] Optionally, in this embodiment, the first planarization layer 103 has a second through-slot 103a, which is located within the first region A and the second region B. Specifically, the first planarization layer 103 can be formed on the first conductive layer 102, and then patterned by etching. In this embodiment, by removing the first planarization layer 103 on the side of the second region B and the first region A closer to the second region B, the left side of the first conductive part 1021 does not have the first planarization layer 103. This allows the left side of the first conductive part 1021 to directly contact the third conductive part 1041 or the second planarization layer 105, avoiding upward warping on the left side of the third conductive part 1041, thereby reducing the probability of short circuit with the third conductive layer 106.

[0035] Optionally, the second planarization layer 105 has a third through groove 105a located within the second region B. Further, within the first region A, the surface of the first conductive portion 1021 facing the second conductive portion 1022 contacts the third conductive portion 1041, and the surface of the third conductive portion 1041 facing the second conductive portion 1022 contacts the second planarization layer 105. The third through groove 105a is used to form a recess 107. Specifically, during the process of forming the second planarization layer 105 on the surface of the second conductive layer 104, the second planarization layer 105 can be patterned by etching to remove it within the second region B.

[0036] Optionally, within the first region A, the second planarization layer 105 is located above the third conductive portion 1041, and a portion of the second planarization layer 105 is in contact with the substrate 101. This ensures that an insulating second planarization layer 105 exists between the left side of the third conductive portion 1041 and the third conductive layer 106, preventing a short circuit between them.

[0037] Specifically, the width of the second region B along the direction from the first region A to the third region C is 5-7 μm; the width of the first conductive layer 102 located in the first region A along the direction from the first region A to the third region C is 5-7 μm; and the maximum distance between the second conductive layer 104 and the substrate 101 in the first region A is 2-4 μm.

[0038] Optionally, the third conductive layer 106 is a continuous layer within the first region A, the second region B, and the third region C; within the first region A and the third region C, the third conductive layer 106 covers the second planarization layer 105. The continuous third conductive layer 106 can be formed by forming a film on the second planarization layer 105 and the surface of the groove 107.

[0039] See Figure 3 , Figure 3 This is a cross-sectional view of the bezel of the display panel 200 in the comparative embodiment of this application. In this comparative embodiment, the display panel 200 has a first conductive layer 202 and a first planarization layer 203 disposed side by side on the substrate 201 in the first region A. A second conductive layer 204 is stacked on the first conductive layer 202 and the first planarization layer 203. A second planarization layer 205 is disposed on the second conductive layer 204 and the first planarization layer 203. A third conductive layer 206 is disposed on the second planarization layer 205. In the second region B and the third region C, the other structures of the display panel 200 of this comparative embodiment are the same as those of the display panel 100 of the embodiment of this application, and will not be described again here.

[0040] It is understandable that the first planarization layer 203 has residue on the side of the first region A near the second region B. This residue is located within the first through-groove of the first conductive layer 202 and is connected to the substrate 201. During the film formation of the first planarization layer 203, it can be patterned by etching to create two trenches on the first planarization layer 203, one trench located in the second region B and the other trench located in the first region A. Subsequently, during the film formation of the second conductive layer 204, because the first planarization layer 203 has residue in the first region A, and the height of this residue is higher than the height of the first conductive layer 202, the side of the second conductive layer 204 near the first planarization layer 203 will warp upwards during film formation. This results in a relatively close distance between the second conductive layer 204 and the third conductive layer 206. After prolonged use, damage may occur between the second conductive layer 204 and the third conductive layer 206, causing the two signals to short-circuit and display anomalies.

[0041] See Figure 4 , Figure 4 This is a schematic flowchart illustrating a method for manufacturing a display panel according to one embodiment of this application. (See attached diagram.) Figures 5a-5e , Figures 5a-5e This is a schematic diagram illustrating the structural steps of a display panel manufacturing method according to an embodiment of this application. This application provides a method for manufacturing a display panel, including:

[0042] Step S101: Provide a substrate 301 and form a first conductive film layer 302 on the substrate 301, such as... Figure 5a As shown.

[0043] Step S102: Pattern the first conductive film layer 302 to form a first conductive portion 3021 and a second conductive portion 3022 separated by the first through groove 302a, such as... Figure 5b As shown, two separate conductive portions can be formed by etching a first through groove 302a on the first conductive film layer 302.

[0044] Step S103: A first planarization film layer 303a is formed on the substrate 301 and the first conductive portion 3021 and the second conductive portion 3022, such as... Figure 5c As shown.

[0045] Step S104: Pattern the first planarization film layer 303a to remove at least a first portion of the first planarization film layer 303a located within the first through groove 302a and at least a second portion connected to the first portion and located on the first conductive portion 3021, thereby forming a first planarization layer 303 at least partially located on the second conductive portion 3022, as shown. Figure 5dAs shown, a portion of the first planarization film layer 303a can be removed by etching, and the first planarization film layer on the side of the first conductive portion 3021 near the second conductive portion 3022 can be removed in this step.

[0046] Step S105: A second conductive film layer 304 is formed on the substrate 301, the first planarization layer 303, and the first conductive portion 3021, such as... Figure 5e As shown, by removing the first planarization film layer on the side of the first conductive portion 3021 near the second conductive portion 3022 in the previous step, the second conductive film layer 304 is prevented from warping upward on the side near the second conductive portion 3022 when the second conductive film layer 304 is formed on the first conductive portion 3021.

[0047] Therefore, the display panel manufacturing method described in the above embodiment provides favorable conditions for preventing the distance between the further conductive layer and the second conductive film layer 304 from becoming too close during subsequent display panel manufacturing. This reduces the probability of short circuits or damage to the two conductive layers in the final manufactured display panel.

[0048] Further, see Figure 6 , Figure 6 This is a schematic flowchart illustrating a method for manufacturing a display panel according to another embodiment of this application. (See attached diagram.) Figures 7a-7d , Figures 7a-7d This is a schematic diagram illustrating the structural steps of a method for manufacturing a display panel according to another embodiment of this application. In this embodiment, steps S201 to S205 are the same as steps S101 to S105 in the previous embodiment, and the method further includes the following step after S205:

[0049] Step S206: In Figure 5e Based on this, the second conductive film layer 304 is patterned to form a third conductive portion 3041 located on the first conductive portion 3021 and a fourth conductive portion 3042 located on the first planarization layer 303, wherein the fourth conductive portion 3042 is isolated from the second conductive portion 3022 by the first planarization layer 303, as shown below. Figure 7a As shown, the second conductive film layer can be etched to divide it into two conductive parts.

[0050] Step S207: A second planarization film layer 305a is formed on the substrate 301, the first planarization layer 303, the third conductive portion 3041, and the fourth conductive portion 3042, as shown below. Figure 7b As shown.

[0051] Step S208: Pattern the second planarization film layer 305a to expose a portion of the substrate 301 corresponding to the first through-groove 302a, thereby forming the second planarization layer 305; the first portion of the second planarization layer 305 is located on the third conductive portion 3041, and the second portion of the second planarization layer 305 is located on the fourth conductive portion 3042; wherein the surface of the first conductive portion 3021 facing the second conductive portion 3022 and the third conductive portion 3041, as shown... Figure 7c As shown, the second planarization layer 305a can be etched to divide it into two parts, respectively covering the third conductive portion 3041 and the fourth conductive portion 3042. In other embodiments, the surface of the first conductive portion 3021 facing the second conductive portion 3022 may be in contact with the second planarization layer 305.

[0052] Step S209: A third conductive layer 306 is formed on the substrate 301 and the second planarization layer 305, wherein at least a portion of the third conductive layer 306 is in contact with a portion of the substrate 301 corresponding to the first through-groove 302a, such as... Figure 7d As shown, this avoids the third conductive layer 306 being too close to the third conductive part 3041 and the fourth conductive part 3042, thereby preventing damage to the display panel caused by short circuit.

[0053] Optionally, in step S104, the side surface of the second conductive part 3022 facing the first conductive part 3021 is brought into contact with the first planarization layer 303 to avoid the second conductive part 3022 and the third conductive layer 306 being too close to each other, which could lead to a short circuit.

[0054] Optionally, in step S208, at least a portion of the structure of the second planarization layer 305 is made to cover the first planarization layer 303 to prevent the second conductive portion 3022 from being too close to the third conductive layer 306, which could lead to a short circuit.

[0055] Optionally, in step S208, the surface of the first conductive part 3021 facing the second conductive part 3022 is brought into contact with the third conductive part 3041, and the surface of the third conductive part 3041 facing the second conductive part 3022 is brought into contact with the second planarization layer 305. That is, the first conductive part 3021, the third conductive part 3041 and the second planarization layer 305 are formed in sequence on the side facing the second conductive part 3022. On the one hand, this prevents the third conductive part 3041 from warping upwards on the side facing the second conductive part 3022. On the other hand, the third conductive part 3041 and the third conductive layer 306 are separated by the second planarization layer 305, so that the third conductive part 3041 is not easily short-circuited with the third conductive layer 306.

[0056] Optionally, in step S208, the first portion of the second planarization layer 305 is positioned above the third conductive portion 3041, and the first portion of the second planarization layer 305 is also in contact with the substrate 301, so as to ensure that the second planarization layer 305 covers the third conductive portion 3041 and the first conductive portion 3021, and that the third conductive portion 3041 and the third conductive layer 306 have a sufficient distance.

[0057] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.

Claims

1. A display panel, the display panel comprising a substrate, a first conductive layer, a first planarization layer, a second conductive layer, a second planarization layer, and a third conductive layer sequentially disposed on the substrate, the display panel having a display area and a non-display area, characterized in that, The non-display area includes a first area, a second area, and a third area connected in sequence. The first conductive layer includes a first conductive portion and a second conductive portion disposed in the first area and the third area, respectively. The second conductive layer includes a third conductive portion and a fourth conductive portion disposed in the first area and the third area, respectively. The fourth conductive portion and the second conductive portion are isolated by the first planarization layer. The third conductive portion is stacked on the first conductive portion. In the first area, the side surface of the first conductive portion facing the second conductive portion is in contact with the third conductive portion, and the side surface of the third conductive portion facing the second conductive portion is in contact with the second planarization layer. The second area is provided with a groove; In the second region, at least a portion of the third conductive layer is in contact with the substrate.

2. The display panel according to claim 1, characterized in that, A first through groove is formed on the first conductive layer, and the first through groove is partially located in the second region and partially extends into the first region and the third region; And / or the side surface of the second conductive portion facing the first conductive portion is in contact with the first planarization layer; And / or in the third region, at least a portion of the structure of the second planarization layer covers the first planarization layer.

3. The display panel according to claim 1, characterized in that, The first planarization layer has a second through slot, which is located in the first region and the second region. And / or the second planarization layer has a third through slot, which is located in the second region.

4. The display panel according to claim 1, characterized in that, Within the first region, the second planarization layer is located above the third conductive portion, and a portion of the second planarization layer is in contact with the substrate.

5. The display panel according to claim 1, characterized in that, The width of the second region along the direction from the first region to the third region is 5-7 μm; And / or the width of the first conductive layer located in the first region along the direction from the first region to the third region is 5-7 μm; And / or the maximum distance between the second conductive layer and the substrate in the first region is 2-4 μm.

6. The display panel according to any one of claims 1-5, characterized in that, The third conductive layer is a continuous layer within the first region, the second region, and the third region; In the first region and the third region, the third conductive layer covers the second planarization layer.

7. A method for manufacturing a display panel, the display panel having a display area and a non-display area, characterized in that, In the non-display area, the method of manufacturing the display panel includes: providing a substrate and forming a first conductive film layer on the substrate; The first conductive film layer is patterned to form a first conductive portion and a second conductive portion separated by a first through groove; A first planarization film layer is formed on the substrate and the first conductive portion and the second conductive portion; The first planarization film layer is patterned to remove at least a first portion of the first planarization film layer located in the first through groove and at least a second portion connected to the first portion and located on the first conductive portion, thereby forming a first planarization layer at least partially located on the second conductive portion; A second conductive film layer is formed on the substrate, the first planarization layer, and the first conductive portion; The second conductive film layer is patterned to form a third conductive portion on the first conductive portion and a fourth conductive portion on the first planarization layer, wherein the fourth conductive portion is isolated from the second conductive portion through the first planarization layer; A second planarization film layer is formed on the substrate, the first planarization layer, the third conductive portion, and the fourth conductive portion; The second planarization film layer is patterned to expose a portion of the substrate corresponding to the first through-slot, thereby forming the second planarization layer; The first portion of the second planarization layer is located on the third conductive portion, and the second portion of the second planarization layer is located on the fourth conductive portion; The first conductive portion has its side surface facing the second conductive portion in contact with the third conductive portion, and the third conductive portion has its side surface facing the second conductive portion in contact with the second planarization layer. A third conductive layer is formed on the substrate and the second planarization layer, wherein at least a portion of the third conductive layer is in contact with a portion of the substrate corresponding to the first through-slot.

8. The method for manufacturing a display panel according to claim 7, characterized in that, In the step of patterning the first planarization film layer, the side surface of the second conductive portion facing the first conductive portion is brought into contact with the first planarization layer.

9. The method for manufacturing a display panel according to claim 7, characterized in that, In the step of patterning the second planarization film layer, at least a portion of the structure of the second planarization layer covers the first planarization layer. And / or in the step of patterning the second planarization film layer, the side surface of the first conductive portion facing the second conductive portion is brought into contact with the third conductive portion, and the side surface of the third conductive portion facing the second conductive portion is brought into contact with the second planarization layer; And / or in the step of patterning the second planarization film layer, a first portion of the second planarization layer is positioned above the third conductive portion, and the first portion of the second planarization layer is also in contact with the substrate.

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