Method for manufacturing optoelectronic hybrid packaging structure and protective structural member

Abstract

The application discloses a kind of photoelectric hybrid packaging structure manufacturing method and protective structural member, comprising the following steps: providing a carrier plate and optical chip, optical chip side is provided with at least one optical interface;At least one electric chip is provided, and is arranged on the upper surface of optical chip;At least one protective structural member is provided, and the protective structural member is cover-like structure, and a cavity is formed in the inside, and the surface of protective structural member is also formed with at least one through hole, the protective structural member is attached to the upper surface of optical chip corresponding to optical interface, so that optical interface is completely located in cavity;The environment in cavity is decompressed, and the film layer is overlaid on the outer surface of protective structural member partial area, so that cavity is low-pressure sealed cavity;Form plastic package body.The cavity forms a closed low-pressure space, prevents the problem that high pressure in cavity leads to crack failure in injection molding and subsequent high-temperature process, to meet the reliability requirements in injection molding process and subsequent process operation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, and in particular to a manufacturing method of an optoelectronic hybrid packaging structure and a protection structure. BACKGROUND

[0002] Hybrid packaging of optoelectronic chips has gradually become the mainstream of future development. The main role of optoelectronic packaging is to convert optical signals and electrical signals, or to use optical chips for operation. The biggest difference compared with traditional electrical chip packaging is that the optical chip has an optical port for light import. The quality of the optical port directly affects the quality of optical coupling, and plays an important role in the efficiency of optical-electrical conversion, and the speed and accuracy of optical operation. However, because of the existence of the optical port in the optical chip, the SIP packaging (System In Package) form commonly used in traditional packaging is difficult to implement. Because the injection molding process used in SIP packaging will directly cover the optical port together with the optical chip, effective optical coupling / optical transmission cannot be achieved. Once the optoelectronic packaging cannot use SIP packaging, it will be at a disadvantage in terms of packaging product reliability, versatility and iterativeness, affecting the development of optoelectronic packaging in the future.

[0003] In the commonly used technology, an optical port protection structure is usually provided before injection molding, which is attached to the upper surface of the optical chip and forms a closed cavity with the upper surface of the optical chip, that is, the optical port is protected in the closed cavity, and then the injection molding process is performed. However, in wafer-level injection molding process, the environmental pressure needs to be reduced to the minimum value (hundred pascal order), if the pressure in the optical port protection structure (i.e. the closed cavity) is normal pressure (ten thousand pascal order), the large pressure difference is easy to cause cracking failure and other problems in injection molding and subsequent high-temperature process. SUMMARY

[0004] The purpose of the present application is to provide a manufacturing method of an optoelectronic hybrid packaging structure and a protection structure to meet the requirements of injection molding process and subsequent process workability and reliability.

[0005] To achieve the above-mentioned purpose of the application, the present application provides a manufacturing method of an optoelectronic hybrid packaging structure, comprising the steps of:

[0006] providing a carrier plate and an optical chip, the optical chip being provided with at least one optical interface on one side, and the side of the optical chip with the optical interface being arranged on the upper surface of the carrier plate away from the carrier plate;

[0007] providing at least one electrical chip, and arranging the electrical chip on the upper surface of the optical chip and realizing electrical connection with the optical chip;

[0008] The application provides at least one protective structural member, which is a cover-shaped structure, and a cavity is formed in the cover-shaped structure. A through hole is formed on the surface of the protective structural member, and the through hole is connected with the inner and outer surfaces of the protective structural member. The protective structural member is attached to the upper surface of the optical chip corresponding to the optical interface, so that the optical interface is completely located in the cavity.

[0009] The environment in the cavity is depressurized, and a film layer is covered on at least part of the outer surface of the protective structural member, so that the cavity is a low-pressure sealed cavity.

[0010] Plastic sealing material is provided to cover the upper surface of the film layer, the upper surface and the side surface of the electric chip, the unshielded upper surface and the side surface of the protective structural member, and the unshielded upper surface of the optical chip, so as to form a plastic sealing body.

[0011] Further, the environment in the cavity is depressurized, and the specific process comprises:

[0012] A vacuum film pressing device is provided, which comprises a vacuum device and a film pressing device. The packaged carrier plate, optical chip, electric chip and protective structural member are placed in the vacuum film pressing device.

[0013] The vacuum device is started, the target vacuum degree is set, the environment outside the cavity is depressurized, and the air pressure in the cavity reaches the target vacuum degree.

[0014] Further, the film layer is covered on at least part of the outer surface of the protective structural member, so that the cavity is a low-pressure sealed cavity, and the specific process comprises:

[0015] The film pressing device is started, and a film layer is covered on the optical chip, and the film layer is tightly attached to the upper surface and the side surface of the protective structural member and the electric chip and the unshielded upper surface of the optical chip.

[0016] The upper surface of the optical chip, the inner side of the cavity of the protective structural member and the lower surface of the film layer form a low-pressure sealed cavity.

[0017] Further, the film layer is covered on the optical chip, and the specific process comprises:

[0018] A film layer with a thickness of 15-30 μm is covered on the optical chip, and the film layer is a special film for cavity devices.

[0019] Further, the plastic sealing body is formed, and the specific process comprises:

[0020] The plastic sealing material is covered on the upper surface of the film layer to form the plastic sealing body, so that the upper surface of the plastic sealing body is at the same height.

[0021] Further, the method further comprises the steps of:

[0022] The plurality of through silicon vias are formed in the optical chip, the functional surface of the electric chip is arranged towards the upper surface of the optical chip, and the electrical connection between the electric chip and the optical chip is realized through the through silicon vias.

[0023] Further, the method further comprises the steps of:

[0024] The optical chip is debonded from the carrier plate.

[0025] A redistribution layer is formed on the side of the optical chip where the electric chip is not attached, and the electrical connection between the optical chip and the redistribution layer is realized through the through silicon vias.

[0026] Further, the method further comprises the steps of:

[0027] The plastic package is thinned until the top wall of the protective structural member is exposed.

[0028] The top wall of the protective structural member is thinned until the optical interface is completely exposed.

[0029] The present application provides a protective structural member for use in the method for manufacturing the optoelectronic hybrid packaging structure according to any one of the preceding embodiments, wherein the protective structural member is a cover-shaped structure, a cavity is arranged inside the cover-shaped structure, at least one through hole is arranged on the surface of the protective structural member, the through hole communicates the inner and outer surfaces of the protective structural member, and when the protective structural member is attached to the upper surface of the optical chip corresponding to the optical interface, the optical interface is completely located in the cavity.

[0030] Further, the surface of the protective structural member is provided with a plurality of through holes, and the cross section of the through hole is circular.

[0031] The present application has the beneficial effect that by arranging a protective structural member at the optical interface and arranging a through hole on the protective structural member, it is convenient to reduce the air pressure in the cavity where the optical interface is located to a lower value, and then press a thin film layer above the optical interface, so that the cavity forms a sealed low-pressure space, preventing the air pressure in the cavity from being too high to cause problems such as cracking failure in injection molding and subsequent high-temperature processes, so as to meet the reliability requirements in the injection molding process and subsequent process operations. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 FIG. 1 is a flowchart of the method for manufacturing the optoelectronic hybrid packaging structure according to an embodiment of the present application.

[0033] Figures 2-8 Process flow chart for manufacturing the corresponding optoelectronic hybrid packaging structure in an embodiment of the present application.

[0034] Figure 9 Side view structural schematic diagram of the protection structure in an embodiment of the present application.

[0035] Figure 10 Top view structural schematic diagram of the protection structure in an embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to make the objectives, technical solutions, and advantages of the present application clearer, the technical solutions of the present application will be described below in conjunction with specific embodiments of the present application and corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort belong to the scope of protection of the present application.

[0037] The embodiments of the present application will be described in detail below, and examples of the embodiments are shown in the drawings, in which the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0038] For the convenience of description, the terms representing spatial relative positions are used in the description, such as “upper”, “lower”, “rear”, “front”, and the like, to describe the relationship of one unit or feature relative to another unit or feature shown in the drawings. The terms of spatial relative positions can include different positions of the device in use or work other than the positions shown in the drawings. For example, if the device in the drawings is turned over, the unit described as being “below” or “above” the other unit or feature will be “below” or “above” the other unit or feature. Therefore, the exemplary term “below” can include both the lower and upper spatial positions.

[0039] As shown in Figure 1 The present application provides a manufacturing method of an optoelectronic hybrid packaging structure, comprising the steps of:

[0040] S1: providing a carrier plate and an optical chip, the optical chip is provided with at least one optical interface on one side surface, and the side surface of the optical chip with the optical interface is arranged on the upper surface of the carrier plate away from the carrier plate.

[0041] S2: providing at least one electronic chip, and arranging the electronic chip on the upper surface of the optical chip and realizing electrical connection with the optical chip.

[0042] S3: providing at least one protective structural member, the protective structural member being a cover-like structure, the cover-like structure having a cavity formed therein, and the protective structural member having at least one through hole formed on a surface thereof, the through hole being in communication with the inner and outer surfaces of the protective structural member, the protective structural member being attached to the upper surface of the optical chip with the optical interface being located in the cavity.

[0043] S4: reducing the pressure in the cavity, and covering the outer surface of the protective structural member with a film layer, so that the cavity is a low-pressure sealed cavity.

[0044] S5: providing plastic sealing material, and covering the upper surface and the side surface of the film layer, the upper surface and the side surface of the electrical chip, the upper surface and the side surface of the protective structural member which are not covered by the film layer, and the upper surface of the optical chip which is not covered by the film layer, to form a plastic sealing body.

[0045] According to step S1, as shown in the figure, Figure 2 a carrier plate 1 and an optical chip 2 are provided. The carrier plate 1 can be a substrate, a glass plate, or other flat plates with certain supporting force and smooth surface. As an example, the optical chip 2 is provided with an optical interface 21 on one side for guiding light, and a plurality of through silicon vias 22 are formed in the optical chip 2, the through silicon vias 22 connecting the upper and lower surfaces of the optical chip 2, and the through silicon vias 22 being filled with conductive material.

[0046] Specifically, a layer of bonding glue can be first coated on the upper surface of the carrier plate 1, and then the optical chip 2 with the optical interface 21 is fixed on the upper surface of the carrier plate 1 with the side of the optical interface 21 facing away from the carrier plate 1. The selection of the bonding glue is not limited in the present application, and a temporary bonding glue can be selected for facilitating the subsequent debonding process.

[0047] In step S2, at least one electrical chip 3 is provided, and the electrical chip 3 is arranged on the upper surface of the optical chip 2 and electrically connected to the optical chip 2, which specifically includes:

[0048] As shown in the figure, Figure 3 as an example, an electrical chip 3 is provided, which includes a functional surface having an electrical pad and a non-functional surface opposite to the functional surface, the functional surface of the electrical chip 3 is arranged towards the upper surface of the optical chip 2, and specifically, the electrical pad on the functional surface of the electrical chip 3 is arranged opposite to the through silicon via 22, that is, the electrical connection between the electrical chip 3 and the optical chip 2 is realized through the through silicon via 22.

[0049] Of course, in other embodiments of the present application, two or more electrical chips 3 can be provided to meet different requirements of products, and the present application is not limited thereto, and the number of electrical chips 3 can be adjusted according to actual design requirements.

[0050] Further, before step S3, the manufacturing method in the present embodiment further includes the step of: attaching at least one passive element 4 to the upper surface of the optical chip 2.

[0051] See also Figure 3 For example, a passive component 4 is mounted on the upper surface of the optical chip 2. The passive component 4 can be a resistor, capacitor or inductor. The present invention does not limit the type and number of passive components mounted on the upper surface of the optical chip 2, and can be adjusted according to actual needs.

[0052] In step S3, at least one protective structural member 5 is provided. The protective structural member 5 is a cover-shaped structure, and a cavity 51 is formed inside the cover-shaped structure. At least one through hole 52 is also formed on the surface of the protective structural member 5, and the through hole 52 connects the inner and outer surfaces of the protective structural member 5. Specifically, it includes:

[0053] See Figure 9 and Figure 10 The figures show a side view and a top view of the protective structure 5 in this embodiment. Specifically, the cover-like structure is a pentahedral structure, and the lower surface of the protective structure 5 is recessed inward to form a cavity 51. That is, the protective structure 5 has a top wall and four side surfaces that are vertically connected to the periphery of the top wall.

[0054] Of course, in other embodiments of the present invention, the cover structure can also be a polyhedral structure or an arc surface structure, that is, the surface of the protective structure 5 is an arc surface. It is only necessary to ensure that the cavity 51 is formed inside the protective structure 5, and that the surface of the cavity 51 can completely cover the optical interface 21 and that the side wall of the protective structure 5 does not contact the optical interface 21.

[0055] The depth of cavity 51 is at least greater than the thickness of the electrical chip 3 and the passive component 4. The depth of cavity 51 can be designed according to actual needs (i.e. the target thickness to be reduced in the subsequent thinning process).

[0056] The surface of the protective structure 5 also has at least one through hole 52, which connects the inner and outer surfaces of the protective structure 5. Specifically, the surface of the protective structure 5 has a through hole 52, which is located inside the top wall of the protective structure 5, that is, the through hole 52 connects the inner and outer surfaces of the top wall of the protective structure 5.

[0057] Of course, in other embodiments, the top wall of the protective structure 5 may be provided with multiple through holes 52, each of which connects the inner and outer surfaces of the protective structure 5. The present invention does not limit the number of through holes 52, their specific positions on the surface of the protective structure 5, or their size, and the design can be adjusted according to actual needs.

[0058] The protective structural component 5 can be made of silicon, glass, epoxy resin or other high-temperature resistant materials, and the present invention does not limit this.

[0059] See Figure 4The aforementioned protective structure 5 is provided, with one side of the protective structure 5 having cavity 51 facing the optical interface 21, and is fixedly attached to the upper surface of the optical chip 2 corresponding to the optical interface 21, so that the optical interface 21 is completely located inside the cavity 51.

[0060] In step S4, the internal environment of cavity 51 is depressurized, specifically including:

[0061] A vacuum film pressing device is provided, which includes a vacuum device and a film pressing device.

[0062] The packaged carrier board 1, optical chip 2, electrical chip 3, and protective structure 5 are placed in a vacuum lamination device, that is... Figure 4 The encapsulation structure is placed inside a vacuum lamination device.

[0063] The vacuum device is activated, a target vacuum level is set, and the external environment of cavity 51 is depressurized until the air pressure inside cavity 51 reaches the target vacuum level. This invention does not limit the specific air pressure value achieved inside cavity 51; the process parameters can be adjusted according to the actual manufacturing process to ensure that the pressure inside cavity 51 remains at a low level and does not affect the reliability of the subsequent molding compound formation.

[0064] In step S4, a thin film layer 6 is pressed onto at least a portion of the outer surface of the protective structure 5 to make the cavity 51 a low-pressure sealed cavity, specifically including:

[0065] When the air pressure inside cavity 51 reaches the target vacuum level, the vacuum device is turned off to maintain the vacuum level inside the vacuum film pressing device.

[0066] Turn on the lamination device to cover the optical chip 2 with a thin film layer 6, ensuring that the thin film layer 6 adheres tightly to the upper and side surfaces of the protective structure 5 and the electrical chip 3, as well as the unshielded upper surface of the optical chip 2. Figure 5 As shown.

[0067] A low-pressure sealed cavity is formed between the upper surface of the optical chip 2, the inner side of the cavity 51 of the protective structure 5, and the lower surface of the thin film layer 6.

[0068] The present invention does not impose specific limitations on the thickness of the formed thin film layer 6, which can be adjusted according to actual manufacturing requirements. Preferably, a thin film layer 6 of 15~30μm is covered on top of the optical chip 2, so that the thin film layer 6 can better adhere to the surface of the object and is not easily damaged.

[0069] In a specific embodiment of the present invention, the thin film layer 6 is a membrane specifically designed for cavity devices. For example, the material of the thin film layer 6 can be one or more organic polymer membranes composed of ABF (Ajinomoto Build-Up Film), epoxy resin, and other organic polymer materials.

[0070] Furthermore, the vacuum-sealed product, i.e. Figure 5 As shown, when the encapsulation structure is removed from the vacuum lamination equipment, the air pressure on the outer surface of the thin film layer 6 rises back to atmospheric pressure, while a low-pressure space is formed inside the cavity 51. Specifically, the cavity 51 at this time is a low-pressure sealed cavity.

[0071] In step S5, forming the encapsulated body 7 specifically includes:

[0072] See Figure 6 A molding compound is provided and applied to the upper surface of the film layer 6 to form a molding compound 7, ensuring that the upper surfaces of the molding compound 7 are at the same height. The molding compound 7 uses epoxy resin as a base and contains additives such as curing agents and coupling agents, which provide mechanical support and sealing protection for the encapsulation structure.

[0073] Furthermore, the manufacturing method in this embodiment also includes the following steps:

[0074] S6: Debond the optical chip 2 to the carrier board 1.

[0075] S7: A redistribution layer 8 is formed on the side of the optical chip 2 where the electrical chip 3 is not mounted, and an electrical connection between the optical chip 2 and the redistribution layer 8 is achieved through a through-silicon via 22.

[0076] See details Figure 7 After the optical chip 2 is debonded to the carrier board 1, a redistribution layer 8 is formed on the side of the optical chip 2 where the electrical chip 3 is not attached, and the electrical connection between the optical chip 2 and the redistribution layer 8 is achieved through the through silicon via 22.

[0077] Furthermore, metal solder balls 9 are formed on the conductive pads on the bottom surface of the redistribution layer 8 for soldering to external circuit boards.

[0078] The processes for debonding the optical chip 2 to the carrier board 1, redistributing the wiring layer 8, and fabricating the metal solder balls 9 are existing technologies, and will not be described in detail here.

[0079] S8: Thin the encapsulated body 7 until the top wall of the protective structure 5 is exposed.

[0080] S9: Thin the top wall of the protective structure 5 until the optical interface 21 is fully exposed.

[0081] See Figure 8 The molding compound 7 can be thinned using grinding or laser processes. During the thinning process, part of the surface of the thin film layer 6 is first exposed, and the thinning process continues until the top wall of the protective structure 5 is exposed. Then, the thinning process continues on the plane until the optical interface 21 is completely exposed, without affecting the quality of optical port coupling at the optical interface 21.

[0082] The present invention also provides a protective structural component 5, which is used in the manufacturing method of the optoelectronic hybrid packaging structure in any of the above embodiments.

[0083] See Figure 9 and Figure 10 The protective structure 5 is a cover-shaped structure with a cavity 51 inside. The surface of the protective structure 5 is also provided with at least one through hole 52, which connects the inner and outer surfaces of the protective structure 5. When the protective structure 5 is attached to the upper surface of the optical chip 2 corresponding to the optical interface 21, the optical interface 21 is completely located inside the cavity 51.

[0084] Specifically, the cover-like structure is a pentahedral structure, with the lower surface of the protective structure 5 recessed inward to form a cavity 51. That is, the protective structure 5 has a top wall and four side surfaces that are vertically connected to the periphery of the top wall.

[0085] Of course, in other embodiments of the present invention, the cover structure can also be a polyhedral structure or an arc surface structure, that is, the surface of the protective structure 5 is an arc surface. It is only necessary to ensure that the cavity 51 is formed inside the protective structure 5, and that the surface of the cavity 51 can completely cover the optical interface 21 and that the side wall of the protective structure 5 does not contact the optical interface 21.

[0086] The present invention does not limit the depth of the cavity 51, and the depth of the cavity 51 can be designed according to actual needs (i.e. the target thickness to be reduced in the subsequent thinning process).

[0087] Specifically, a through hole 52 is provided on the surface of the protective structure 5. The through hole 52 is located inside the top wall of the protective structure 5, that is, the through hole 52 connects the inner and outer surfaces of the top wall of the protective structure 5.

[0088] Of course, in other embodiments, the surface of the protective structure 5 may be provided with a plurality of through holes 52, each through hole 52 connecting the inner and outer surfaces of the protective structure 5.

[0089] More specifically, the cross-section of the through hole 52 is circular. Of course, in other embodiments, the cross-section of the through hole 52 may also be square or polygonal.

[0090] The present invention does not limit the number of through holes 52, their specific positions on the surface of the protective structure 5, their size, or their shape; the design can be adjusted according to actual needs.

[0091] The protective structural component 5 can be made of silicon, glass, epoxy resin or other high-temperature resistant materials, and the present invention does not limit this.

[0092] In summary, this invention provides a protective structure with a through hole at the optical interface. This allows for the subsequent process of reducing the air pressure inside the cavity containing the optical interface to a lower value before applying a thin film layer. This creates a sealed, low-pressure space within the cavity, preventing excessively high air pressure from causing cracking failures during injection molding and subsequent high-temperature processes. This ensures the reliability requirements of the injection molding process and subsequent manufacturing operations are met.

[0093] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0094] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a photoelectric hybrid packaging structure, characterized in that, Including the following steps: A carrier board and an optical chip are provided. The optical chip has at least one optical interface on one side. The side of the optical chip with the optical interface is disposed on the upper surface of the carrier board, facing away from the carrier board. At least one electrical chip is provided, which is disposed on the upper surface of the optical chip and electrically connected to the optical chip; At least one protective structure is provided, the protective structure being a cover-shaped structure, a cavity is formed inside the cover-shaped structure, and at least one through hole is formed on the surface of the protective structure, the through hole connecting the inner and outer surfaces of the protective structure. The protective structure is attached to the upper surface of the optical chip corresponding to the optical interface, so that the optical interface is completely located in the cavity. The internal environment of the cavity is depressurized, and a thin film layer is pressed onto at least a portion of the outer surface of the protective structure to make the cavity a low-pressure sealed cavity; the thickness of the thin film layer is 15~30μm, and it is a special film for cavity devices. A molding compound is provided, and the molding compound is used to cover the upper surface of the thin film layer, the upper surface and side surface of the electrical chip, the unshielded upper surface and side surface of the protective structure, and the unshielded upper surface of the optical chip to form a molding compound; Specifically, the depressurization process for the internal environment of the cavity includes: providing a vacuum lamination device, which includes a vacuum device and a lamination device; placing the packaged carrier board, optical chip, electrical chip, and protective structural components inside the vacuum lamination device; activating the vacuum device; setting a target vacuum level; depressurizing the external environment of the cavity until the internal air pressure reaches the target vacuum level; and then activating the vacuum device to maintain the vacuum level within the vacuum lamination device. The method further includes the following steps: Thin the encapsulation until the top wall of the protective structure is exposed; Thin the top wall of the protective structure until the optical interface is fully exposed.

2. The method for fabricating the optoelectronic hybrid packaging structure according to claim 1, characterized in that, The method of pressing a thin film layer onto at least a portion of the outer surface of the protective structure to make the cavity a low-pressure sealed cavity specifically includes: Turn on the film pressing device to cover the optical chip with a thin film layer, and make the thin film layer adhere tightly to the upper and side surfaces of the protective structure and the electrical chip, as well as the unshielded upper surface of the optical chip; A low-pressure sealed cavity is formed between the upper surface of the optical chip, the inner side of the cavity of the protective structure, and the lower surface of the thin film layer.

3. The method for fabricating the optoelectronic hybrid packaging structure according to claim 2, characterized in that, The formation of the encapsulated body specifically includes: The molding compound is applied to the upper surface of the film layer to form the molding body, such that the upper surfaces of the molding body are at the same height.

4. The method for fabricating the optoelectronic hybrid packaging structure according to claim 1, characterized in that, The provision of at least one electrical chip, wherein the electrical chip is disposed on the upper surface of the optical chip and electrically connected to the optical chip, specifically includes: The optical chip has multiple through-silicon vias (TSVs) formed inside it, with the functional surface of the electrical chip facing the upper surface of the optical chip. The electrical connection between the electrical chip and the optical chip is achieved through the TSVs.

5. The method for fabricating the optoelectronic hybrid packaging structure according to claim 4, characterized in that, The method further includes the following steps: Debond the optical chip to the carrier board; A redistribution layer is formed on the side of the optical chip where the electrical chip is not attached, and an electrical connection between the optical chip and the redistribution layer is achieved through the through-silicon via.

6. The method for fabricating the optoelectronic hybrid packaging structure according to claim 1, characterized in that, The surface of the protective structure is provided with multiple through holes, and the cross-section of the through holes is circular.

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