A storage system and a method of reading and writing data thereof

Abstract

The application discloses a storage system and a data reading and writing method thereof. The storage system comprises m write interfaces, n read interfaces, a physical storage unit, an entry storage unit, a data moving unit and a read request processing unit. The entry storage unit comprises an idle address list and D storage spaces. Each storage space corresponds to a storage address and an address valid bit. The idle address list records the storage address with invalid address valid bit. The data moving unit comprises a queue scheduling unit and a moving request queue. The queue scheduling unit schedules the moving request queue to store data in the physical storage unit. The read request processing unit obtains data in the entry storage unit and the physical storage unit according to the read address in the read request, and outputs the combined data. The application can effectively save area and power consumption, and further reduce the cost and power consumption of chip design.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a memory system and a method for reading and writing data in the memory system. Background Technology

[0002] Memory is a device used to store programs and various data. Based on whether it is located within the chip, it can be divided into on-chip memory and off-chip memory. On-chip memory is widely used in large-scale integrated circuit design. On-chip memory is typically implemented using SRAM (Static Random-Access Memory) or by building a FA (Flop Array) using registers. Speed ​​and cost are usually important factors in selecting on-chip memory.

[0003] In high-bandwidth network chip design, multi-read-write port memory is required. This multi-read-write port memory is typically implemented in two ways: one is through a register-based FA memory, and the other is through an nRmW memory built with m×n target-size SRAMs. Here, nRmW memory refers to a memory with n read interfaces and m write interfaces.

[0004] like Figure 1 The diagram shows a schematic of a FA (Functional Availability) memory structure built using registers. As can be seen, the memory array is constructed using registers, with each bit implemented through a register and matched with corresponding read / write control logic to ultimately achieve data reading and writing. However, compared to SRAM of the same specifications, registers have a larger physical area and higher power consumption, ultimately resulting in a relatively higher area and power consumption for multi-read / write port memories. Since memory is a crucial component of a chip, increased memory area and power consumption also increase the chip's power consumption and cost.

[0005] like Figure 2 The diagram shows the structure of an mRnW memory built using m×n target-size SRAMs. In this mRnW memory, the number of read / write ports determines the required number of 1-read-1-write memory modules. For example, to build a memory with 9 read ports, 8 write ports, a depth of 16384, and a bit width of 64, 72 memory modules with 1 read port, 1 write port, a depth of 16384, and a bit width of 64 are needed. However, this would consume a large amount of physical resources and increase the cost of the chip. Summary of the Invention

[0006] The purpose of this invention is to provide a storage system that can save costs and power consumption, and also to provide a method for reading and writing data in the storage system.

[0007] To achieve the above objectives, the present invention proposes a storage system, wherein the storage system:

[0008] There are m write interfaces and n read interfaces;

[0009] A physical storage unit consists of Z basic storage units, each of which is an nR1W memory with a depth of X / Z and a width of Y, where X is the depth of the storage system and Y is the width of the storage system.

[0010] The entry storage unit includes a free address list and D storage spaces for storing write request information. Each storage space corresponds to a storage address and an address validity bit used to indicate whether the storage address is valid. The free address list is used to record storage addresses where the address validity bit is invalid. The write request information includes the write address and the write data.

[0011] The data transfer unit, connected between the entry storage unit and the physical storage unit, includes a queue scheduling unit and Z transfer request queues for storing data transfer information. Each transfer request queue corresponds to a basic storage unit. The queue scheduling unit is used to schedule the transfer request queues and store the data into the corresponding physical storage unit according to the data transfer information stored in the transfer request queues. The data transfer information includes the storage address of the written data in the entry storage unit and the storage address of the written data in the physical storage unit.

[0012] The read request processing unit is connected to each read interface, entry storage unit, and physical storage unit. It is used to obtain the data in the entry storage unit and physical storage unit respectively according to the read address in the read request, and output the data after merging the two. D≥(m-1)×(X / Z)+m×G, where m, n, X, and Z are integers greater than 1.

[0013] Preferably, the nR1W memory includes n 1R1W memories of the same specification, and the 1R1W memory is a memory with one read interface and one write interface.

[0014] Preferably, the minimum depth of the entry storage unit is (m-1)×(X / Z)+m×G, where G is the minimum delay from inputting a write request to writing the data in the write request into the physical storage unit.

[0015] Preferably, the queue scheduling unit schedules L relocation request queues each time, where L is less than or equal to Z.

[0016] Preferably, the queue scheduling unit obtains the corresponding data according to the storage address of the written data in the entry storage unit in the transfer data information, and obtains the corresponding data according to the storage address of the written data in the physical storage unit in the transfer data information, and then merges and stores it in the physical storage unit.

[0017] This invention discloses a method for writing data to a storage system, the method comprising the following steps:

[0018] S100: Receive multiple write requests and determine whether the write addresses contained in the multiple write requests are the same;

[0019] S200, in response to the same write address, merge the write data contained in multiple write requests with the same write address, and merge multiple write requests with the same write address into one write request;

[0020] S300, determine whether the write address stored in the memory space where the address valid bit is valid in the entry memory unit has the same valid address as the write address of the current write request;

[0021] S400, in response to the existence of the same valid address, obtain the storage address of the storage space, and merge the data stored at the storage address with the write data in the write request and store it in the storage address;

[0022] S500: Calculate the corresponding basic storage unit based on the write address in the write request, and further store the relocation information in the relocation request queue corresponding to the basic storage unit;

[0023] S600, the queue scheduling unit schedules the transfer request queue and stores the data in the corresponding physical storage unit according to the data transfer information stored in the transfer request queue.

[0024] Preferably, the queue scheduling unit schedules L relocation request queues each time, where L is less than or equal to Z.

[0025] Preferably, in step S600, the queue scheduling unit obtains the corresponding data according to the storage address of the written data in the entry storage unit in the transfer data information, obtains the corresponding data according to the storage address of the written data in the physical storage unit in the transfer data information, and stores the merged data in the physical storage unit.

[0026] This invention also discloses a method for reading data from a storage system, comprising:

[0027] S100: Based on the read address contained in the read request, query whether the same write address is stored in the memory space where the valid address bit is valid in the entry memory unit.

[0028] S200, in response to the existence of the same address, retrieve the corresponding data from the entry storage unit;

[0029] S300 retrieves the corresponding data from the physical storage unit based on the read address contained in the read request;

[0030] S400: The data obtained in steps S300 and S400 are merged and output.

[0031] Preferably, in step S100, the address stored in the memory space where the address valid bit is valid is the same as the read address by querying the memory space in the entry memory unit.

[0032] The beneficial effects of this invention are:

[0033] The storage system with multiple read / write interfaces described in this invention can effectively save area and power consumption, thereby reducing the cost and power consumption of chip design. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the FA memory structure in the prior art;

[0035] Figure 2 This is a schematic diagram of the existing nRmW memory structure;

[0036] Figure 3 This is a schematic diagram of the structure of a storage system according to an embodiment of the present invention;

[0037] Figure 4 yes Figure 3 A flowchart of writing data in a storage system;

[0038] Figure 5 yes Figure 3 A flowchart for reading data from the storage system. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings.

[0040] like Figure 3 The diagram illustrates a storage system according to an embodiment of the present invention. The system has a storage depth of X, a bit width of Y, and n read interfaces and m write interfaces, where X, Y, n, and m are all integers greater than 1. Specifically, the storage system includes n read interfaces, m write interfaces, a physical storage unit, an entry storage unit, a data transfer unit, and a read request processing unit.

[0041] like Figure 3As shown, a physical memory cell comprises Z basic memory cells, each with a depth of X / Z and a width of Y. The number Z of basic memory cells can be determined based on the total depth of physical memory required during chip design and the depth of individual physical memory cells in the chip process library. For example, the required depth of physical memory during chip design is usually large, such as 128K, while the depth of individual physical memory cells provided by the chip process library is limited, such as 1024K. Therefore, to implement a physical memory with a depth of 128K, it needs to be formed by splicing together a certain number of physical memory cells with a depth of 1024K. Furthermore, each basic memory cell is an nR1W memory cell with a depth of X / Z and a width of Y. Here, nR1W memory refers to a memory cell with n read interfaces and 1 write interface, and an nR1W memory cell is composed of n 1R1W memory cells of the same specification.

[0042] like Figure 3 As shown, the entry storage unit is connected to m write interfaces and includes D storage spaces. That is, the depth of the entry storage unit is D, where D ≥ (m-1) × (X / Z) + m × G, and G is the minimum latency from the input write request to the data stored in the write request reaching the physical storage unit. Each storage space can be used to store write data and write addresses. The write data includes, but is not limited to, the data to be stored in the current write request, and may also include accumulated data. The write address is used to indicate which basic storage unit in the physical storage unit the write data needs to be stored in. Each storage space corresponds to a storage address, and each storage address corresponds to an address validity bit. This address validity bit is used to identify whether the storage address is valid, i.e., whether the storage space corresponding to the storage address is occupied. When the storage space stores information related to the write request (including but not limited to write data and write addresses), the address validity bit is configured to a first preset value to indicate that the storage address corresponding to the storage space is invalid. When the storage space does not store information related to the write request, the address validity bit is configured to a second preset value to indicate that the storage address corresponding to the storage space is valid. The value of the address validity bit, namely the first preset value and the second preset value, can be set according to actual needs. For example, setting the address validity bit to 1 indicates that the storage address corresponding to the storage space is valid, that is, the storage space corresponding to the storage address stores the relevant information of the write request. Setting the address validity bit to 0 indicates that the storage address corresponding to the storage space is invalid, that is, the storage space corresponding to the storage address does not store the relevant information of the write request. Alternatively, the address validity bit can be set to 0 to indicate that the storage address corresponding to the storage space is valid, and the address validity bit can be set to 1 to indicate that the storage address corresponding to the storage space is invalid.

[0043] Furthermore, the entry storage unit also includes a free address list, which records the storage addresses corresponding to storage spaces that have not stored write addresses or write data, i.e., storage addresses where the valid address bit is invalid. Initially, since each storage space is in an idle state, the free address list stores the storage addresses corresponding to all storage spaces. When it is necessary to store information related to a write request, a storage address is selected from the free address list, and the relevant information of the write request is stored in the storage space corresponding to that storage address. At the same time, the valid address bit corresponding to that storage address is configured to a preset value, such as 1 or 0, to indicate that the storage address is valid. When the data stored in the storage space is read out and written to the physical storage unit, the valid address bit corresponding to that storage space is set to invalid, and the storage address is reclaimed to the free address list. In this embodiment, the entry storage unit is typically composed of a small-capacity cache unit, which can support multiple interfaces to read and write to it simultaneously. The minimum depth of the entry storage unit is related to the depth of the storage system, the number of write interfaces, and the internal latency of the storage system. The minimum depth of the entry storage unit is (m-1)×(X / Z)+m×G, where G is the minimum latency from the input write request to the data being stored in the write request reaching the physical storage unit. In other words, the minimum latency from the input write request to the data being stored in the write request reaching the physical storage unit is G clock cycles. By setting the minimum depth of the entry storage unit to (m-1)×(X / Z)+m×G, the resources of the entry storage unit can be optimized, and the performance requirements of m input write requests can be met.

[0044] like Figure 3 As shown, the data transfer unit connects the entry storage unit and the physical storage unit. It includes a queue scheduling unit and Z transfer request queues, each corresponding to a basic storage unit. The transfer request queues store data transfer information, including the storage address of the written data in the entry storage unit and the storage address of the written data in the physical storage unit. The queue scheduling unit schedules the transfer request queues, storing the corresponding data into the physical storage unit according to the transfer request information stored in the queues. Specifically, based on the storage address of the written data in the entry storage unit, the unit reads the data from the corresponding storage space in the entry storage unit; simultaneously, it reads the corresponding data from the storage address in the physical storage unit where the written data needs to be stored. The two sets of data are then merged, and the merged data is written back to the corresponding storage space in the physical storage unit. After data storage is complete, the storage address of the written data in the entry storage unit is reclaimed to the free address list, and the valid address bit corresponding to that address is set to invalid.

[0045] like Figure 3As shown, the read request processing unit is connected to n read interfaces, the entry storage unit, and the physical storage unit. It checks if a matching address exists in the entry storage unit based on the read address in the read request, and simultaneously retrieves the corresponding data from the physical storage unit based on the read address in the read request. The two data are then merged and output; the output data is the data to be read. In implementation, the read request processing unit checks if the write address stored in the storage space where the address validity bit is valid is the same as the read address. If they are the same, the read request processing unit further reads the write data from that storage space. If they do not exist, it directly retrieves the corresponding data from the physical storage unit based on the read address. If the read request processing unit reads data from both the entry storage unit and the physical storage unit simultaneously, it merges the two data. The merging method can be customized, such as data accumulation.

[0046] Combination Figure 4 and Figure 5 As shown, the data writing and data reading processes of the storage system described in this invention will be explained in detail.

[0047] (1) Data writing process:

[0048] The system checks if multiple concurrent write requests contain the same write address, meaning whether multiple write requests are simultaneously operating on the same address in physical storage. If so, it merges the write data from these requests (including but not limited to data accumulation) and combines them into a single write request.

[0049] Further, the system checks whether the write address stored in the storage space with a valid address bit in the entry storage unit has the same valid address as the write address contained in the current write request. If it does, the system obtains the storage address corresponding to that storage space, denoted as storage address C. The system then merges the write data contained in the write request with the write data stored in the storage space corresponding to storage address C, and writes the merged data back to the storage space corresponding to storage address C.

[0050] If no address exists, select a free storage address from the list of free addresses, denoted as storage address A, and store the write data contained in the write request in the storage space corresponding to storage address A. At the same time, set the address validity bit corresponding to storage address A to valid.

[0051] Furthermore, based on the write address in the write request, denoted as write address B, we calculate which basic storage unit in the physical storage unit it corresponds to. After obtaining the corresponding basic storage unit, we store the data migration information in the migration request queue corresponding to that basic storage unit. For example, if the write address in the write request is mapped to the Zth basic storage unit, we further store the data migration information in the storage queue corresponding to the Zth basic storage unit.

[0052] Furthermore, the queue scheduling unit schedules the transfer request queues. The queue scheduling unit schedules m transfer request queues and obtains the storage address of the write data stored in the transfer request queue in the entry storage unit. Based on the storage address, it retrieves the corresponding write data from the entry storage unit, denoted as data P. At the same time, it obtains the storage address of the physical storage unit where the write data stored in the transfer request queue needs to be written. Based on the storage address, it retrieves the corresponding write data, denoted as data Q. The two data P and Q are then merged and written into the storage space corresponding to the physical storage unit.

[0053] Furthermore, the valid address bit corresponding to the storage address of the data written in the entry storage unit in the data migration information is set to invalid, and the storage address is recycled to the free address list.

[0054] In this embodiment, during the data writing process, the queue scheduling unit schedules L transfer request queues at a time, where L is less than or equal to Z. This means the queue scheduling unit can schedule a maximum of Z transfer request queues at a time. In practice, scheduling m queues is optimal. By limiting the queue scheduling unit to a maximum of Z transfer request queues at a time, two considerations are taken into account: firstly, the logic implementation cost is considered to control the number of interfaces accessing the entry storage unit; secondly, the capacity of the entry storage unit is limited, requiring sufficient bandwidth to read the output from the entry storage unit and store it in the corresponding physical storage unit, thus avoiding overflow of the entry storage unit.

[0055] (2) Data reading process:

[0056] The system checks if a matching address exists in the entry storage unit based on the read address included in the read request. In practice, it checks if the address stored in the storage space where the address validity bit is valid matches the read address. If a matching address exists, the data in the storage space corresponding to that address is read out and denoted as data P.

[0057] Further, the corresponding data is retrieved from the physical storage unit based on the read address contained in the read request, denoted as data Q.

[0058] Furthermore, the two data points P and Q are merged and output as the final data, which is the data read out by the read request.

[0059] The storage mechanism employed in the storage system with multiple read / write interfaces described in this invention is to absorb simultaneously input write requests through an entry storage unit and schedule them by moving the request queue, so as to read the data from the entry storage unit and write it into the corresponding physical storage unit. This enables the storage system to be implemented with appropriate resources, and compared with existing storage systems, it can effectively save area and power consumption, thereby reducing the cost and power consumption of chip design.

[0060] The technical content and features of the present invention have been disclosed above. However, those skilled in the art may still make various substitutions and modifications that do not depart from the spirit of the present invention based on the teachings and disclosures of the present invention. Therefore, the scope of protection of the present invention should not be limited to the content disclosed in the embodiments, but should include various substitutions and modifications that do not depart from the present invention, and should be covered by the claims of this patent application.

Claims

1. A storage system, characterized in that, The storage system includes: There are m write interfaces and n read interfaces; A physical storage unit consists of Z basic storage units, each of which is an nR1W memory with a depth of X / Z and a width of Y, where X is the depth of the storage system and Y is the width of the storage system. The entry storage unit includes a free address list and D storage spaces for storing write request information. Each storage space corresponds to a storage address and a valid address bit to indicate whether the storage address is valid. The free address list is used to record storage addresses where the valid address bit is invalid. The write request information includes the write address and the write data. The depth of the entry storage unit is D≥(m-1)×(X / Z)+m×G, where m, n, X, and Z are integers greater than 1, and G is the minimum delay from inputting a write request to writing the data in the write request to the physical storage unit. The data transfer unit, connected between the entry storage unit and the physical storage unit, includes a queue scheduling unit and Z transfer request queues for storing data transfer information. Each transfer request queue corresponds to a basic storage unit. The queue scheduling unit is used to schedule the transfer request queues and store the data into the corresponding physical storage unit according to the data transfer information stored in the transfer request queues. The data transfer information includes the storage address of the written data in the entry storage unit and the storage address of the written data in the physical storage unit. The read request processing unit is connected to each read interface, entry storage unit, and physical storage unit. It is used to obtain the data in the entry storage unit and physical storage unit respectively according to the read address in the read request, and then output the data after merging the two.

2. The storage system according to claim 1, characterized in that, The nR1W memory includes n identical 1R1W memories, each 1R1W memory having one read interface and one write interface.

3. The storage system according to claim 1, characterized in that, The queue scheduling unit schedules L relocation request queues each time, where L is less than or equal to Z.

4. The storage system according to claim 1, characterized in that, The queue scheduling unit obtains the corresponding data based on the storage address of the written data in the entry storage unit in the transfer data information, and obtains the corresponding data based on the storage address of the written data in the physical storage unit in the transfer data information, and then merges and stores it in the physical storage unit.

5. A method for writing data based on the storage system according to any one of claims 1 to 4, characterized in that, The method includes the following steps: S100: Receive multiple write requests and determine whether the write addresses contained in the multiple write requests are the same; S200, in response to the same write address, merge the write data contained in multiple write requests with the same write address, and merge multiple write requests with the same write address into one write request; S300, determine whether the write address stored in the memory space where the address valid bit is valid in the entry memory unit has the same valid address as the write address of the current write request; S400, in response to the existence of the same valid address, obtain the storage address of the storage space, and merge the data stored at the storage address with the write data in the write request and store it in the storage address; S500: Calculate the corresponding basic storage unit based on the write address in the write request, and further store the relocation information in the relocation request queue corresponding to the basic storage unit; S600, the queue scheduling unit schedules the transfer request queue and stores the data in the corresponding physical storage unit according to the data transfer information stored in the transfer request queue.

6. The method according to claim 5, characterized in that, The queue scheduling unit schedules L relocation request queues each time, where L is less than or equal to Z.

7. The method according to claim 5, characterized in that, In step S600, the queue scheduling unit obtains the corresponding data according to the storage address of the written data in the entry storage unit in the transfer data information, and obtains the corresponding data according to the storage address of the written data in the physical storage unit in the transfer data information, and then merges and stores it in the physical storage unit.

8. A method for reading data based on the storage system according to any one of claims 1 to 4, characterized in that, include: S100: Based on the read address contained in the read request, query whether there is a write address in the memory space where the valid address bit is valid in the entry memory unit; S200, in response to the existence of the same address, retrieve the corresponding data from the entry storage unit; S300 retrieves the corresponding data from the physical storage unit based on the read address contained in the read request; S400: The data obtained in steps S300 and S400 are merged and output.

9. The method according to claim 8, characterized in that, In step S100, the address stored in the memory space where the address valid bit is valid is checked to see if it is the same as the read address.

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