GaN enhancement-mode PMOS device based on annealing diffusion and preparation method thereof

Abstract

The application discloses a GaN enhancement mode PMOS device based on annealing diffusion and a preparation method thereof. The method comprises the following steps: performing heat treatment on a substrate layer; sequentially growing a nucleation layer, a buffer layer, a back barrier layer and a p-type GaN layer on the heat-treated substrate layer; etching the device to form a mesa isolation of the device; performing partial etching on the p-type GaN of a gate region of the device to form a gate recess; depositing an n-type doped diffusion layer in the gate recess; growing a protective layer on the p-type GaN layer and the n-type doped diffusion layer; performing annealing diffusion on the device; removing all the protective layers and residual n-type doped diffusion layers; depositing source metal and drain metal on source and drain regions respectively to form source and drain electrodes; depositing a dielectric layer on the surface of the device after the source and drain electrodes are formed; depositing gate metal on the gate region to form a T-shaped gate electrode, and etching away the dielectric layer in the contact region of the source and drain electrodes. The application improves the performance of the GaN enhancement mode PMOS device.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to a GaN-enhanced PMOS device based on annealing diffusion and its fabrication method. Background Technology

[0002] GaN materials possess unique advantages such as wide bandgap, high stability, and direct bandgap, making them important semiconductor materials for manufacturing microwave power devices, power electronic devices, and light-emitting diodes.

[0003] High Electron Mobility Transistors (HEMTs) and PMOS devices based on GaN materials have developed rapidly in recent years, attracting a large number of research hotspots. Both types of devices operate through a two-dimensional electron gas or a two-dimensional hole gas generated by the GaN polarization effect. However, the high background carrier concentration and low p-type doping efficiency in GaN result in low two-dimensional hole gas concentrations in AlGaN and p-type GaN heterojunctions. Furthermore, the hole mobility is much lower than the electron mobility, leading to PMOS devices with significantly lower performance than HEMT devices. On the other hand, enhancement-mode GaN PMOS devices based on heterojunctions are often achieved through trench etching, and the large etching damage significantly reduces the hole concentration and mobility at the channel, further limiting the performance of GaN PMOS devices. In the past, researchers have implemented a series of methods to achieve high-performance enhancement-mode GaN PMOS devices, such as gate annealing repair, tetramethylammonium hydroxide (TMAH) repair, shallow etching, and ion treatment techniques.

[0004] However, neither gate annealing nor TMAH repair has the ability to repair etching damage, making it difficult to significantly improve device performance. Although the combination of shallow etching and ion treatment effectively protects the channel, ion treatment involves the accelerated bombardment process of plasma, which inevitably causes some damage to the channel, thus affecting device performance. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a GaN-enhanced PMOS device based on annealing diffusion and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, embodiments of the present invention provide a method for fabricating a GaN enhancement-mode PMOS device based on annealing diffusion, comprising:

[0007] Select a substrate layer;

[0008] The substrate layer is subjected to heat treatment;

[0009] A nucleus layer is grown on the heat-treated substrate.

[0010] A buffer layer is grown on the nucleation layer;

[0011] A back barrier layer is grown on the buffer layer;

[0012] A p-type GaN layer is grown on the back barrier layer;

[0013] The p-type GaN layer and the back barrier layer outside the active region of the device are completely etched, and the buffer layer is partially etched to form a mesa isolation of the device.

[0014] Partial etching is performed on the p-type GaN in the gate region of the device to form a gate trench;

[0015] An n-type doped diffusion layer is deposited in the gate groove;

[0016] A protective layer is grown on the p-type GaN layer and the n-type doped diffusion layer;

[0017] The device after the protective layer growth is completed is subjected to annealing and diffusion treatment to allow the n-type doped diffusion layer to diffuse into the p-type GaN layer;

[0018] Remove all the protective layers and the remaining n-type doped diffusion layer to complete the annealing and diffusion process of the gate region;

[0019] Source metal and drain metal are deposited in the source region and drain region, respectively, to form source electrode and drain electrode;

[0020] A dielectric layer is deposited on the device surface after the source electrode and the drain electrode are completed;

[0021] A T-shaped gate electrode is formed by depositing gate metal in the gate region, and the dielectric layer at the contact region between the source electrode and the drain electrode is etched away to complete the fabrication of the enhancement-mode GaN PMOS device.

[0022] In one embodiment of the present invention, the substrate layer is subjected to heat treatment, including:

[0023] The substrate layer was placed in the MOCVD reaction chamber, and the vacuum level of the MOCVD reaction chamber was reduced to less than 2 × 10⁻⁶. - 2 Torr;

[0024] A mixture of hydrogen and ammonia gas is introduced into the MOCVD reaction chamber. Under the condition that the pressure in the MOCVD reaction chamber reaches 20 Torr to 760 Torr, the substrate layer is heated to a temperature of 900°C to 1200°C and held for 5 min to 10 min.

[0025] In one embodiment of the present invention, a p-type GaN layer is grown on the back barrier layer, comprising:

[0026] A p-type GaN layer with a thickness of 30 nm to 100 nm was grown on the back barrier layer using the MOCVD process.

[0027] In one embodiment of the present invention, partial etching of the p-type GaN in the gate region of the device to form a gate trench includes:

[0028] Partial etching of p-type GaN in the gate region of the device is performed to form a gate trench with a depth of 10nm to 90nm.

[0029] In one embodiment of the present invention, an n-type doped diffusion layer is deposited in the gate trench, comprising:

[0030] An n-type doped diffusion layer with a thickness of 10 nm to 100 nm is deposited in the gate groove by sputtering or evaporation.

[0031] In one embodiment of the present invention, the n-type doped diffusion layer is silicon, germanium, or selenium.

[0032] In one embodiment of the present invention, a protective layer is grown on the p-type GaN layer and the n-type doped diffusion layer, comprising:

[0033] A protective layer with a thickness of 100 nm to 300 nm is grown on the p-type GaN layer and the n-type doped diffusion layer using PECVD or LPCVD processes.

[0034] In one embodiment of the present invention, the protective layer is silicon dioxide or silicon nitride.

[0035] In one embodiment of the present invention, the device after the protective layer growth is completed undergoes an annealing diffusion process, including:

[0036] The device with the protective layer grown is subjected to annealing diffusion treatment under the conditions of annealing diffusion temperature of 700℃~1000℃, nitrogen atmosphere, and annealing time of 10min~60min.

[0037] Secondly, embodiments of the present invention provide a GaN-enhanced PMOS device based on annealing diffusion, which is prepared by any of the preparation methods described above.

[0038] The beneficial effects of this invention are:

[0039] This invention proposes a novel method for fabricating GaN-enhanced PMOS devices based on annealing diffusion. The method involves partially etching the p-type GaN in the gate region, followed by depositing an n-type doped diffusion layer and a protective layer in the gate region, and then performing annealing diffusion. This allows the n-type dopant to diffuse into the p-type channel, thereby depleting the holes in the p-type channel under the gate and realizing a GaN-enhanced PMOS device. This method effectively avoids channel damage caused by existing methods combining etching and ion treatment, thus improving the performance of GaN-enhanced PMOS devices. Furthermore, the annealing diffusion method proposed in this invention allows for precise control of the threshold voltage of the GaN-enhanced PMOS device by controlling the annealing time and temperature. The process is relatively simple and convenient, and it has a promising market prospect for widespread application.

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0041] Figure 1 This is a schematic flowchart of a method for fabricating a GaN-enhanced PMOS device based on annealing diffusion, provided in an embodiment of the present invention.

[0042] Figure 2 (a)~ Figure 2 (m) is a schematic diagram of the structure corresponding to the method for fabricating a GaN-enhanced PMOS device based on annealing diffusion provided in the embodiments of the present invention;

[0043] Figure 3 This is a schematic diagram of the structure of a GaN enhancement-type PMOS device based on annealing diffusion provided in an embodiment of the present invention.

[0044] Explanation of reference numerals in the attached figures:

[0045] 1-Substrate layer; 2-Nucleation layer; 3-Buffer layer; 4-Back barrier layer; 5-p-type GaN layer; 6-n-type doped diffusion layer; 7-Protective layer; 8-Source electrode; 9-Drain electrode; 10-Dielectric layer; 11-T-type gate electrode. Detailed Implementation

[0046] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0047] Firstly, to improve the performance of GaN enhancement-mode PMOS devices, please refer to... Figure 1 This invention provides a method for fabricating a GaN-enhanced PMOS device based on annealing diffusion, specifically including:

[0048] S10, Select substrate layer 1.

[0049] Please see Figure 2 (a) In this embodiment of the invention, the substrate layer 1 can be a sapphire substrate, a silicon substrate, a gallium nitride substrate, or a silicon carbide substrate. The substrate layer 1 is sequentially immersed in hydrofluoric acid, acetone solution, anhydrous ethanol solution, and deionized water for ultrasonic cleaning for 5 minutes, and finally dried with nitrogen gas.

[0050] S20. Heat treatment is performed on substrate layer 1.

[0051] In this embodiment of the invention, the cleaned substrate layer 1 is placed in a metal-organic chemical vapor deposition (MOCVD) reaction chamber, and the vacuum level of the MOCVD reaction chamber is reduced to less than 2 × 10⁻⁶. -2 Torr; A mixture of hydrogen and ammonia gas is introduced into the MOCVD reaction chamber. Under the condition that the pressure in the MOCVD reaction chamber reaches 20 Torr to 760 Torr, the substrate 1 is heated to a temperature of 900℃ to 1200℃ and held for 5 min to 10 min to complete the heat treatment of the substrate 1.

[0052] S30. A nucleation layer 2 is grown on the heat-treated substrate layer 1.

[0053] Please see Figure 2 (b) In this embodiment of the invention, a GaN or AlN nucleation layer 2 with a thickness of 10 nm to 100 nm is grown on the heat-treated substrate layer 1 using MOCVD technology, more preferably a GaN or AlN nucleation layer 2 with a thickness of 30 nm. Specifically, the process conditions for growing the GaN nucleation layer 2 using MOCVD technology are: reaction chamber pressure of 20 Torr to 60 Torr, temperature of 520°C to 560°C, gallium source flow rate of 50 sccm to 100 sccm, hydrogen flow rate of 1200 sccm, and ammonia flow rate of 3000 sccm to 4000 sccm; or the process conditions for growing the AlN nucleation layer 2 using MOCVD technology are: reaction chamber pressure of 20 Torr to 60 Torr, temperature of 700°C to 900°C, hydrogen flow rate of 1200 sccm, ammonia flow rate of 200 sccm to 300 sccm, and aluminum source flow rate of 100 sccm to 300 sccm.

[0054] S40. Grow a buffer layer 3 on the nucleation layer 2.

[0055] Please see Figure 2(c) In this embodiment of the invention, a GaN buffer layer 3 with a thickness of 2 μm to 4 μm is grown on the nucleation layer 2 using MOCVD technology, more preferably a GaN buffer layer 3 with a thickness of 3 μm. Specifically, the process conditions for growing the GaN buffer layer 3 using MOCVD technology are as follows: reaction chamber pressure of 20 Torr to 60 Torr, temperature of 1000℃ to 1200℃, hydrogen flow rate of 1200 sccm, gallium source flow rate of 150 sccm to 180 sccm, and ammonia flow rate of 2000 sccm to 5000 sccm.

[0056] S50, grow a back barrier layer 4 on the buffer layer 3.

[0057] Please see Figure 2 (d) In this embodiment of the invention, an AlGaN back barrier layer 4 with a thickness of 10 nm to 30 nm is grown on the buffer layer 3 using MOCVD technology, and more preferably, an AlGaN back barrier layer 4 with a thickness of 20 nm is grown. Specifically, the process conditions for growing the AlGaN back barrier layer 4 using MOCVD technology are as follows: reaction chamber pressure of 20 Torr to 60 Torr, temperature of 1000℃ to 1200℃, Al source flow rate of 20 sccm to 50 sccm, Ga source flow rate of 100 sccm to 150 sccm, ammonia flow rate of 3000 sccm to 6000 sccm, and hydrogen flow rate of 1200 sccm.

[0058] S60. A p-type GaN layer 5 is grown on the back barrier layer 4.

[0059] Please see Figure 2 (e) In this embodiment of the invention, a p-type GaN layer 5 with a thickness of 30 nm to 100 nm is grown on the back barrier layer 4 using MOCVD technology, more preferably a p-type GaN layer 5 with a thickness of 50 nm. Specifically, the process conditions for growing the p-type GaN layer 5 using MOCVD technology are as follows: reaction chamber pressure of 20 Torr to 60 Torr, temperature of 1000 °C to 1200 °C, hydrogen flow rate of 1200 sccm, gallium source flow rate of 150 sccm to 180 sccm, ammonia flow rate of 2000 sccm to 5000 sccm, and magnesium source flow rate of 100 sccm to 200 sccm.

[0060] S70. Completely etch the p-type GaN layer 5 and the back barrier layer 4 outside the active region of the device, and partially etch the buffer layer 3 to form a mesa isolation of the device.

[0061] In this embodiment of the invention, inductively coupled plasma (ICP) is used to completely etch the p-type GaN layer 5 and the back barrier layer 4 outside the active region of the device down to the surface of the buffer layer 3, and then to partially etch the buffer layer 3 to form a mesa isolation of the device. The figure does not show a schematic diagram of the mesa isolation.

[0062] S80. Partial etching is performed on the p-type GaN in the gate region of the device to form a gate trench.

[0063] Please see Figure 2 (f) In this embodiment of the invention, the p-type GaN in the gate region of the device is partially etched in the photolithography and ICP etching process to form a gate trench with a depth of 10nm to 90nm, and more preferably, a gate trench with a depth of 20nm is formed.

[0064] S90. An n-type doped diffusion layer 6 is deposited in the gate trench.

[0065] Please see Figure 2 (g) In this embodiment of the invention, an n-type doped diffusion layer 6 with a thickness of 10 nm to 100 nm is deposited in the gate trench by sputtering or evaporation, and more preferably an n-type doped diffusion layer 6 with a thickness of 50 nm is deposited.

[0066] Preferably, the n-type doped diffusion layer 6 is silicon, germanium, or selenium.

[0067] S100, a protective layer 7 is grown on the p-type GaN layer 5 and the n-type doped diffusion layer 6.

[0068] Please see Figure 2 (h) In the embodiments of the present invention, a protective layer 7 with a thickness of 100 nm to 300 nm is grown on the p-type GaN layer 5 and the n-type doped diffusion layer 6 by plasma enhanced chemical vapor deposition (PECVD) and low pressure chemical vapor deposition (LPCVD), and more preferably a protective layer 7 with a thickness of 200 nm is grown to prevent decomposition and degradation of GaN during annealing.

[0069] Preferably, the protective layer 7 is silicon dioxide or silicon nitride.

[0070] S110. Annealing and diffusion treatment is performed on the device after the protective layer 7 has been grown, so that the n-type doped diffusion layer 6 diffuses into the p-type GaN layer 5.

[0071] Please see Figure 2(i) In this embodiment of the invention, under the conditions of an annealing diffusion temperature of 700℃~1000℃, a nitrogen atmosphere, and an annealing time of 10min~60min, the device after the protective layer 7 has been grown is subjected to an annealing diffusion treatment, so that the n-type doped diffusion layer 6, such as silicon, germanium, or selenium, diffuses into the p-type GaN layer 5, forming a structure as shown in the figure. Figure 2 (i) The gray area below the gate groove is doped with n-type by annealing diffusion, which can neutralize the holes in the p-type GaN layer 5 under the gate, thus realizing a GaN enhancement-mode PMOS device.

[0072] S120: Remove all protective layers 7 and the remaining n-type doped diffusion layer 6 to complete the annealing and diffusion process of the gate region.

[0073] Please see Figure 2 (j) In this embodiment of the invention, ICP etching process is used to remove the protective layer 7 on the p-type GaN layer 5 and the n-type doped diffusion layer 6, as well as the n-type doped diffusion layer 6 that has not diffused into the p-type GaN layer 5, to complete the annealing diffusion process of the gate region.

[0074] S130. Source metal and drain metal are deposited in the source region and drain region respectively to form source electrode 8 and drain electrode 9.

[0075] Please see Figure 2 (k) In this embodiment of the invention, photolithography and metal deposition processes are used to deposit source metal Ni / Au and drain metal Ni / Au in the source region and drain region, respectively, and annealing is performed at a high temperature of 550°C to form source electrode 8 and drain electrode 9.

[0076] S140. Deposit a dielectric layer 10 on the device surface where the source electrode 8 and drain electrode 9 are completed.

[0077] Please see Figure 2 (l) In this embodiment of the invention, plasma enhanced atomic layer deposition (PEALD) or PECVD technology is used to deposit a dielectric layer 10 with a thickness of 5nm to 40nm on the device surface after the source electrode 8 and drain electrode 9 are completed, and more preferably a dielectric layer 10 with a thickness of 20nm is deposited.

[0078] Preferably, the dielectric layer 10 is made of SiN. x Or SiO2 or Al2O3 or HfO2.

[0079] S150. Deposit gate metal in the gate region to form a T-type gate electrode 11, and etch away the dielectric layer 10 in the contact area between the source electrode 8 and the drain electrode 9 to complete the fabrication of the enhancement-mode GaN PMOS device.

[0080] Please see Figure 2 (m) In this embodiment of the invention, photolithography and metal deposition processes are used to deposit gate metal Ni / Pt / Au or Ni / Au in the gate region to form the gate electrode. The dielectric layer 10 in the contact area between the source electrode 8 and the drain electrode 9 is etched away by photolithography to finally complete the fabrication of the enhancement-mode GaN PMOS device.

[0081] In summary, the fabrication method of GaN enhancement-mode PMOS device based on annealing diffusion proposed in this invention presents a novel approach. By partially etching the p-type GaN in the gate region, followed by depositing an n-type doped diffusion layer and a protective layer 7 in the gate region and then performing annealing diffusion, the n-type dopant diffuses into the p-type channel, thereby depleting the holes in the p-type channel under the gate and realizing a GaN enhancement-mode PMOS device. This method effectively avoids channel damage caused by existing methods combining etching and ion treatment, improving the performance of the GaN enhancement-mode PMOS device. Furthermore, the annealing diffusion method proposed in this invention allows for precise control of the threshold voltage of the GaN enhancement-mode PMOS device by controlling the annealing time and temperature. It is relatively simple and convenient to implement and has a promising market prospect for widespread application.

[0082] Secondly, please see Figure 3 This invention provides a GaN-enhanced PMOS device based on annealing diffusion, characterized in that it is prepared by the fabrication method provided in the first aspect above. As the device embodiment is substantially similar to the method embodiment provided in the first aspect, its description is relatively simple; relevant details can be found in the description of the method embodiment provided in the first aspect.

[0083] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0084] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0085] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a GaN enhancement-mode PMOS device based on annealing diffusion, characterized in that, The method comprises the following steps: selecting a substrate layer; heat treating the substrate layer; growing a nucleation layer on the heat treated substrate layer; growing a buffer layer on the nucleation layer; growing a back barrier layer on the buffer layer; growing a p-type GaN layer on the back barrier layer; completely etching the p-type GaN layer and the back barrier layer outside the active region of the device, and partially etching the buffer layer, to form mesa isolation of the device; partially etching the p-type GaN in the gate region of the device to form a gate recess; depositing an n-type doped diffusion layer in the gate recess; growing a protective layer on the p-type GaN layer and the n-type doped diffusion layer; annealing and diffusing the device after the growth of the protective layer, so that the n-type doped diffusion layer diffuses into the p-type GaN layer; removing all the protective layer and the residual n-type doped diffusion layer, to complete the annealing and diffusion treatment of the gate region; depositing source metal and drain metal in the source region and the drain region respectively to form source electrode and drain electrode; depositing a dielectric layer on the surface of the device after the source electrode and the drain electrode are completed; depositing gate metal in the gate region to form a T-shaped gate electrode, and etching the dielectric layer in the contact region of the source electrode and the drain electrode, to complete the preparation of the enhancement-mode GaN PMOS device.

2. The method for fabricating a GaN enhancement-mode PMOS device based on annealing diffusion according to claim 1, characterized in that, The heat treatment of the substrate layer comprises the following steps: The substrate layer is placed in a MOCVD reaction chamber and the vacuum level of the MOCVD reaction chamber is reduced to less than 2 x 10 - 2 Torr; mixing hydrogen and ammonia gas, and heating the substrate layer to a temperature of 900-1200℃ under a pressure of 20-760 Torr in the MOCVD reaction chamber for 5-10 min.

3. The method for fabricating a GaN enhancement-mode PMOS device based on annealing diffusion according to claim 1, characterized in that, The growth of the p-type GaN layer on the back barrier layer comprises the following steps: growing a p-type GaN layer with a thickness of 30-100 nm on the back barrier layer by MOCVD process.

4. The method for fabricating a GaN enhancement-mode PMOS device based on annealing diffusion according to claim 1, characterized in that, The partial etching of the p-type GaN in the gate region of the device to form a gate recess comprises the following steps: partially etching the p-type GaN in the gate region of the device to form a gate recess with a depth of 10-90 nm.

5. The method of fabricating an anneal-diffusion-based GaN enhancement-mode PMOS device according to claim 1, wherein, The deposition of the n-type doped diffusion layer in the gate recess comprises the following steps: depositing an n-type doped diffusion layer with a thickness of 10-100 nm in the gate recess by sputtering or evaporation.

6. The method of fabricating an anneal-diffusion-based GaN enhancement mode PMOS device according to claim 1, wherein, The n-type doped diffusion layer is silicon, germanium or selenium.

7. The method for fabricating a GaN enhancement-mode PMOS device based on annealing diffusion according to claim 1, characterized in that, The growth of the protective layer on the p-type GaN layer and the n-type doped diffusion layer comprises the following steps: growing a protective layer with a thickness of 100-300 nm on the p-type GaN layer and the n-type doped diffusion layer by PECVD or LPCVD process.

8. The method of claim 1, wherein the anneal diffusion based GaN enhancement mode PMOS device is formed by: The protective layer is silicon dioxide or silicon nitride.

9. The method for fabricating a GaN enhancement-mode PMOS device based on annealing diffusion according to claim 1, characterized in that, The annealing and diffusion treatment of the device after the growth of the protective layer comprises the following steps: annealing and diffusing the device after the growth of the protective layer under the conditions of an annealing and diffusion temperature of 700-1000℃, a nitrogen atmosphere, and an annealing and diffusion time of 10-60 min.

10. An anneal-diffusion based GaN enhancement mode PMOS device, characterized in that, The device is prepared by the method of any one of claims 1-9.

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