Package structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a packaging structure and a manufacturing method thereof, wherein the packaging structure comprises: a stack, the stack comprising a plurality of stacked semiconductor devices; a plurality of electrical connection parts, the electrical connection parts being located on one side of the stack, and each electrical connection part being electrically connected to a plurality of wires of the corresponding two semiconductor devices, each wire connecting one electrical connection part and at least two semiconductor devices; wherein each wire comprises a common part and at least two connection parts connected to one end of the common part, the other end of the common part being connected to the electrical connection part, and each connection part being connected to the corresponding semiconductor device respectively. At least the problems of reflection caused by stub effect and large time delay existing in the packaging structure can be solved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to a packaging structure and a manufacturing method thereof. BACKGROUND

[0002] A packaging structure is a structure in which a semiconductor device is configured to be used as a part of an electronic product. In order to meet the needs of miniaturization and highly integrated packaging structure, the concept of a stacked package is currently proposed, which has a plurality of semiconductor devices stacked, and can meet the needs of fast processing of large capacity data while having a small footprint.

[0003] Generally, a packaging structure of a stacked package includes a substrate and a plurality of semiconductor devices stacked on the substrate, and the semiconductor devices are electrically connected to the substrate by a wire bonding process to achieve electrical connection between the semiconductor devices and the internal circuit of the substrate, and then achieve signal transmission between the semiconductor devices and the external circuit. For a packaging structure including a plurality of stacked semiconductor devices, the same electrical connection part on the substrate can be connected to two semiconductor devices of different stacking heights by two wires. SUMMARY

[0004] Embodiments of the present disclosure provide a packaging structure and a manufacturing method thereof, which at least advantageously solve the reflection problem and the large time delay problem caused by the stub effect in the packaging structure.

[0005] According to some embodiments of the present disclosure, the present disclosure provides a packaging structure, which includes: a stack, the stack including a plurality of stacked semiconductor devices; a plurality of electrical connection parts, the electrical connection parts being located on one side of the stack, and each of the electrical connection parts being electrically connected to two corresponding semiconductor devices; and a plurality of wires, each of the wires connecting one of the electrical connection parts and at least two of the semiconductor devices; wherein each of the wires includes a common part and at least two connection parts connected to one end of the common part, the other end of the common part being connected to the electrical connection part, and each of the connection parts being connected to a corresponding semiconductor device, respectively.

[0006] According to other embodiments of the present disclosure, among the at least two semiconductor devices connected to the same wire, the semiconductor device at the lowest layer is defined as a lower semiconductor device; and the connection point of the common part and the connection part is higher than the top surface of the lower semiconductor device.

[0007] According to other embodiments of the present disclosure, the distance between the connection point of the common part and the connection part and the top surface of the lower semiconductor device is less than or equal to 70 μm.

[0008] According to another aspect of the present disclosure, for the same wire, the line width of the common part is the same as the line width of the connecting part.

[0009] According to another aspect of the present disclosure, for the same wire, the material of the common part is the same as the material of the connecting part.

[0010] According to another aspect of the present disclosure, the substrate, the electric connecting part and the stack are all located on the surface of the substrate.

[0011] According to another aspect of the present disclosure, the wire includes two connecting parts; the angle between the common part and the surface of the substrate is a first angle, the angle between the two connecting parts is a second angle, the second angle is smaller than the first angle, and the second angle is smaller than 90°.

[0012] According to another aspect of the present disclosure, the two semiconductor devices electrically connected to the same wire are located in adjacent layers.

[0013] According to another aspect of the present disclosure, between the two semiconductor devices electrically connected to the same wire, there is at least one semiconductor device.

[0014] According to another aspect of the present disclosure, the stack is a vertical stack, and the side surfaces of the plurality of semiconductor devices are flush with each other.

[0015] According to another aspect of the present disclosure, the stack is a staggered stack, and the side surfaces of the plurality of semiconductor devices are staggered with each other.

[0016] According to another aspect of the present disclosure, the semiconductor device includes a chip, and the semiconductor device further includes a pad exposed by the chip, and one end of the connecting part is electrically connected to the pad.

[0017] According to another aspect of the present disclosure, the manufacturing method of the packaging structure includes the following steps: providing a stack, the stack including a plurality of stacked semiconductor devices; forming a plurality of electric connecting parts, the electric connecting parts located on one side of the stack, and each electric connecting part being electrically connected to two corresponding semiconductor devices; and forming a plurality of wires, each wire connecting one electric connecting part and at least two semiconductor devices; wherein each wire includes a common part and at least two connecting parts connected to one end of the common part, the other end of the common part being connected to the electric connecting part, and each connecting part being connected to a corresponding semiconductor device, respectively.

[0018] According to some other embodiments of the present disclosure, the process step of forming the conductive lines comprises: providing a mold having a hollow region corresponding to the shape of each of the conductive lines; pouring liquid conductive material into the hollow region and performing a cooling process to form the conductive lines; and demolding the conductive lines from the mold.

[0019] The technical solution provided by the packaging structure of the embodiments of the present disclosure has at least the following advantages:

[0020] In the technical solution of the packaging structure provided by the embodiments of the present disclosure, the stack includes a plurality of stacked semiconductor devices, a plurality of electrical connection portions are located on one side of the stack, each electrical connection portion is electrically connected to two corresponding semiconductor devices (the two semiconductor devices are connected to different RANKs), there are a plurality of conductive lines, each conductive line connects one electrical connection portion and at least two semiconductor devices, each conductive line includes a common portion and at least two connection portions connected to one end of the common portion, the other end of the common portion is connected to the electrical connection portion, and each connection portion is connected to a corresponding semiconductor device. In this way, in the two semiconductor devices connected to the same electrical connection portion in the embodiments of the present disclosure, one of the semiconductor devices is in a working state and the other semiconductor device is in an idle state, and the connection portion connected to the semiconductor device in the idle state is a stub. In the ordinary packaging structure, the stub is the entire conductive line connecting the semiconductor device in the idle state and the electrical connection portion. The packaging structure provided by the embodiments of the present disclosure shortens the length of the stub, thereby reducing the reflection of the stub on the conductive line connected to the semiconductor device in the working state and reducing the signal delay. In addition, in the packaging structure provided by the embodiments of the present disclosure, two semiconductor devices are connected to only one electrical connection portion, while in the ordinary packaging structure, two semiconductor devices are connected to two electrical connection portions or one large electrical connection portion. Therefore, the packaging structure provided by the embodiments of the present disclosure can also save the space of the substrate, which is conducive to the miniaturization and micro-miniaturization development of the packaging structure. BRIEF DESCRIPTION OF DRAWINGS

[0021] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not limiting of the embodiments and unless otherwise defined, the figures do not constitute an arrangement limitation. In order to clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, a brief introduction will be given to the drawings needed in the embodiments. Obviously, the drawings described below only constitute some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor.

[0022] Figure 1 It is a cross-sectional structure schematic diagram of a packaging structure.

[0023] Figure 2Fig. 1 is a schematic view of a cross-sectional structure of a stack in a packaging structure according to an embodiment of the present disclosure;

[0024] Figure 3 Fig. 2 is a schematic view of a cross-sectional structure of a packaging structure according to an embodiment of the present disclosure;

[0025] Figure 4 Fig. 3 is a schematic view of a cross-sectional structure of a stack in a packaging structure according to an embodiment of the present disclosure;

[0026] Figure 5 Fig. 4 is a schematic view of another cross-sectional structure of a packaging structure according to an embodiment of the present disclosure;

[0027] Figure 6 Fig. 5 is a schematic view of another cross-sectional structure of a packaging structure according to an embodiment of the present disclosure;

[0028] Figure 7 Fig. 6 is a schematic view of a step of manufacturing a lead in a manufacturing method of a packaging structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] As can be known from the background, the existing packaging structure has the problems of reflection caused by stub effect and large time delay.

[0030] REFERENCE Figure 1 and Figure 2 , Figure 1 Fig. 7 is a schematic view of a side structure of a packaging structure according to an embodiment of the present disclosure, Figure 2 Fig. 8 is a schematic view of a side structure of a stack in a packaging structure according to an embodiment of the present disclosure. The packaging structure comprises: a stack 10, the stack 10 comprising a plurality of stacked semiconductor devices 11; a plurality of electrical connection portions 20, the electrical connection portions 20 being located on one side of the stack 10, and each electrical connection portion 20 being electrically connected with two corresponding semiconductor devices 11; a plurality of leads 30, each lead 30 connecting one electrical connection portion 20 and one corresponding semiconductor device 11.

[0031] The packaging structure can further comprise: a substrate 40, the electrical connection portions 20 and the stack 10 being located on a surface of the substrate 40; an adhesive layer 12, the adhesive layer 12 being located between adjacent semiconductor devices 11, and being used for adhering the adjacent semiconductor devices 11; a pad 50, one end of the lead 30 being electrically connected with the pad 50.

[0032] The semiconductor devices 11 arranged in the stacking 10 in the direction towards the substrate 40 (i.e. arranged from top to bottom) can be respectively rank 0, rank 0, rank 1, rank 1. Among them, one pair of semiconductor devices 11 corresponding to rank 0 and one pair of semiconductor devices 11 corresponding to rank 1 are connected to the same electrical connection part 20, and the other pair of semiconductor devices 11 corresponding to rank 0 and the semiconductor devices 11 corresponding to rank 1 are connected to another electrical connection part 20.

[0033] During the operation of the stacking 10, only one of the two semiconductor devices 11 connected to the same electrical connection part 20 is in an operating state, and the other semiconductor device 11 is in an idle state. In this case where one semiconductor device 11 is operating and one semiconductor device 11 is idle, the wire 30 connected to the idle semiconductor device 11 becomes a stub, which will have a reflection effect on the wire 30 connected to the semiconductor device 11 in the operating state, causing signal delay, causing stub effect, and causing the operating state of the corresponding semiconductor device 11 to possibly be incorrect. For example, when the semiconductor device 11 is a memory, bit errors in the data transmitted by the semiconductor device 11 will occur, causing the packaging structure to fail. In addition, the strength of the stub effect is positively correlated with the length of the stub: the longer the length of the stub, the stronger the reflection effect of the stub on the wire 30 connected to the semiconductor device 11 in the operating state, the greater the signal delay, and the stronger the stub effect; the shorter the length of the stub, the weaker the reflection effect of the stub on the wire 30 connected to the semiconductor device 11 in the operating state, the smaller the signal delay, and the weaker the stub effect.

[0034] Analysis shows that in the above packaging structure, the stub is the entire wire connected between the electrical connection part and the semiconductor device, the length of the wire is relatively long, the stub effect is relatively large, the reflection intensity is relatively strong, and the signal delay is relatively large. If the length of the wire corresponding to the stub can be reduced, the above problems can be improved.

[0035] In the technical scheme of the packaging structure provided by the embodiments of the present disclosure, a wire having one common part and two connection parts is provided, wherein one end of the common part is connected to the electrical connection part, the other end is connected to the two connection parts, and the other end of the two connection parts is connected to different semiconductor devices. In the packaging structure, when the stacking is operating, the stub is the connection part, and by shortening the length of the stub, the reflection of the stub is reduced, and the signal delay is reduced. In addition, providing such a wire having one common part and two connection parts can reduce the number of electrical connection parts on the substrate, greatly saving the space of the substrate, and is conducive to the miniaturization and micro-miniaturization development of the packaging structure.

[0036] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present disclosure, many technical details are presented in order to make the readers better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and based on various changes and modifications of the following embodiments.

[0037] Figure 3 A cross-sectional structure schematic diagram of the packaging structure provided by the embodiments of the present disclosure is shown in FIG. 1. Figure 4 As shown in FIG. 1, Figure 3 A cross-sectional structure schematic diagram of the stack is shown in FIG. 2.

[0038] Reference will now be made to the drawings and embodiments illustrated in the drawings to explain the present disclosure. Figure 3 And Figure 4 The packaging structure includes: a stack 100, the stack 100 including a plurality of stacked semiconductor devices 101; a plurality of electrical connection portions 102, the electrical connection portions 102 being located on one side of the stack 100, and each electrical connection portion 102 being electrically connected to two corresponding semiconductor devices 101; a plurality of wires 103, each wire 103 connecting one electrical connection portion 102 and at least two semiconductor devices 101; wherein each wire 103 includes a common portion 113 and at least two connection portions 123 connected to one end of the common portion 113, the other end of the common portion 113 being connected to the electrical connection portion 102, and each connection portion 123 being connected to a corresponding semiconductor device 101.

[0039] In the above packaging structure, the wire 103 connecting the same electrical connection portion 102 to two different semiconductor devices 101 is provided in a structure including a common portion 113 connected to one end of the electrical connection portion 102 and a connection portion 123 connected to the other end of the common portion 113 and the two semiconductor devices 101. When one of the two semiconductor devices 101 connected to the same electrical connection portion 102 is in an active state, the common portion 113 in the wire 103 and the connection portion 123 connected to the semiconductor device 101 in the active state are in an active state, and the other connection portion 123 is in an idle state. This idle connection portion 123 acts as a stub at this time, which will reflect on the wire 103 in the active state, causing signal delay. In the embodiments provided by the present disclosure, the length of the stub is shorter, the reflection is weaker, and the signal delay is smaller. Moreover, since the number of connection points of the wire on the substrate 104 is reduced, the packaging structure provided by the embodiments of the present disclosure can also save the space of the substrate 104, which is conducive to the miniaturization and micro-miniaturization development of the packaging structure.

[0040] The embodiments of the present disclosure will be described in more detail below with reference to the drawings.

[0041] The stack 100 can include a plurality of stacked semiconductor devices 101. For example, the number of layers of the semiconductor devices 101 can be 4, 6, 8, 10, etc. Hereinafter, an example of 4 layers is described.

[0042] The semiconductor devices 101 can be wafers or chips. The plurality of semiconductor devices 101 in the stack 100 can be chips of the same kind. For example, the plurality of semiconductor devices 101 can be memory semiconductor chips. Each of the memory semiconductor chips can be, for example, a volatile memory semiconductor chip. The volatile memory semiconductor chip can be a dynamic random access memory (DRAM) or a static random access memory (SRAM). The non-volatile memory semiconductor chip can be a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). The semiconductor devices 101 can also be flash memories, for example, NAND flash memories.

[0043] In addition, the plurality of semiconductor devices 101 in the stack 100 can also include semiconductor chips of different kinds. For example, some of the plurality of semiconductor devices 101 can be logic chips, and other semiconductor chips can be memory chips. For example, each of the logic chips can be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

[0044] Figure 3 A cross-sectional structure of a package structure according to an embodiment of the present disclosure is shown in FIG. 1. The package structure includes a stack 100 and an electrical connection portion 102. The stack 100 includes a plurality of semiconductor devices 101. The electrical connection portion 102 is electrically connected to the plurality of semiconductor devices 101. Figure 3 In some embodiments, the stack 100 can be an interleaved stack. The plurality of semiconductor devices 101 can be interleaved with each other. Such an interleaved stack is advantageous in that it leaves sufficient space for a wire 103 electrically connecting the semiconductor devices 101 and the electrical connection portion 102, thereby avoiding unnecessary contact of the wire 103 with the semiconductor devices 101 and collision of the wire 103 with the semiconductor devices 101.

[0045] In some embodiments, the semiconductor device 101 includes a chip, and the semiconductor device 101 further includes a pad 106 exposed by the chip, and one end of the connecting portion 123 of the wire 103 is connected to the pad 106. The pad 106 is used for electrical connection with the circuit in the semiconductor device 101. The pad 106 can protrude from the surface of the semiconductor device 101, or the surface of the pad 106 can be flush with the surface of the semiconductor device 101. The pad 106 is usually arranged on the edge surface of the semiconductor device 101.

[0046] The material of the pad 106 can include copper (Cu), nickel (Ni), aluminum (Al), silver (Ag), gold (Au), or a combination thereof. The pad 106 can be arranged on the side edge of the semiconductor device 101 close to the electrical connecting portion 102.

[0047] Figure 4 A cross-sectional structure diagram of a stack of the packaging structure provided by an embodiment of the present disclosure is shown in FIG. 2. As shown in FIG. 2, the stack 100 includes a plurality of semiconductor devices 101 arranged in a stack. The semiconductor devices 101 are arranged in a stack in a direction perpendicular to the surface of the semiconductor device 101. Figure 4 In addition, an adhesive layer 105 can be arranged between the plurality of stacked semiconductor devices 101. The adhesive layer 105 is arranged between adjacent semiconductor devices 101, and is used to adhere the adjacent semiconductor devices 101.

[0048] The adhesive layer 105 can be a die attach film (DAF). In other embodiments, the adhesive layer 105 can not be arranged, and the adjacent semiconductor devices 101 can be in contact with each other, and the stack 100 can be formed by electrostatic bonding or chemical bonding.

[0049] Figure 5 Another cross-sectional structure diagram of the packaging structure provided by an embodiment of the present disclosure is shown in FIG. 3. As shown in FIG. 3, the stack 100 includes a plurality of semiconductor devices 101 arranged in a stack. The semiconductor devices 101 are arranged in a stack in a direction perpendicular to the surface of the semiconductor device 101. Figure 5 In other embodiments, the stack 100 can be a vertical stack, and the side surfaces of the plurality of semiconductor devices 101 are flush with each other. This stacking method can relatively reduce the size of the entire packaging structure, and is conducive to the miniaturization of the packaging structure.

[0050] The semiconductor devices 101 in the stack 100 can include two rank 0 and two rank 1. Among them, one semiconductor device 101 as rank 0 and one semiconductor device 101 as rank 1 are connected to the same electrical connection part 102, and the other semiconductor device as rank 0 and the other semiconductor device 101 as rank 1 are connected to the other electrical connection part 102. Rank refers to all memory particles connected to the same chip select (CS), and the memory controller can simultaneously read and write all semiconductor devices 101 of the same rank. The same rank semiconductor devices 101 also share the same control signal. The CS0 signal controls the operation of the rank 0 semiconductor device 101, and the CS1 signal controls the operation of the rank 1 semiconductor device 101. Therefore, the two semiconductor devices 101 connected to the same electrical connection part 102 are always in one of the working state and the idle state.

[0051] In some embodiments, the packaging structure can further include a substrate 104, and the electrical connection part 102 and the stack 100 are located on the surface of the substrate 104. The substrate 104 can be a printed circuit board (PCB), which can be a rigid PCB or a flexible PCB. In some embodiments, the electrical connection part 102 can be electrically connected with the circuit in the substrate 104, so that the semiconductor device 101 is electrically connected with the circuit in the substrate 104 via the electrical connection part 102. In other embodiments, the substrate 104 can also be a wafer carrier, and the substrate 104 serves as a carrier for carrying the electrical connection part 102 and the stack 100, and the substrate 104 can not be provided with a circuit.

[0052] In addition, the substrate 104 further includes a solder ball 108. The material of the solder ball 108 can be tin.

[0053] Correspondingly, the electrical connection part 102 can be a conductive column or a gold finger, and the material of the electrical connection part 102 can be at least one of copper (Cu), nickel (Ni) or gold (Au).

[0054] In addition, the packaging structure further includes a plurality of wires 103 having a common part 113 and two connection parts 123.

[0055] The wire 103 can convert two wires connecting the same electrical connection part 102 and two semiconductor devices 101 into one wire 103 connecting one electrical connection part 102, which can effectively save the space of the packaging structure. In addition, when one semiconductor device 101 is in a working state, only the common part 113 and one connection part 123 connected to the semiconductor device 101 in the working state are in a working state, and the other connection part 123 is in an idle state. The idle connection part 123 acts as a stub, which reflects the wire 103 in the working state and causes signal time delay. Since the stub is the connection part 123 at this time, the length of the connection part 123 is much shorter than that of the stub in the traditional packaging structure, so the reflection of the stub is smaller, and the signal time delay caused by the stub is also smaller, which can effectively improve the performance of the device.

[0056] In some embodiments, among the at least two semiconductor devices 101 connected by the same wire 103, the semiconductor device 101 at the lowermost layer is defined as the lower semiconductor device, and the connection point of the common part 113 and the connection part 123 can be higher than the top surface of the lower semiconductor device 101. The height of such a connection point can make both connection parts 123 in a shorter state, and no matter which connection part 123 is in a working state, the other connection part 123 as a stub will not have a great impact. In other embodiments, the connection point of the common part 113 and the connection part 123 can also be lower than the top surface of the upper semiconductor device 101, or the connection point of the common part 113 and the connection part 123 can also be lower than the top surface of the lower semiconductor device 101, or the connection point of the common part 113 and the connection part 123 can be flush with the top surface of the lower semiconductor device 101.

[0057] Specifically, in some embodiments, the connection point of the common part 113 and the connection part 123 can be higher than the top surface of the lower semiconductor device 101, and the distance between the connection point of the common part 113 and the connection part 123 and the top surface of the lower semiconductor device 101 can be less than or equal to 70 μm. Such a distance can maximize the length of the two connection parts 123, reducing the impact of the stub on the performance of the semiconductor device.

[0058] It should be noted that, Figure 3 In the above embodiments, the same wire 103 has two connection parts 123 and is electrically connected to two semiconductor devices 101. In other embodiments, the same wire 103 can have three or more connection parts 123, and each connection part 123 is electrically connected to a different semiconductor device 101.

[0059] In some embodiments, the line width of the common portion 113 and the line width of the connection portion 123 can be the same for the same wire 103. Since only one connection portion 123 and the common portion 113 are in working state at the same time, the line width of the common portion 113 and the line width of the connection portion 123 can be the same when in working state, which can reduce impedance and signal reflection. It can be understood that in other embodiments, the line width of the common portion 113 can also be greater than the line width of the connection portion 123, which can appropriately reduce power inductance and power noise.

[0060] It should be noted that the common portion 113 and the connection portion 123 can both be circular wires, and the line width of the common portion 113 refers to the diameter of the circular wire, and the line width of the connection portion 123 refers to the diameter of the circular wire. In other embodiments, the common portion 113 and the connection portion 123 can also not be circular wires, and the line width of the common portion 113 refers to the area of the cross section of the common portion 113, and the line width of the connection portion 123 refers to the area of the cross section of the connection portion 123.

[0061] In addition, in some embodiments, the material of the common portion 113 and the material of the connection portion 123 can be the same for the same wire 103, which can reduce signal attenuation caused by impedance. The common portion 113 and the connection portion 123 in the wire 103 can both be at least one of silver alloy bonding wire, copper wire, aluminum wire or gold wire. In other embodiments, the material of the common portion 113 can also be different from the material of the connection portion 123 for the same wire 103, for example, the resistivity of the material of the common portion 113 is less than the resistivity of the material of the connection portion 123.

[0062] In some embodiments, the wire 103 includes two connection portions 123, the angle between the common portion 113 and the surface of the substrate 104 is a first angle, and the angle between the two connection portions 123 is a second angle, which can be less than the first angle, and the second angle can be less than 90°. Such an angle range can ensure that the electrical signal can be normally and smoothly transmitted when the wire 103 is working, and also make the lengths of the two connection portions 123 as small as possible, thereby reducing the influence of the stub on the performance of the device.

[0063] It should be noted that the first angle here is the angle between the line connecting the connection point of the electrical connection portion 102 and the common portion 113 and the connection portion 123 and the surface of the substrate 104. The second angle is the angle between the line connecting the connection point of the common portion 113 and the connection portion 123 and the pad 106 of the two semiconductor devices 101 connected.

[0064] Reference Figure 5In some embodiments, there are at least one semiconductor device 101 between two semiconductor devices 101 electrically connected with the same wire 103. Since the two semiconductor devices 101 connected with the same electrical connection part 102, one of the semiconductor devices 101 is rank0, and the other semiconductor device 101 is rank1. Therefore, in the direction towards the electrical connection part 102 (i.e. from top to bottom), the arrangement of the semiconductor devices 101 can be rank0, rank0, rank1, rank1. Or in the direction towards the electrical connection part 102, the arrangement of the semiconductor devices 101 can also be rank1, rank1, rank0, rank0. In the direction towards the electrical connection part 102, the semiconductor devices 101 are arranged adjacently. This arrangement can increase the distance between the two connection parts 123 of the wire 103, so that the wire 103 is less likely to collide with the semiconductor devices 101 or other objects in the packaging structure, thereby increasing the yield of the product.

[0065] Reference Figure 6 In other embodiments, the two semiconductor devices 101 electrically connected with the same wire 103 are in adjacent layers. Since the two semiconductor devices 101 connected with the same electrical connection part 102, one of the semiconductor devices 101 is rank0, and the other semiconductor device 101 is rank1. Therefore, in the direction towards the electrical connection part 102 (i.e. from top to bottom), the arrangement of the semiconductor devices 101 can be rank0, rank1, rank0, rank1. Or in the direction towards the electrical connection part 102, the arrangement of the semiconductor devices 101 can also be rank1, rank0, rank1, rank0. In the direction towards the electrical connection part 102, the semiconductor devices 101 are arranged alternately.

[0066] In the technical scheme of the packaging structure provided by the embodiments of the present disclosure, a wire with one common part and two connection parts is provided, wherein one end of the common part is connected with an electrical connection part, and the other end is connected with the two connection parts, and the other ends of the two connection parts are connected with different semiconductor devices. Thus, in the packaging structure, the stub is the connection part when the stacked device is working, and the length of the stub is shortened, thereby reducing the reflection caused by the stub and reducing the signal delay. In addition, providing such a wire with one common part and two connection parts can reduce the number of electrical connection parts on the substrate, greatly saving the space of the substrate, and is conducive to the miniaturization and micro-miniaturization development of the packaging structure.

[0067] Another embodiment of the present disclosure also provides a manufacturing method of a packaging structure, which can be used to form the above packaging structure. The semiconductor structure provided by another embodiment of the present disclosure will be described in detail below with reference to the drawings. The same or corresponding parts as the previous embodiment can refer to the corresponding description of the previous embodiment, which will not be described in detail below.

[0068] Referring to Figures 3 to 6 A stack 100 is provided, the stack 100 comprising a plurality of stacked semiconductor devices 101; a plurality of electrical connection portions 102 are formed, the electrical connection portions 102 being located on one side of the stack 100, and each electrical connection portion 102 being electrically connected to a corresponding two semiconductor devices 101; a plurality of wires 103 are formed, each wire 103 connecting one electrical connection portion 102 and at least two semiconductor devices 101; wherein each wire 103 comprises a common portion 113 and at least two connection portions 123 connected to one end of the common portion 113, the other end of the common portion 113 being connected to the electrical connection portion 102, and each connection portion being connected to a corresponding semiconductor device 101, respectively.

[0069] In some embodiments, a substrate 104 can also be provided in the packaging structure, and the electrical connection portions 102 and the stack 100 are located on the substrate 104.

[0070] Referring to Figure 7 In some embodiments, the process steps of forming the wires 103 comprise: providing a mold 107, the mold 107 having a hollow region 117 corresponding to the shape of each wire 103; pouring liquid conductive material into the hollow region 117 and performing a cooling process to form the wires 103; and demolding the wires 103 from the mold 107. Since the wires 103 have a common portion 113 and two connection portions 123 connected to one end of the common portion 113, and the line widths of the common portion 113 and the connection portions 123 of the wires 103 are the same, and the materials are the same, the mold pouring method is used to integrally form the required wires 103. This method of forming the wires 103 integrally from the mold 107 can ensure that the line widths of the wires 103 are uniform and the materials are consistent, which can improve the stability of the semiconductor devices 101 and facilitate large-scale production and improve production efficiency.

[0071] The liquid conductive material can comprise at least one of silver alloy, copper, aluminum or gold.

[0072] In addition, a bonding layer 105 can also be included between the plurality of stacked semiconductor devices 101, the bonding layer 105 being located between the semiconductor devices 101 of adjacent layers and used to adhere the adjacent semiconductor devices 101.

[0073] The bonding layer 105 can be a die attach film (DAF). In other embodiments, the bonding layer 105 can not be provided, and the semiconductor devices 101 of adjacent layers can be in contact, and the stack 100 can be formed by electrostatic bonding or chemical bonding.

[0074] The adhesive layer 105 can include a first adhesive layer in contact with an active surface of the chip, and a second adhesive layer in contact with a back surface of another chip, the first adhesive layer having a greater elastic modulus than the second adhesive layer, the active surface generating more heat, the first adhesive layer having a greater elastic modulus and a smaller deformation, thereby ensuring the adhesive effect.

[0075] The technical scheme of the manufacturing method of the packaging structure provided by the embodiments of the present disclosure provides a method for manufacturing a lead wire having one common part and two connection parts, wherein one end of the common part is connected to an electrical connection part, and the other end is connected to the two connection parts, and the other ends of the two connection parts are connected to different semiconductor devices. The lead wire is manufactured by using a mold pouring method, which can ensure that the line width of the lead wire 103 is uniform and the material is consistent, thereby improving the stability of the semiconductor device 101 and facilitating large-scale production and improving production efficiency. In addition, the method can reduce the reflection caused by residual piles and reduce signal time delay. In addition, the method can also save a large amount of space of the substrate, which is conducive to the miniaturization and micro-miniaturization development of the packaging structure.

[0076] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present disclosure, therefore the protection scope of the present disclosure should be limited by the scope defined in the claims.

Claims

1. A package structure, characterized by, The semiconductor device includes: a stack including a plurality of semiconductor devices stacked one on another; a plurality of electrical connection portions on one side of the stack, each of the electrical connection portions being electrically connected to two corresponding semiconductor devices; a plurality of wires, each of the wires connecting one of the electrical connection portions and at least two semiconductor devices; wherein each of the wires includes a common portion and at least two connection portions connected to one end of the common portion, the other end of the common portion being connected to the electrical connection portion, each of the connection portions being connected to a pad of a corresponding semiconductor device, respectively; a substrate, the electrical connection portions and the stack being on a surface of the substrate; the wire includes two connection portions; an angle between a line connecting the electrical connection portion and a connection point of the common portion and the connection portion and the substrate is a first angle, an angle between a line connecting the connection point of the common portion and the connection portion and the pads of the two semiconductor devices connected thereto is a second angle; the second angle is smaller than the first angle, and the second angle is smaller than 90°.

2. The package structure of claim 1, wherein, of the at least two semiconductor devices connected to the same wire, a semiconductor device located at a lowermost layer is defined as a lower semiconductor device; the connection point of the common portion and the connection portion is higher than a top surface of the lower semiconductor device.

3. The package structure of claim 2, wherein, a distance between the connection point of the common portion and the connection portion and the top surface of the lower semiconductor device is smaller than or equal to 70 μm.

4. The package structure of claim 1, wherein, for the same wire, a line width of the common portion is the same as a line width of the connection portion.

5. The package structure of claim 1, wherein, for the same wire, a material of the common portion is the same as a material of the connection portion.

6. The package structure of claim 1, wherein, the two semiconductor devices connected to the same wire are located at adjacent layers.

7. The package structure of claim 1, wherein, there is at least one semiconductor device between the two semiconductor devices connected to the same wire.

8. The package structure of claim 1, wherein, the stack is a vertical stack, side surfaces of the plurality of semiconductor devices are flush with each other.

9. The package structure of claim 1, wherein, the stack is a staggered stack, side surfaces of the plurality of semiconductor devices are staggered with each other.

10. The package structure of claim 1, wherein, the semiconductor device includes a chip, and the semiconductor device further includes a pad exposed by the chip, one end of the connection portion being electrically connected to the pad.

11. A method of manufacturing a package structure, characterized by: The semiconductor device includes: providing a stack including a plurality of semiconductor devices stacked one on another, and placing the stack on a substrate; forming a plurality of electrical connection portions on the substrate, each of the electrical connection portions being electrically connected to two corresponding semiconductor devices; forming a plurality of wires, each of the wires connecting one of the electrical connection portions and at least two semiconductor devices; wherein each of the wires includes a common portion and at least two connection portions connected to one end of the common portion, the other end of the common portion being connected to the electrical connection portion, each of the connection portions being connected to a pad of a corresponding semiconductor device, respectively; wherein the wire includes two connection portions; an angle between a line connecting the electrical connection portion and a connection point of the common portion and the connection portion and the substrate is a first angle, an angle between a line connecting the connection point of the common portion and the connection portion and the pads of the two semiconductor devices connected thereto is a second angle; The second included angle is smaller than the first included angle, and the second included angle is smaller than 90°.

12. The production method according to claim 11, wherein The process steps for forming the conductive lines include: providing a mold having hollow regions corresponding to the shapes of the conductive lines; pouring liquid conductive material into the hollow regions and performing a cooling process to form the conductive lines; and demolding the conductive lines from the mold.

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