Finfet device with enhanced on-resistance and breakdown voltage

Abstract

The present disclosure relates to fin-based field effect transistor (finFET) devices with enhanced on-resistance and breakdown voltage. The finFET devices can include a fin structure having a first portion, a second portion, and a third portion. The finFET devices can include a first gate structure disposed over at least a portion of the first portion, a first source / drain region disposed in the first portion, and a second drain / source region disposed in the third portion. Each of the first, second, and third portions can include one or more fin portions. A total fin count in the second portion is less than a total fin count in the first portion. The second portion can include a drift region. Methods of fabricating finFETs are also disclosed. The finFET devices provide lower on-resistance and higher breakdown voltage than conventional finFETs.

Description

Technical Field

[0001] This description generally relates to transistors, including but not limited to fin-based field-effect transistor (finFET) devices with enhanced on-resistance and breakdown voltage. Background Technology

[0002] Integrated circuits (ICs) can include microprocessors, microcontrollers, static random access memory, communication circuits, digital logic circuits, and other circuits, as well as combinations of those circuits fabricated on a substrate. ICs can include devices such as transistors. As IC devices continue to scale down to smaller sizes, various designs and techniques are employed to improve device performance. For example, fin-based field-effect transistor (finFET) structures can be used as an alternative to planar metal-oxide-semiconductor field-effect transistor (MOSFET) structures and offer improved scalability. Fin-based fabrication techniques can be used to create non-planar structures on semiconductor substrate materials (e.g., silicon), which can increase device density because channels, sources, and / or drains protrude from the semiconductor substrate material in the form of fins.

[0003] The descriptions provided in the background section should not be assumed to be prior art simply because they are mentioned in or associated with the background section. The background section may contain information describing one or more aspects of the art. Summary of the Invention

[0004] In one aspect, this disclosure relates to a fin-based field-effect transistor (finFET) device comprising: a fin structure including a first portion, a second portion, and a third portion; a first gate structure disposed on at least a portion of the first portion; a first source / drain region disposed in the first portion; and a second drain / source region disposed in the third portion, wherein: each of the first, second, and third portions includes one or more fins; and the total number of fins in the second portion is less than the total number of fins in the first portion.

[0005] In another aspect, this disclosure relates to a fin-based field-effect transistor (finFET) device, comprising: a fin structure including a first portion, a second portion, and a third portion; a first gate structure disposed on at least a portion of the first portion; a first source / drain region disposed in the first portion; and a second drain / source region disposed in the third portion, wherein: each of the first, second, and third portions includes one or more fins; the first fin in the first portion is connected to the first fin in the third portion via the first fin in the second portion; and the second fin in the first portion is separated from the second fin in the third portion by at least one separating region in the second portion.

[0006] In another aspect, this disclosure relates to a method of manufacturing a fin-based field-effect transistor (finFET) device, comprising: providing a fin structure including a first portion, a second portion, and a third portion; providing a first source / drain region in the first portion; providing a second drain / source region in the third portion; and providing a first gate structure over at least a portion of the first portion, wherein: each of the first, second, and third portions includes one or more fins; and the total number of fins in the second portion is less than the total number of fins in the first portion. Attached Figure Description

[0007] Figure 1A A plan view illustrating an example of a finFET device.

[0008] Figure 1B Illustrate an example of a dual-drain region.

[0009] Figure 2 Explain the line AA' along the direction parallel to the fin length. Figure 1A An example of a cross-sectional view of a finFET device depicted in the image.

[0010] Figure 3 Explain the line BB' along the direction parallel to the fin length. Figure 1A An example of a cross-sectional view of a finFET device depicted in the image.

[0011] Figure 4 Explain the line CC' along the direction parallel to the fin length. Figure 1A An example of a cross-sectional view of a finFET device depicted in the image.

[0012] Figure 5 A flowchart illustrating an example of manufacturing operations used to form a finFET device.

[0013] Figure 6 A block diagram illustrating an example of an integrated circuit.

[0014] Figure 7 This section describes the current and voltage characteristics of an example finFET device.

[0015] Figure 8 A top plan view illustrating another example of a finFET device.

[0016] In the figures, the same reference numerals may generally indicate the same, functionally similar, and / or structurally similar elements. In one or more embodiments, not all of the components depicted in each figure may be required, and one or more embodiments may include additional components not shown in the figures. Variations in the arrangement and type of components may be made without departing from the scope of this disclosure. Within the scope of this disclosure, additional components, different components, or fewer components may be utilized. Detailed Implementation

[0017] The detailed description provided below is intended to describe various embodiments and is not intended to represent the only embodiment in which the present technology can be practiced. Those skilled in the art will recognize that the described embodiments can be modified in various ways without departing from the scope of this disclosure. Therefore, the figures and descriptions are to be considered illustrative and non-limiting in nature. Furthermore, for ease of illustration, identical or similar components are illustrated with the same or similar reference numerals. Descriptions provided with respect to components having given reference numerals in one or more figures are applicable to components having the same given reference numerals shown in one or more other figures, unless otherwise stated or provided.

[0018] In one or more embodiments, the fin-based field-effect transistor (finFET) device has a laterally double-diffused metal-oxide-semiconductor (LDMOS) structure (e.g., a superjunction LDMOS structure). The LDMOS structure may include multiple alternating regions of, for example, n-type and p-type doped semiconductors. In one or more embodiments, the structure and fabrication process allow for smaller devices that can operate at higher voltages and have lower on-resistance (Ron). In one or more embodiments, the finFET device architecture provides compatibility with fabrication processes for finFET-based complementary MOS (CMOS) devices, including smaller technologies such as 5nm, 7nm, 14nm, and 16nm. In one or more embodiments, the enhanced finFET device can be fabricated using, for example, a 5nm process, and this enhanced finFET can provide low Ron with high breakdown voltage. In one or more aspects, no additional masking or process steps are required to provide the enhanced finFET device.

[0019] In one or more embodiments, the fabrication process of the finFET structure and its operation advantageously reduces the adverse effects associated with the tighter fin spacing of finFET technology scaled down to smaller sizes (e.g., 5nm). Tighter fin spacing can result in thinner fins, which degrades performance, especially when using protruding source / drain epitaxial (EPI) processes. Therefore, as smaller-scale processes are developed, finFETs with similar characteristics may require larger silicon (Si) areas. In one or more embodiments, enhancement-mode finFET structures improve the overall performance of finFET devices fabricated using smaller-scale processes and provide lower Ron and higher breakdown voltage than conventional finFETs. Enhancement-mode finFET structures can be incorporated into integrated circuits that utilize supply voltages such as 0.65V, 0.75V, 1.8V, 3.3V, and 5V without the disadvantages associated with the tighter fin spacing of some finFETs.

[0020] Figure 1A This is a plan view illustrating an example of a finFET device. The finFET device 100 may include two or more fins 101a to e extending from the left end to the right end of the finFET device. In one aspect, the fins 101a to e do not touch the left and right ends. For example, the fins 101a to e may extend across segments 1 to 5, except in this example, the fins 101a to e do not include two outer fins in each of segments 2 and 4 (e.g., fins 108.1a and 108.1e are not present in segment 2 of segments 2T and 2B respectively, and fins 108.2a and 108.2e are not present in segment 4; therefore, these are not shown in...). Figure 1A (In the middle). The number of fins 101a to e can be any number greater than 1 (e.g., from 2 to 20 or more, depending on system requirements and device characteristics). In one or more embodiments, lower Ron and higher current requirements can be achieved by utilizing more fins 101a to e.

[0021] The finFET device 100 includes a substrate 105 or is disposed on or within the substrate 105. The fin structure may include multiple fins, such as fins 101a to e. The fin structure may have multiple portions, such as a first portion (in or across segment 1), a second portion (in or across segment 2), a third portion (in or across segment 3), a fourth portion (in or across segment 4), and a fifth portion (in or across segment 5). The first portion may include fins 102a to e (in or across segment 1). The second portion may include fins 108.1b to d (in or across segment 2). The third portion may include fins 103a to e (in or across segment 3). The fourth portion may include fins 108.2b to d (in or across segment 4). The fifth section may include fins 109a to e (in or across segment 5). Fins 102a to e may include fins 104.1a to e and 106.1a to e, respectively. Fins 109a to e may include fins 106.2a to e and 104.2a to e, respectively. Fins 103a to e may include fins 107a to e, respectively. Fins 101a to e may be disposed above the top surface (or first surface) of the substrate 105.

[0022] In one or more embodiments, fins 101a to e and their portions are parallel to each other and parallel to the direction of fin length, generally rectangular in shape, and formed in rows. In one or more examples, fins 101a to e may comprise undoped Si formed by an epitaxial process. For an N-channel device, the source and drain 104.1a to e, 104.2a to e, and 107a to e may comprise highly concentrated N-type doped Si formed by an epitaxial process. The regions between the fin portions within the respective segments (e.g., the first region 104.11a to d, the third region 108.11b to c, the fourth region 107.11a to d, the fifth region 108.22b to c, and the sixth region 104.22a to d) may comprise a dielectric material, such as silicon dioxide.

[0023] In one or more embodiments, the width of each fin can be 4 to 10 nm, and the distance or spacing between fins can be 20 to 50 nm. In one or more embodiments, the length of each of fins 102a to e can be 50 to 100 nm, the length of each of sources 104.1a to e and 104.2a to e can be 50 to 100 nm, the length of each of channel portions 106.1a to e and 106.2a to e can be 120 to 600 nm, the length of each of fins 108.1b to d and 108.2b to d can be 60 to 250 nm, and the length of each of fins 103a to e can be 50 to 150 nm. The dimensions provided herein are non-limiting embodiments, and the technology can be used in other embodiments.

[0024] In one or more embodiments, fins 102a to e may include or be associated with corresponding source portions 104.1a to e and corresponding channel portions 106.1a to e disposed within or associated with fins 102a to e. Fins 103a to e may include or be associated with corresponding drain portions 107a to e disposed within or associated with fins 103a to e. Fins 109a to e may include or be associated with corresponding channel portions 106.2a to e and corresponding source portions 104.2a to e disposed within or associated with fins 109a to e. In one or more embodiments, source portions 104.1a to e and 104.2a to e are interchangeable with drain portions 107a to e. In one or more embodiments, the finFET device 100 may be an N-channel or P-channel device. The terms source / drain region and drain / source region may refer to a source region or a drain region. For example, the first source / drain region may include source 104.1a to e, the second drain / source region may include drain 107a to e, and the third source / drain region may include source 104.2a to e. The channel portions 106.1a to e and 106.2a to e may sometimes be referred to as fin portions 106.1a to e and 106.2a to e.

[0025] The finFET 100 may include one or more gate structures (e.g., gate 1 and gate 2). Gate 1 may be disposed over at least a portion of a first portion of the fin structure (in or across segment 1) (e.g., over fin portions 106.1a to e). Gate 2 may be disposed over at least a portion of a fifth portion of the fin structure (in or across segment 5) (e.g., over channel portions 106.2a to e). Each of gates 1 and 2 is substantially perpendicular to the fin length. Gates 1 and 2 may be interconnected using one or more conductive layers (not shown).

[0026] The finFET 100 may also include one or more dummy gate structures (e.g., dummy gate 1, dummy gate 2, dummy gate 3, and dummy gate 4). In one or more instances, the finFET manufacturing process generates dummy gates to facilitate the fabrication of various components of the finFET device. However, the dummy gates are not used as actual gates during finFET device operation. The finFET 100 also includes one or more sources (e.g., source 1 and source 2). Source 1 may include source 104.1a to e, and source 2 may include source 104.2a to e. Sources 1 and 2 may be interconnected using one or more conductive layers (not shown). The finFET 100 also includes a drain (e.g., drain 1). Drain 1 may include drain 107a to e.

[0027] In one or more embodiments, the finFET device 100 includes drift regions (e.g., drift region 1 and drift region 2). A second portion of the fin structure may include drift region 1 (in or across segment 2), and a fourth portion of the fin structure may include drift region 2 (in or across segment 4). Drift region 1 may include fin portions 108.1b to d, and drift region 2 may include fin portions 108.2b to d.

[0028] In one or more embodiments, each of the drift regions (or each of the second and fourth portions) may contain fewer fins than the other portions of the fin structure. In one or more instances, the total number of fins in the second portion (e.g., the total number of fins 108.1b to d in or across segment 2) is less than the total number of fins in the first portion (e.g., the total number of fins 102a to e in or across segment 1). The total number of fins in the second portion may be 1 or greater than 1, but not less than 1. In this example, the total number of fins in the fourth portion (e.g., the total number of fins 108.2b to d in or across segment 4) is the same as the total number of fins in the second portion. In this example, the total number of fins in the first portion is the same as the total number of fins in each of the third and fifth portions.

[0029] In one or more embodiments, with respect to each of the second and fourth portions (respectively, in or across segments 2 or 4), the top and bottom outer portions (e.g., for segments 2T and 2B of segment 2) do not have fins. In one or more instances, the top outer portion of the second portion (e.g., segment 2T) does not contain fins. In one or more instances, the bottom outer portion of the second portion (e.g., segment 2B) does not contain fins. In one or more instances, the middle portion of the second portion (e.g., segment 2M) contains at least one fin. A similar arrangement applies to the fourth portion.

[0030] In one or more embodiments, having fewer fins in the second portion compared to each of the first and third portions provides lower Ron and higher breakdown voltage. In one or more embodiments, having fewer fins in each of the second and fourth portions compared to each of the first, third, and fifth portions provides lower Ron and higher breakdown voltage.

[0031] In one or more instances, the fins in each of the second and fourth sections are preferably symmetrical about the centerline of the corresponding section (e.g., line AA' in this instance). In one or more instances, it is preferred that the fins (e.g., 108.1b to d and 108.2b to d) are positioned in the middle portion (rather than the top and bottom outer portions) of each of the second and fourth sections to minimize the effects of, for example, process variations. In this instance, each of the fins 101b to d (positioned in the middle portion) exists in the first, second, third, fourth, and fifth sections of the fin structure. In this instance, each of the fins 101a and 101e (positioned in the top and bottom outer portions) exists only in the first, third, and fifth sections of the fin structure. The second and fourth sections of the fin structure do not include the fins of fins 101a and 101e (i.e., the outer fins).

[0032] Figure 1A This describes the top outer portion 1T, middle portion 1M, and bottom outer portion 1B in the first part (e.g., in or across segment 1); the top outer portion 2T, middle portion 2M, and bottom outer portion 2B in the second part (e.g., in or across segment 2); and the top outer portion 3T, middle portion 3M, and bottom outer portion 3B in the third part (e.g., in or across segment 3). Although in Figure 1A Not explicitly shown, but the fourth part (e.g., in or across segment 4) has a top outer portion, middle portion, and bottom outer portion similar to the second part. Although in Figure 1A It is not explicitly shown, but the fifth part (e.g., in or across section 5) has a top outer portion, middle portion and bottom outer portion similar to the first part.

[0033] In one or more embodiments, a first fin in the first portion (e.g., each of 102b, 102c, and 102d) is connected to a first fin in the third portion (e.g., 103b, 103c, and 103d, respectively) via a first fin in the second portion (e.g., 108.1b, 108.1c, and 108.1d, respectively). A second fin in the first portion (e.g., each of 102a and 102e) is separated from a second fin in the third portion (e.g., 103a and 103e, respectively) by at least one separating region in the second portion. The separating region may be, for example, a region in the second portion between the right edge of the fin in the first portion and the left edge of the fin in the third portion. Similarly, the third fin in the fifth part (e.g., each of 109b, 109c, and 109d) is connected to the first fin in the third part (e.g., 103b, 103c, and 103d, respectively) via the third fin in the fourth part (e.g., 108.2b, 108.2c, and 108.2d, respectively). The fourth fin in the fifth part (e.g., each of 109a and 109e) is separated from the second fin in the third part (e.g., 103a and 103e, respectively) by at least one second dividing region in the fourth part. The second dividing region may be, for example, the region in the fourth part between the right edge of the fin in the third part and the left edge of the fin in the fifth part.

[0034] In one or more embodiments, the second portion (e.g., spanning segment 2) may include a drift region (e.g., drift region 1). The second portion does not include any gate structure (e.g., gate 1), any source / drain region (e.g., source 1), or any second drain / source region (e.g., drain 1). Similarly, the fourth portion (e.g., spanning segment 4) may include a drift region (e.g., drift region 2). The fourth portion does not include any gate structure (e.g., gate 2), any source / drain region (e.g., source 2), or any second drain / source region (e.g., drain 1).

[0035] Figure 1A The finFET device 100 shown includes two gate structures (e.g., gates 1 and 2), two source regions (e.g., source 1 and 2), and a drain region (e.g., drain 1). In this example, the component may be symmetrical about plane DD' (the middle line in segment 3) and also about line AA'.

[0036] In another embodiment, the finFET device may include a gate structure (e.g., gate 1), a source region (e.g., source 1), and a drain region (e.g., drain 1), but not a second gate structure (e.g., gate 2) or a second source region (e.g., source 2). In this example, the finFET device may include components in segments 1, 2, and 3, but... Figure 1ASections 4 and 5 do not contain components.

[0037] In yet another embodiment, the drain region of the finFET device may have a dual drain region, such as... Figure 1B It is displayed in the middle. Figure 1B Explain section 3', which is Figure 1A The modified version of section 3. The dual-drain region may contain three dummy gates (e.g., dummy gates A, B, and C in parallel) instead of two dummy gates. The dual-drain region may have fins 103'a to e that are longer than fins 103a to e to accommodate the three dummy gates. Fins 103'b to d may be connected to fins 108.1b to d and 108.2b to d. Fins 103'a and 103'e are separate from fins 102a and 109a, and from fins 102e and 109e, respectively. The dual-drain region may have two sets of drains (e.g., drain 1' and drain 1"). The first set of drains 107'a to e may be disposed between dummy gates A and B. The second set of drains 107"a to e may be disposed between dummy gates B and C. A dual-drain region (having two drain regions instead of one) provides reduced resistance, lower electric field, and less current congestion. In one example, segment 3' can replace segment 3 to create a finFET device with two gate structures, two source regions, and a dual-drain region. This finFET includes segments 1, 2, 3', 4, and 5. In another example, segment 3' can replace segment 3 to create another finFET device with one gate structure, one source region, and a dual-drain region. This finFET includes segments 1, 2, and 3'.

[0038] Figure 2 Explain the line AA' (along fin 101c) between plane FF' and plane EE'. Figure 1A An example of a cross-sectional view of a FinFET device 100 depicted herein includes segments 1, 2, and 3. The FinFET device 100 includes a substrate 105, which may have a top substrate 105A and a bottom substrate 134. The top substrate 105A may include a dielectric material 111, a well region 114, and a well region 115. Figure 2 In the finFET device 100, there is a portion of fin 102c, a source 104.1c in fin 102c, a channel portion 106.1c in fin 102c, a fin 108.1c, a left portion of fin 103c, a drain 107c in fin 103c, and a right portion of fin 103c.

[0039] refer to Figure 1A and 2The finFET device 100 includes a gate 1 and a drift region 1. The drift region 1 (having a fin 108.1c) is above a first surface 185 (or top surface) of the substrate 105. The dielectric material 111 may be a trench, such as a shallow trench isolation (STI) region in one or more embodiments. In one or more embodiments, the trench may be a deep trench isolation region or a locally grown isolation region. The trench may be, for example, silicon dioxide. The drift region 1 and the fin 108.1c are above a first portion of the well region 115 and not above any trench.

[0040] In one or more embodiments, source 1 (including source 104.1c) includes a highly doped region (N-type), for example... Figure 2 Region 133. In one or more embodiments, drain 1 (including drain 107c) includes a highly doped region (N-type), for example, region 139. In one or more instances, regions 133 and 139 are epitaxial doped regions (e.g., in-situ phosphorus doped). In one or more embodiments, region 133 includes a doped epitaxial region 143 (e.g., N-type), and region 139 includes a doped epitaxial region 149 (e.g., N-type). In one or more instances, region 133 is disposed in or above fin 102c, and region 139 is disposed in or above fin 103c.

[0041] Substrate 105 includes a bottom substrate 134 (e.g., a bulk silicon substrate lightly doped with a p-type dopant such as boron) and a top substrate 105A, said top substrate 105A being doped to form well regions 114 and 115 which may have different doping (e.g., different types of dopants). In one or more embodiments, well region 114 is a p-well and well region 115 is an n-well. The bottom substrate 134 is below well regions 114 and 115 and is a lightly doped p-type region in one or more embodiments.

[0042] In one or more embodiments, substrate 105 may be a p-type substrate. Well region 115 and epitaxial regions 133 and 139 (including 143 and 149) contain n-type dopants. Well region 114 contains p-type dopants. The finFET device 100 formed by this arrangement of p-type and n-type regions may be referred to as a superjunction n-type LDMOS (NLDMOS) device with a single drain or dual drain having an associated NLDMOS doping profile. Well region 114 (e.g., a p-well region) may be depleted by a neighboring n-region (e.g., well region 115). For a p-type LDMOS (PLDMOS) device, the p-type and n-type regions are reversed from the previous description (e.g., well region 114 is doped with n-type dopants, well region 115 is doped with p-type dopants, regions 133 and 139 (including 143 and 149) are doped with p-type dopants, etc.); however, the bottom substrate 134 may be lightly doped with p-type dopants. In one or more instances, both the top substrate 105A and the bottom substrate 134 are bulk substrates. In another instance, the top substrate 105A is an epitaxial growth layer, and the bottom substrate 134 is a bulk substrate.

[0043] In one or more embodiments, well region 115 may have a lower doping concentration than epitaxial regions 133 and 139 (including 143 and 149). Bottom substrate 134 may have a lower doping concentration than well regions 114 and 115. In one or more examples, portions 102c (including portions 106.1c), 108.1c, and 103c are undoped silicon and epitaxially grown. Portions 133 and 139 (including 143 and 149) are highly doped n-type regions and epitaxially grown. Portions 102c (including portions 106.1c), 108.1c, and 103c have a lower doping concentration than portions 133 and 139 (including 143 and 149).

[0044] For p-type doping, boron can be used as a dopant material. For n-type doping, phosphorus or arsenic can be used as dopant materials. The doping concentration of well regions 115 and / or 114 can be 10. 18 cm -3 With 10 19 cm -3 Between. The doping concentration of epitaxial regions 133 and 139 (including 143 and 149) can be between 10. 20 cm -3 With 10 21 cm -3 The dopant material and doping concentration are provided through non-limiting examples, and other dopant materials and doping concentrations may be used. The type of dopant (e.g., p-type, n-type), dopant material, and doping concentration may be selected based on, for example, device characteristics (e.g., threshold voltage requirements).

[0045] In one or more embodiments, the source contact and drain contact may be coupled to epitaxial region 143 and epitaxial region 149, respectively. Gate 1 is disposed on three sides of fin portion 106.1c of fin 101c between source 1 (e.g., epitaxial region 133) and drift region 1.

[0046] The example bias voltages applied to the source contact, gate (e.g., gate 1), and drain contact can be 0V, 1.8V, and 3.3V, respectively. In one or more embodiments, gate 1 can be biased to deplete the channel beneath gate 1. In one or more embodiments, epitaxial region 133 can allow depletion of portion 106.1c of portion 102c. Channel current path 290a is provided from drain 1 (or epitaxial region 139) to source 1 (or epitaxial region 133) through the left portion of fin 103c, through fin 108.1c, and through channel portion 106.1c. This path provides more than one or more well regions (e.g., such as...). Figure 3 The path shown in the image is lower for Ron.

[0047] A drain 107c (including an epitaxial region 139) may be formed in a portion 103c defined by two dummy gate structures (e.g., dummy gates 2 and 3). The dummy gate structure 160 of dummy gate 2 may include a spacer 162 and a dummy gate material 164. The dummy gate structure 214 of dummy gate 3 may include a spacer 218 and a dummy gate material 216. An end 202 of portion 102c is covered by a dummy gate structure 204 of dummy gate 1 (including dummy gate material 206 and spacer 208). The dummy gate structure 204 is disposed over at least a portion of a dielectric material 111. An edge of the dielectric material 111 may be aligned with the end 202. The source 1, gate 1, and drain 1 may be connected to their respective contacts or electrodes. Regions above the dummy gates, source 1, gate 1, and drain 1 that are not filled with contacts and electrodes may be filled with dielectric material. The drift region 1 above part of 108.1c may be filled with dielectric material.

[0048] Drift region 1 (e.g., portion 108.1c) may be defined by the structure of gate 1 and the dummy gate structure 160 of dummy gate 2. The structure of gate 1 may include spacers 182. Spacers 208, 182, 162, and 218 and associated dummy gate material limit the ends or sides of fins 101a to e to protect them from lateral and other growth during epitaxy.

[0049] Gate 1 includes gate conductor 152. Gate conductor 152 may be a metallic material or a doped polysilicon material. Gate conductor 152 is disposed above channel portion 106.1c and above first surface 185 of substrate 105. Gate conductor 152 may cover three sides of portion 106.1c of fin 101c that does not contact surface 185 of substrate 105.

[0050] Gate 1 (gate conductor 152) is disposed above boundary 189 between well regions 114 and 115. Spacers 208, 182, 162, and 218 are dielectric materials, such as silicon dioxide, silicon nitride, etc. Gate 1 may comprise a gate oxide material, a gate dielectric material, and a work function metal. For ease of understanding, oxide materials, dielectric materials, and work function metals are not shown in the figures.

[0051] Although Figure 2 This is about the fin 101c specification, but specifically for... Figure 2 The provided descriptions may describe fins 101b and 101d in the same or similar manner. Although Figure 2 This describes segments 1, 2, and 3 of finFET 100 along line AA', but for... Figure 2 The provided description may describe segments 4 and 5 along line AA' in the same or similar manner, since the finFET 100 is symmetrical about plane DD'.

[0052] Figure 3 Explain the line BB' (along fin 101e) between plane FF' and plane EE'. Figure 1A Examples of cross-sectional views of a finFET device depicted include segments 1, 2, and 3. Regarding... Figure 1A , 1B The description provided for the components with given reference figures in section 2 is applicable to components having... Figure 3 Components that are shown with the same given reference figures, unless otherwise stated or provided.

[0053] refer to Figure 3 The finFET device 100 includes a bottom substrate 134 and a top substrate 105A, which have dielectric materials 111, 110e, 112e, a well region 114, and a well region 115. The finFET device 100 includes a left portion of a fin 102e, a source 104.1e in the fin 102e, a channel portion 106.1e in the fin 102e, a left portion of a fin 103e, a drain 107e in the fin 103e, and a right portion of the fin 103e.

[0054] Unlike Figure 2 , Figure 3 The channel portion 106.1e is separated from portion 103e. The separation distance may be at least one separation region 308 in segment 2. The separation distance may further include a first distance between the right edge 154 of portion 106.1e and the left end of separation region 308 and a second distance between the right end of separation region 308 and the left end 144 of portion 103e.

[0055] Unlike Figure 2 , Figure 3 The well region 115 comprises dielectric materials 110e and 112e. Dielectric materials 110e and 112e may be formed in the same or similar manner as dielectric material 111 and have the same or similar composition. Like dielectric material 111, dielectric materials 110e and 112e may be trenches, such as STI regions. The left edge of dielectric material 110e may be aligned with the right edge 154 of portion 106.1e. The right edge of dielectric material 110e may be aligned with the left end 144 of portion 103. The left edge of dielectric material 112e may be aligned with the right end 212 of portion 103e. There are no fins above or on dielectric material 110e. A partition region 308 in the second portion is above a portion of well region 115 and at least a portion of dielectric material 110e, which is a trench or STI. The partition region may be filled with dielectric material.

[0056] The separation region 308 can be defined by the structure of the gate 1 and the dummy gate structure 160. The gate conductor 152 is disposed above end 154 of portion 106.1e and above the first surface 185 of substrate 105. The gate conductor 152 can cover the four sides of portion 106.1e (including end 154). The dummy gate structure 160 is disposed on the four sides of portion 103e (including end 144).

[0057] Although Figure 3 This is about the fin 101e specification, but specifically for... Figure 3 The provided description may describe fin 101a in the same or similar manner. Although Figure 3 This describes segments 1, 2, and 3 of the finFET 100 along line BB', but for... Figure 3 The provided description may describe segments 4 and 5 along line BB' in the same or similar manner, since the finFET 100 is symmetrical about plane DD'.

[0058] Figure 4 Describe the line CC' along the space between planes FF' and EE' (along the space between fins 101c and 101d). Figure 1A Examples of cross-sectional views of a finFET device depicted include segments 1, 2, and 3. Regarding... Figure 1A , 1B The descriptions provided for components with given reference numerals in sections 1, 2, and 3 are applicable to components having... Figure 4 Components that are shown with the same given reference figures, unless otherwise stated or provided.

[0059] refer to Figure 4The finFET device 100 includes a bottom substrate 134 and a top substrate 105A, which has dielectric materials 111, 118c, 110c, 119c, 112c, a well region 114, and a well region 115. Figure 4 Depicting along Figure 1A The space between fins 101c and 101d of line CC' in the diagram, and different from... Figure 2 and 3 The finFET device 100 does not contain any fins in this space.

[0060] Unlike Figure 2 and 3 The region between gate 1 and gate 1 does not have any fins. (Reference) Figure 1A and 4 Region 104.11c is located between the dummy gate structure 204 and the gate 1 structure, and between fins 101c and 101d. Region 104.11c is defined by the dummy gate structure 204 and the gate 1 structure, and by the source 104.1c and 104.1d. Region 104.11c is located at the first end between fins 102c and 102d in the first portion and is disposed on a portion of the well region 114 and on at least a portion of the dielectric material 118c, which is a trench or STI. Region 104.11c may be filled with dielectric material.

[0061] The region at gate 1 between fins 102c and 102d does not have any fins. (Reference) Figure 1A and 4 This region is defined by the channel portions 106.1c and 106.1d at the structure of the gate 1. This region is located at the structure of the gate 1 between the fin portions 102c and 102d in the first part and is disposed above a portion of the well region 114 and a portion of the well region 115.

[0062] The region between gate 1 and dummy gate 2 has no fins. (Reference) Figure 1A and 4 Region 108.11c is located between the structure of gate 1 and the dummy gate structure 2, and between fins 101c and 101d. Region 108.11c is defined by the structure of gate 1 and the dummy gate structure 2, and by fins 108.1c and 108.1d. Region 108.11c is located between fins 108.1c and 108.1d in the second portion and is disposed on a portion of the well region 115 and on at least a portion of the dielectric material 110c, which is a trench or STI. Region 108.11c may be filled with dielectric material.

[0063] The region between dummy gate 2 and dummy gate 3 has no fins. (Reference) Figure 1A and 4 Region 107.11c is located between dummy gates 2 and 3 and between fins 101c and 101d. Region 107.11c may be defined by dummy gate structures 160 and 214 and by drains 107c and 107d. Region 107.11c is located between fins 103c and 103d in the third portion and is disposed above a portion of the well region 115 and above at least a portion of dielectric material 119c, which is a trench or STI. Region 107.11c may be filled with dielectric material.

[0064] Although Figure 4 This is a description of the area between fins 101c and 101d, but specifically... Figure 4 The provided description can describe other spaces in the same or similar manner (e.g., the region between fins 101b and 101c). For Figure 4 The provided description may also describe the region between fins 101a and 101b and the region between fins 101d and 101e in the same or similar manner, except for: the region on the first side of fin portion 108.1b away from portion 108.1c (e.g., Figure 1A The region 2T above the fin 108.1b in the middle can be defined by the structure of the gate 1 and the dummy gate structure 2, and by the fin 108.1b and dielectric in the segment 2 between portions 106.1a and 103a, and the region on the second side of the fin 108.1d away from portion 108.1c (e.g., Figure 1A The region 2B below the fin 108.1d can be defined by the structure of the gate 1 and the dummy gate structure 2, and by the fin 108.1d and the dielectric in the segment 2 along line BB'. Although Figure 4 This describes segments 1, 2, and 3 of the finFET 100 along line CC', but for... Figure 5 The provided description may describe segments 4 and 5 along line CC' in the same or similar manner, since the finFET 100 is symmetrical about plane DD'.

[0065] Figure 5 This document describes a flowchart illustrating an example fabrication operation 500 for forming a FinFET device according to one or more embodiments. Operations 500 need not be performed in the order shown. It should be understood that the depicted order is illustrative of one or more example methods, and this technique is not intended to limit us to the specific order or hierarchy presented. For example, based on preferences and / or specifications (e.g., cost, available materials, performance specifications), a specific order or hierarchy of the blocks may be rearranged or adjusted, and some operations may be removed while others are added. Two or more of the operations may be performed simultaneously. In one or more embodiments, operation 500 can be used to form a device with respect to... Figure 1A , 1BThe finFET device 100 is described in sections 2, 3, and 4. Other finFET devices according to one or more embodiments may be formed by operation 500. Other processes according to one or more embodiments may be implemented to form the finFET device 100.

[0066] For the purpose of explanation, this article mainly refers to Figure 1A , 2 Sections 3 and 4 describe example operation 500. In operation 505, one or more fin structures (e.g., fins 101a to e) are formed on substrate 105. In one or more embodiments, the fin structures may be formed using spacer photolithography. In one or more embodiments, the fin structures are disposed in a semiconductor layer above the substrate, formed by etching the substrate, grown on the substrate, or otherwise formed. The fin spacing (e.g., the distance between the same points on two adjacent fins (e.g., fins 101b and 101c)) can be measured from a point on one fin to the same point on another fin. In one or more embodiments, the fin length (e.g., the length across segments 1, 2, and 3 for a single-gate finFET or for...) Figure 1A The lengths of segments 1, 2, 3, 4, and 5 in the dual-gate finFET can be tens of micrometers or less. Substrate 105 can be a bulk substrate or a silicon-on-insulator substrate. Top substrate 105A can be a bulk substrate or a silicon-on-insulator substrate. In another configuration, top substrate 105A can be an epitaxial growth substrate. In one or more embodiments, the fin dimensions (e.g., fin width, fin length) and the fin spacing between fin structures do not need to be the same between any two adjacent or non-adjacent fin structures. The fin length employed may depend on the desired channel length and / or number of fins. In one or more embodiments, the fin structures may be cut to form shorter fin structures. In one or more embodiments, a wider dielectric material (e.g., 110e, 110c) and a longer gate (e.g., gates 1 and 2) are used at higher voltages.

[0067] Substrate 105 may be or may contain semiconductor materials such as silicon, silicon germanium, and gallium arsenide. In one or more embodiments, one or more fin structures may be formed as part of an STI process. For example, the STI process may involve forming STI regions (e.g., materials 110c, 110e, 111, 112c, 112e, 118c, 119c, and other similar regions) in substrate 105. In one or more embodiments, the STI process for forming materials 110c and 110e and other similar materials may form separation regions 308 (in section 2) between portions 102a, 102e and portions 103a, 103e, respectively. Other similar materials mentioned in the preceding sentence may include, for example: (i) a top substrate 105A formed below the separation region between portions 106.1a and 103a (in section 2). Figure 1A(ii) a dielectric material formed in the top substrate 105A (in region 2T) adjacent to but not adjacent to the partition region of portion 108.1b but not adjacent to portion 108.1c; (iii) a dielectric material formed in the top substrate 105A below portion 108.1b; and (iv) a dielectric material formed in the top substrate 105A (in region 2B) adjacent to but not adjacent to the partition region of portion 108.1d but not adjacent to portion 108.1c. In one or more embodiments, the partition region 308 may be 80 to 110 nm wide. The fin height may be about 40 to 50 nm, and the STI depth of materials 111 and materials 112c and 112e may be about 60 to 100 nm. Materials 118c and 119c may be about 60 to 100 nm deep. The finFET device 100 may be surrounded by material 111, and material 111 may be disposed between fins 101a to e. In one or more embodiments, materials 110c and 110e may be approximately 200 nm deep. Other dimensions are possible.

[0068] In operation 510, well regions (e.g., well region 114 and well region 115) are patterned and formed. Well regions 114 and 115 can be formed by applying dopant (e.g., via ion implantation) to substrate 105. The dopant type and doping concentration of well regions 114 and 115 can be tuned to meet the specifications (e.g., cost, performance, etc.) of the resulting finFET device (e.g., finFET device 100) and can be formed by ion implantation or using doped epitaxial material. In one or more embodiments, well regions 114 and 115 can be tuned to meet thermal voltage requirements.

[0069] In operation 515, a dummy gate material is patterned and deposited onto substrate 105 (e.g., surface 185 of substrate 105), comprising a fin structure (e.g., fins 101a to e). The dummy gate material may comprise polysilicon. The gate material may be used to form the metallic structure of the gate 1 of fins 101a to e. The gate 1 may span or surround multiple fins (or fin portions). In one or more embodiments, spacers, such as spacers 208, 182, 162, and 218, are provided after the dummy gate material has been deposited and etched back.

[0070] In operation 520, source 104.1a to e and 104.2a to e, and drain 107a to e are doped by photolithography performed on the open regions of the fin structure (e.g., the open regions corresponding to fins 102a to e and 109a to e of 104.1a to e and 104.2a to e). Epitaxial regions 133 and 139 (including 143 and 149) are formed in the open regions, wherein dopants are incorporated into the grown epitaxial material. The epitaxial material may be silicon or silicon-germanium, wherein dopants are incorporated into the silicon or silicon-germanium. In one or more embodiments, ion implantation may be performed to increase the doping concentration of epitaxial regions 133 and 139 (including 143 and 149). In one or more embodiments, epitaxial regions 133 and 139 (including 143 and 149) may be formed by epitaxial growth, drive-in annealing, and / or ion implantation. The height (e.g., vertical direction) of epitaxial regions 133 and 139 (including 143 and 149) can be tuned based on, for example, the doping concentration in epitaxy and ion implantation. The length of epitaxial regions 133 and 139 (including 143 and 149) can be controlled by photolithography.

[0071] In one or more embodiments, in operation 525, the dummy gate material is removed and replaced. Gates 1 and 2 may span or surround corresponding plurality of fins. In one or more embodiments, gates 1 and 2 may be formed by removing the dummy material and depositing one or more dielectric materials and one or more conductive materials. For example, an oxide material of silicon dioxide may be present under one or more conductive structures and form portions of the gate. In one or more embodiments, the oxide material is deposited prior to the deposition of the gate material and may be a dielectric having a high dielectric constant (K).

[0072] Gate 1 may include spacer 182, which may be formed during the formation of spacers 208, 162, and 218 (e.g., in operation 515). Gate 1 includes gate conductor 152, which is asymmetrical about gate conductor 152 for a shallower drain. In one or more embodiments, gate 1 may include two fingers (gate conductor 152 and another conductor not shown). Gate 2 may have the same or similar structure as gate 1.

[0073] In one or more embodiments, one or more layers of dielectric material may be deposited (e.g., in operation 530) over surface 185 of a substrate having trenches (e.g., 111, 110c, 110e, 112c, 112e, 118c and 119c), and the formation of gates 1 and 2 may occur after the vias and contacts are formed (e.g., in operation 535).

[0074] In one or more embodiments, the finFET device may be a dual-gate finFET device comprising a superjunction LDMOS structure with multiple alternating regions of n-type and p-type doped semiconductors. The alternating regions can facilitate depletion of one region at a relatively low voltage and can result in a high breakdown voltage. One or more drift regions (e.g., the n-type channel or n-type portion of a fin structure) can be depleted by one or more adjacent p-type regions (e.g., the p-type well or p-type portion of a fin structure). The breakdown voltage can be increased by this depletion. In one or more embodiments, this technology allows for operation at higher voltages and can result in a smaller device with lower on-resistance.

[0075] Figure 6 This illustrates a block diagram of an example integrated circuit. In one or more embodiments, integrated circuit 600 may include multiple devices. Such devices may include, for example, power amplifiers and / or radio frequency (RF) circuitry. Each of such devices may include one or more FinFETs 100. The integrated circuit may be a packaged IC, which is sometimes referred to as a packaged IC chip.

[0076] Figure 7 This section illustrates the current and voltage characteristics of an example finFET device. The horizontal axis represents the gate-to-source voltage (Vgs) in volts, and the vertical axis represents the drain current (Id) per fin in amperes.

[0077] Curve 710 illustrates the example Id / Vgs characteristics of a FinFET device, where the total number of fins in each of the second and fourth portions (see, for example, segments 2 and 4) is the same as the total number of fins in each of the first, third, and fifth portions (see, for example, segments 1, 3, and 5). In this case, the total number of fins in the drift regions (e.g., each of drift regions 1 and 2) is the same as the total number of fins in each of the first, third, and fifth portions.

[0078] Curve 720 illustrates the example Id / Vgs characteristics of a FinFET device, where the total number of fins in each of the second and fourth portions (see, for example, segments 2 and 4) is less than the total number of fins in each of the first, third, and fifth portions (see, for example, segments 1, 3, and 5). In this case, the total number of fins in the drift regions (e.g., each of drift regions 1 and 2) is less than the total number of fins in each of the first, third, and fifth portions.

[0079] While the device of curve 710 may have a lower Ron than the device of curve 720 (due to the presence of more fins in the drift region), the device of curve 710 has a higher breakdown voltage than the device of curve 720. For the device of curve 710, by including fins in the drift region, Ron is reduced, but the breakdown voltage is lower than the desired level. For the device of curve 720, by including fewer fins in the drift region, Ron is reduced in the device without any fins in the drift region, and simultaneously, the breakdown voltage increases to the desired level.

[0080] Figure 8 This is a plan view illustrating another example of a finFET device. The finFET device 800 has a fin structure including left fins 802a, 802b, 802c, and 802d and right fins 809a, 809b, 809c, and 809d. A source 810 is located in the left fins 802a, 802b, 802c, and 802d. A gate 820 is located above the left fins 802a, 802b, 802c, and 802d. A drain 840 is located in the right fins 809a, 809b, 809c, and 809d. The left fins 802a, 802b, 802c, and 802d are separated from the right fins 809a, 809b, 809c, and 809d by a gap 830. The finFET device 800 does not have any fins within the gap 830.

[0081] Figure 1A , 1B The finFET device 100 shown in Figures 2, 3, and 4 has improved Ron and breakdown voltage compared to the finFET device 800. In one or more aspects, the finFET device 100 has a lower Ron and a higher breakdown voltage than the finFET device 800 because, in the finFET device 100, its drift region (or each of the second and fourth portions) includes fins, wherein the total number of fins in the drift region (or each of the second and fourth portions) is less than the total number of fins in each of the first, third, and fifth portions. By including fins in the drift region, the Ron of the finFET device 100 is reduced compared to the finFET device 800, and by having fewer fins in the drift region, the breakdown voltage of the finFET device 100 is increased. Furthermore, the finFET device 100 can be manufactured without the need for additional mask fabrication and additional processing steps compared to the finFET device 800.

[0082] It should be noted that the dimensional aspects provided above (e.g., gate width, thickness, fin height, fin length, region size) are examples, and other values ​​of the dimensions may be used depending on one or more embodiments. Furthermore, the dimensional aspects provided above are typically nominal values. As those skilled in the art will understand, each dimensional aspect (e.g., oxide thickness) has tolerances associated with that dimensional aspect. For example, in terms of oxide thickness, the tolerance may vary depending on the process used to deposit or grow the oxide. In one or more examples, the dielectric material may be silicon dioxide, silicon nitride, or other dielectric materials.

[0083] Return to reference Figure 1A In one or more embodiments, segment 1 is adjacent to segment 2, segment 2 is adjacent to segment 3, segment 3 is adjacent to segment 4, and segment 4 is adjacent to segment 5. In one or more instances, the fin structure (e.g., including fins 101a to e) includes a first portion (in or across segment 1), the first portion being adjacent to a second portion (in or across segment 2), the second portion being adjacent to a third portion (in or across segment 3), the third portion being adjacent to a fourth portion (in or across segment 4), and the fourth portion being adjacent to a fifth portion (in or across segment 5). In one or more instances, with respect to fin 101a, fin portion 102a is separated from fin portion 103a (through at least one separating region in segment 2), and fin portion 103a is separated from fin portion 109a (through at least one separating region in segment 4). Similarly, for fin 101e, fin portion 102e is separated from fin portion 103e (through at least one separating region in segment 2), and fin portion 103e is separated from fin portion 109e (through at least one separating region in segment 4). For fin 101b, fin portion 102b is adjacent to fin portion 108.1b, fin portion 108.1b is adjacent to fin portion 103b, fin portion 103b is adjacent to fin portion 108.2b, and fin portion 108.2b is adjacent to fin portion 109b. Similarly, for fin 101c, fin portion 102c is adjacent to fin portion 108.1c, fin portion 108.1c is adjacent to fin portion 103c, fin portion 103c is adjacent to fin portion 108.2c, and fin portion 108.2c is adjacent to fin portion 109c. Similarly, for fin 101d, fin portion 102d is adjacent to fin portion 108.1d, fin portion 108.1d is adjacent to fin portion 103d, fin portion 103d is adjacent to fin portion 108.2d, and fin portion 108.2d is adjacent to fin portion 109d. The term "adjacent" can mean adjacent to, touching, directly contacting, continuous with, or similar to.

[0084] In one or more examples, for fin 101a, the left end of fin portion 102a is adjacent to fin portion (or source electrode) 104.1a, fin portion 104.1a is adjacent to fin portion (or channel portion) 106.1a, fin portion 106.1a is separated from the left end of fin portion 103a (through at least one separating region in segment 2), fin portion 103a is adjacent to fin portion (or drain electrode) 107a, fin portion 107a is adjacent to the right end of fin portion 103a, fin portion 103a is separated from fin portion (or channel portion) 106.2a (through at least one separating region in segment 4), fin portion 106.2a is adjacent to fin portion (or source electrode) 104.2a, and fin portion 104.2a is adjacent to the right end of fin portion 109a. Fin 101e has adjacent and separated portions similar to those of fin 101a. Regarding fin 101b, the left end of fin portion 102b is adjacent to fin portion (or source pole) 104.1b, fin portion 104.1b is adjacent to fin portion (or channel portion) 106.1b, fin portion 106.1b is adjacent to fin portion 108.1b, fin portion 108.1b is adjacent to fin portion 103b, fin portion 103b is adjacent to fin portion 106.2b, fin portion 106.2b is adjacent to fin portion (or source pole) 104.2b, and fin portion 104.2b is adjacent to the right end of fin portion 109b. Fins 101c and 101d have adjacent portions similar to those of fin 101b.

[0085] In one or more embodiments of the manufacturing process, each of fins 101b to d is manufactured as a single piece, and each of fins 101a and 101e is manufactured as three pieces. Adjacent portions (excluding source / drain fins 104.1a to e, 107a to e, and 104.2a to e) may be manufactured as a single piece. In one or more instances, fins 101a to e are manufactured simultaneously. In the description provided in this paragraph, (i) source / drain fins 104.1a to e, 107a to e, and 104.2a to e may be formed after fins 101a to e are formed, and (ii) source / drain fins 104.1a to e, 107a to e, and 104.2a to e may be formed simultaneously.

[0086] For convenience, various examples of aspects of this disclosure are described below. These are provided as examples and do not limit the technology. Some of the examples described below are illustrated with reference to the figures disclosed herein, for illustrative purposes only and without limiting the scope of the technology.

[0087] One or more embodiments provide a fin-based field-effect transistor (finFET) device (e.g., 100) comprising: a fin structure (e.g., 101a to e) having a first portion (e.g., in or across segment 1), a second portion (e.g., in or across segment 2), and a third portion (e.g., in or across segment 3); a first gate structure (e.g., gate 1) disposed over at least a portion of the first portion; and a first source / drain region (e.g., source 1, 104.1a to e) disposed on... The first portion and the second source / drain region (e.g., drain 1, 107a to e) are disposed in the third portion, wherein: each of the first, second, and third portions includes one or more fins (see, for example, one or more of 102a to e, 108.1b to d, 103a to e); and the total number of fins in the second portion (e.g., 108.1b, 108.1c, 108.1d) is less than the total number of fins in the first portion (e.g., 102a, 102b, 102c, 102d, 102e). The second portion may include a drift region. The second portion does not include the first gate structure, the first source / drain region, or the second drain / source region.

[0088] One or more instances provide: the first fin in the first part (e.g., Figure 2 102c) in the first part is connected to the first fin in the third part (e.g., 103c) via the first fin in the second part (e.g., 108.1c); the second fin in the first part (e.g., Figure 3 102e) is separated from the second fin (e.g., 103e) in the third part by at least one dividing region (e.g., 308) in the second part; the first fin (e.g., 108.1c) in the second part is above the first part of the first well region (e.g., 115) and not above the trench (e.g., 111, 110c, 112c); and the dividing region (e.g., 308) in the second part is above the second part of the first well region (e.g., 115) and above at least a part of the second trench (e.g., 110e).

[0089] One or more instances provide: the third fin in the first part (e.g., Figure 1A 102d in the first part is connected to the third fin in the third part (e.g., 103d) via the third fin in the second part (e.g., 108.1d); the first region at the first end between the first and third fins in the first part (e.g., along...) Figure 1A The left-hand region between 102c and 102d of CC'; for example, Figure 4 104.11c in the second well region (e.g., Figure 4 Above the first part of 114) and in the third trench (e.g., Figure 4Above at least a portion of 118c); the first gate structure (e.g., between the first and third fins in the first portion (e.g., between 102c and 102d) Figure 4 The second region at the gate 1) in the second well region (e.g., Figure 4 Above the second part of 114) and in the first well region (e.g., Figure 4 Above the third part of 115); the third region between the first and third fins in the second part (e.g., Figure 4 108.11c) is above the fourth portion of the first well region (e.g., 115) and at least a portion of the fourth trench (e.g., 110c); and the fourth region (e.g., between the first and third fins in the third portion) is above the fourth portion of the first well region (e.g., 115). Figure 4 107.11c) above the fifth portion of the first well region (e.g., 115) and in the fifth trench (e.g., Figure 4 At least part of 119c).

[0090] One or more instances provide that: at least a portion of the first part (e.g., the portion of the first part containing 102b to d) is adjacent to the second part; the second part is adjacent to at least a portion of the third part (e.g., the portion of the third part containing 103b to d); and the first part (e.g., across segment 1) is located on a first side of the second part (e.g., across segment 2), and the third part (e.g., across segment 3) is located on a second side of the second part opposite to the first side of the second part.

[0091] One or more examples are provided: a first portion includes two or more fins (e.g., 102a to e); a third portion includes two or more fins (e.g., 103a to e) corresponding to the two or more fins of the first portion; all fins in the first, second, and third portions are parallel to each other; at least one of the two or more fins (e.g., 102a, 102e) of the first portion is separated from at least one of the two or more fins (e.g., 103a, 103e) of the third portion; and at least another of the two or more fins (e.g., 102b, 102c, 102d) of the first portion is connected to at least one of the two or more fins (e.g., 108.1b, 108.1c, 108.1d) of the second portion via at least one of the two or more fins (e.g., 103b, 103c, 103d) of the third portion.

[0092] One or more instances provide that at least one of two or more fins (e.g., 102a, 102e) in the first part and at least one corresponding to two or more fins (e.g., 103a, 103e) in the third part are separated from each other by at least one dividing region (e.g., 308) in the second part.

[0093] One or more instances provide: the second part includes the first outer parts that are parallel to each other (e.g., Figure 1A 2T in the middle part (e.g., Figure 1A 2M in the middle) and the second outer part (e.g., Figure 1A 2B); the first and second outer portions and the middle portion of the second part are located between the first part (e.g., across segment 1) and the third part (e.g., across segment 3); the first outer portion of the second part is located on the first side of the middle portion of the second part, and the second outer portion of the second part is located on the second side of the middle portion opposite to the first side of the middle portion of the second part; the middle portion of the second part (e.g., 2M) includes one or more fins (e.g., 108.1b, 108.1c, 108.1d); and the first and second outer portions of the second part (e.g., 2T and 2B) do not contain fins.

[0094] One or more instances provide that one or more fins (e.g., 108.1b, 108.1c, 108.1d) of the middle portion of the second portion are connected to one or more corresponding fins (e.g., 102b, 102c, 102d) of the first portion and to one or more corresponding fins (e.g., 103b, 103c, 103d) of the third portion.

[0095] One or more examples are provided: each of the first and third parts includes a first outer portion (e.g., 1T, 3T), a middle portion (e.g., 1M, 3M), and a second outer portion (e.g., 1B, 3B) that are parallel to each other; the first and second outer portions (e.g., 2T, 2B) of the second part are respectively positioned between the first and second outer portions (e.g., 1T, 1B) of the first part and the first and second outer portions (e.g., 3T, 3B) of the third part; the first outer portion (e.g., 1T) of the first part is located on a first side of the middle portion (e.g., 1M) of the first part, and the second outer portion (e.g., 1B) of the first part is located on a second side of the middle portion (e.g., 1M) of the first part, opposite to the first side of the first part; the first outer portion (e.g., 3T) of the third part is located on the middle portion (e.g., 3M) of the third part. The first side of the third part is located at the first side of the third part, and the second outer part of the third part (e.g., 3B) is located at the second side of the middle part of the third part opposite to the first side of the third part; one or more fins of the middle part of the second part (e.g., 108.1b, 108.1c, 108.1d) are connected to one or more corresponding fins of the middle part of the first part (e.g., 102b, 102c, 102d) and connected to one or more corresponding fins of the middle part of the third part (e.g., 103b, 103c, 103d); and some fins of the first and second outer parts of the first part (e.g., 102a, 102e) and some fins of the corresponding first and second outer parts of the third part (e.g., 103a, 103e) are separated by at least the corresponding first and second outer parts of the second part (e.g., 2T, 2B).

[0096] One or more examples provide that: the fin structure (e.g., 101a to e) further includes a fourth portion (e.g., in or across segment 4) and a fifth portion (e.g., in or across segment 5); the finFET device further includes: a second gate structure (e.g., gate 2) disposed over at least a portion of the fifth portion; and a third source / drain region (e.g., source 2, 104.2a to e) disposed in the fifth portion; and the total number of fins (e.g., 108.2b, 108.2c, 108.2d) in the fourth portion is less than the total number of fins (e.g., 109a, 109b, 109c, 109d, 109e) in the fifth portion.

[0097] One or more examples provide that: the total number of fins in the second part (e.g., 108.1b, 108.1c, 108.1d) is 1 or greater than 1; the total number of fins in the second part is the same as the total number of fins in the fourth part (e.g., 108.2b, 108.2c, 108.2d); the total number of fins in the first part (e.g., 102a, 102b, 102c, 102d, 102e) is the same as the total number of fins in the third part (e.g., 103a, 103b, 103c, 103d, 103e); and the total number of fins in the first part is the same as the total number of fins in the fifth part (e.g., 109a, 109b, 109c, 109d, 109e).

[0098] One or more examples provide an integrated circuit (e.g., 600) having a plurality of devices, each of which includes a finFET device (e.g., 100).

[0099] One or more embodiments provide a fin-based field-effect transistor (finFET) device (e.g., 100) comprising: a fin structure (e.g., 101a to e) having a first portion (e.g., in or across segment 1), a second portion (e.g., in or across segment 2), and a third portion (e.g., in or across segment 3); a first gate structure (e.g., gate 1) disposed over at least a portion of the first portion; a first source / drain region (e.g., source 1, 104.1a to e) disposed in the first portion; and a second drain / source region (e.g., drain 1, 107a to e). It is disposed in the third part, wherein: each of the first, second and third parts includes one or more fins; the first fins in the first part (e.g. 102b, 102c, 102d) are connected to the first fins in the third part (e.g. 103b, 103c, 103d) via the first fins in the second part (e.g. 108.1b, 108.1c, 108.1d); and the second fins in the first part (e.g. 102a, 102e) are separated from the second fins in the third part (e.g. 103a, 103e) by at least one dividing region (e.g. 308) in the second part.

[0100] One or more examples provide that: the first fin in the second portion (e.g., 108.1c) is above the substrate (e.g., 105) and not above the trench (e.g., 111); and the partition region in the second portion (e.g., 308) is above the substrate and at least a portion of the second trench (e.g., 110e).

[0101] One or more examples provide: a third fin in a first portion is connected to a third fin in a third portion via a third fin in a second portion; a first region between the first and third fins in the first portion is above the substrate and above at least a portion of a third trench; a second region between the first and third fins in the first portion is above the substrate and above at least another portion of a third trench and above at least a portion of a fourth trench; a third region between the first and third fins in the second portion is above the substrate and above at least another portion of a fourth trench; and a fourth region between the first and third fins in the third portion is above the substrate and above at least a portion of a fifth trench.

[0102] One or more examples provide that: the second part includes a first outer part, a middle part, and a second outer part that are parallel to each other; the first and second outer parts and the middle part of the second part are positioned between the first part and the third part; the first outer part of the second part is located on a first side of the middle part of the second part, and the second outer part of the second part is located on a second side of the middle part opposite to the first side of the middle part of the second part; the middle part of the second part includes one or more fins; and the first and second outer parts of the second part do not contain fins.

[0103] One or more examples are provided: each of the first and third portions includes a first outer portion, a middle portion, and a second outer portion that are parallel to each other; the first and second outer portions of the second portion are respectively positioned between the first and second outer portions of the first portion and the first and second outer portions of the third portion; the first outer portion of the first portion is located on a first side of the middle portion of the first portion, and the second outer portion of the first portion is located on a second side of the middle portion of the first portion opposite to the first side of the first portion; the first outer portion of the third portion is located on a first side of the middle portion of the third portion, and the second outer portion of the third portion is located on a second side of the middle portion of the third portion opposite to the first side of the third portion; one or more fins of the middle portion of the second portion are connected to corresponding one or more fins of the middle portion of the first portion and connected to corresponding one or more fins of the middle portion of the third portion; and the fins of the first and second outer portions of the first portion and the fins of the corresponding first and second outer portions of the third portion are separated by at least the corresponding first and second outer portions of the second portion.

[0104] One or more embodiments provide a method of manufacturing a fin-based field-effect transistor (finFET) device (e.g., 100), wherein the method includes: providing a fin structure (e.g., 101a to e) comprising a first portion, a second portion, and a third portion; providing a first source / drain region (e.g., source 1) in the first portion; providing a second drain / source region (e.g., drain 1) in the third portion; and providing a first gate structure (e.g., gate 1) over at least a portion of the first portion, wherein: each of the first, second, and third portions includes one or more fins; and the total number of fins in the second portion (e.g., 108.1b, 108.1c, 108.1d) is less than the total number of fins in the first portion (e.g., 102a, 102b, 102c, 102d, 102e).

[0105] One or more examples provide that the method further comprises: providing a first well region (e.g., 115) formed in a substrate and doped with a first type of dopant, wherein: a first fin in a first portion is connected to a first fin in a third portion via a first fin in a second portion; a second fin in the first portion is separated from a second fin in the third portion by at least one separating region in the second portion; the first fin in the second portion is above a first portion of the first well region and not above a trench; and the separating region in the second portion is above a second portion of the first well region and above at least a portion of the second trench.

[0106] One or more examples provide that the method further includes: providing a second well region (e.g., 114) formed in a substrate and doped with a second type of dopant, wherein: a third fin in a first portion is connected to a third fin in a third portion via a third fin in a second portion; a first region at a first end between the first and third fins in the first portion is over a first portion of the second well region and over at least a portion of a third trench; a second region at a first gate structure between the first and third fins in the first portion is over a second portion of the second well region and over a third portion of the first well region; a third region between the first and third fins in the second portion is over a fourth portion of the first well region and over at least a portion of a fourth trench; and a fourth region between the first and third fins in the third portion is over a fifth portion of the first well region and over at least a portion of a fifth trench.

[0107] In one or more instances, the term "gate" may refer to the insulated gate terminal of a FET. The physical structure of the gate terminal may be referred to as the gate electrode. In one or more instances, the terms "source" and "drain" may refer to the source and drain terminals of a FET, where conduction occurs between the source and drain terminals under the influence of an electric field caused by a voltage applied to the gate terminal of the FET after the semiconductor surface is reversed. Designers may designate a terminal as "source" or "drain" based on the voltage applied to a particular source / drain terminal when the FET is operating in a circuit.

[0108] In one or more instances, both the terms "contact" and "path" can refer to a structure in a chip used for electrical connections between conductors, such as for different interconnect layers of the chip. These terms can describe both an opening in the insulator that completes the structure and the completed structure itself.

[0109] In one or more instances, the terms "substrate" and "substrate material" can refer to a physical object that serves as the basis for transforming into a desired microelectronic configuration through various process operations. A typical substrate used in the fabrication of integrated circuits is a wafer. Wafers can be made from semi-conductive (e.g., bulk silicon), non-semi-conductive (e.g., glass), or a combination of semi-conductive and non-semi-conductive materials (e.g., silicon-on-insulator (SOI)). In the semiconductor industry, bulk silicon wafers are commonly used in the fabrication of integrated circuits.

[0110] In the semiconductor industry environment of foundries and fabless companies, foundries develop, specify, and provide designers with the physical structures they use to implement their designs. Foundries provide manufacturing services to many fabless semiconductor companies, but in order to operate profitably, they optimize manufacturing processes to achieve high yields. Such optimizations often require limiting the variety of structures that can be produced through a specific manufacturing process. Consistent with the foregoing, foundries typically offer a limited set of transistor structures that they hope to cover a wide range of circuit applications.

[0111] The terms “configured” and “operable” do not imply any specific tangible or intangible modification of the subject, but rather are intended to be used interchangeably. For example, the terms “top,” “middle,” “bottom,” “front,” “back,” “side,” “horizontal,” “vertical,” and the like refer to any frame of reference, not a typical gravitational frame of reference. Therefore, these terms can extend upwards, downwards, diagonally, or horizontally within a gravitational frame of reference. The terms “above,” “above,” “below,” “under,” and the like refer to any frame of reference, not a typical gravitational frame of reference, and these terms can refer directly or indirectly to “above,” “above,” “below,” “under,” and the like. The terms “coupled,” “connected,” and the like can refer directly or indirectly to “coupled,” “connected,” and the like. The terms “row,” “column,” and the like refer to any frame of reference, and they can refer to horizontal or vertical rows or columns.

[0112] Unless explicitly stated otherwise, references to a singular element are not intended to mean "one and only one," but rather "one or more." For example, a "one" module may refer to one or more modules. Without further constraints, elements preceded by "a / an" or "the / said" exclude the presence of additional identical elements. Unless otherwise explicitly stated, the term "some" refers to one or more. Furthermore, while this disclosure may provide numerous example ranges and values, these are non-limiting examples, and other ranges and values ​​are within the scope of this art.

[0113] Titles and subtitles (if any) are used for convenience only and do not limit the invention. The word "exemplary" is used to mean as an example or illustration. Any embodiment described herein as an "example" is not necessarily to be construed as being more preferred or superior to other embodiments. To the extent that the terms "comprising," "having," or the like are used, this term is intended to be inclusive in a manner similar to the term "including," as "including" is interpreted when used as a transitional word in a claim. For example, relational terms such as first and second and the like may be used only for ease of understanding and do not necessarily require or imply any actual relationship or order between elements or actions, nor do they necessarily require or imply that they have different characteristics, unless otherwise stated.

[0114] Phrases such as "one aspect," "the other aspect," "some aspects," "one or more aspects," "one implementation," "the other implementation," "some implementations," "one or more implementations," "one embodiment," "the other embodiment," "some embodiments," "one or more embodiments," "one configuration," "the other configuration," "some configurations," "one or more configurations," "the present disclosure," "the disclosure," "other variations thereof," and the like are for convenience and do not imply that the disclosure relating to such phrases is necessary to the present technology or that the disclosure applies to all configurations of the present technology. The disclosure relating to such phrases may apply to all configurations or one or more configurations. The disclosure relating to such phrases may provide one or more instances. For example, a phrase referring to one or more aspects may refer to one or more aspects, and vice versa, and this similarly applies to other foregoing phrases.

[0115] The phrase “at least one of…” preceding a series of items (where the terms “and” or “or” separate any of the items) modifies the entire list, not each member of the list. The phrase “at least one of…” does not require selection of at least one item; rather, the phrase allows for the meaning of at least one of any of the items and / or at least one of any combination of items and / or at least one of each of the items. By example, each of the phrases “at least one of A, B, and C” or “at least one of A, B, or C” refers to only A, only B, or only C; any combination of A, B, and C; and / or at least one of each of A, B, and C.

[0116] It should be understood that the specific order or hierarchy of the disclosed steps, operations, or processes is illustrative of the method. Unless otherwise expressly stated, it should be understood that the specific order or hierarchy of steps, operations, or processes may be performed in a different order. Some of the steps, operations, or processes may be performed simultaneously. The appended method claims (if any) claim the current elements of the respective steps, operations, or processes in a sample order and are not intended to be limited to the specific order or hierarchy presented. These may be performed sequentially, linearly, in parallel, or in a different order.

[0117] This disclosure is provided to enable any person skilled in the art to practice the various aspects described herein. In some instances, structures and components are shown in block diagram form to avoid obscuring the concepts of the art. This disclosure provides various examples of the art, and the art is not limited to these examples. Various modifications to these aspects will be readily apparent to those skilled in the art, and the principles described herein can be applied to other aspects.

[0118] All structural and functional equivalents of elements throughout the various aspects described herein, known or to be known later by one of ordinary skill in the art, are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, the disclosure herein is not intended to be made public, whether or not it is expressly stated in the claims. Unless an element is expressly referred to using the phrase “component for…”, or, in the case of a method claim, the element is referred to using the phrase “step for…”, no claim element shall be construed in accordance with paragraph 6 of 35 U.S.SC § 112.

[0119] The title, background, brief description of the figures, abstract, and figures are hereby incorporated into this disclosure and provided as illustrative examples of this disclosure, not as limiting descriptions. It is intended to be understood that they are not intended to limit the scope or meaning of the claims. Furthermore, in the detailed description, it is evident that for the purpose of simplifying this disclosure, illustrative examples are provided, and in various embodiments, features are grouped together. The method of this disclosure should not be interpreted as reflecting an intention to require more features than expressly cited in each claim. In fact, the claims reflect that the inventive subject matter consists of fewer than all features disclosed in a single configuration or operation. The claims are hereby incorporated into the detailed description, wherein each claim is independently and separately claimed as a subject matter. The claims are not intended to be limited to the aspects described herein, but rather to conform to the full scope consistent with the language of the claims and to cover all legal equivalents. Nevertheless, none of the claims are intended to cover subject matter that fails to meet the requirements of applicable patent law, nor should they be interpreted in this manner.

Claims

1. A fin-based field effect transistor (finFET) device comprising: a fin structure comprising a first portion, a second portion, a third portion, a fourth portion, and a fifth portion; a first gate structure disposed over at least part of the first portion and a second gate structure disposed over at least part of the fifth portion; a first source / drain region disposed in the first portion; a second drain / source region disposed in the third portion; and a third source / drain region disposed in the fifth portion; wherein: each of the first, third, and fifth portions comprises a plurality of fins; the first gate structure is disposed over the plurality of fins in the first portion; and a total number of fins in the second portion is less than a total number of fins in the first portion and a total number of fins in the fourth portion is less than a total number of fins in the fifth portion.

2. A fin-based field effect transistor (finFET) device comprising: a fin structure comprising a first portion, a second portion, a third portion, a fourth portion, and a fifth portion; a first gate structure disposed over at least part of the first portion and a second gate structure disposed over at least part of the fifth portion; a first source / drain region disposed in the first portion; a second drain / source region disposed in the third portion; and a third source / drain region disposed in the fifth portion; wherein: each of the first, third, and fifth portions comprises a plurality of fins; a total number of fins in the second portion is less than a total number of fins in the first portion and a total number of fins in the fourth portion is less than a total number of fins in the fifth portion a first fin in the first portion is connected to a first fin in the third portion via a first fin in the second portion; a second fin in the first portion is separated from a second fin in the third portion by at least one separation region in the second portion; the first fin in the second portion is over a first portion of a first well region and not over a trench formed in a substrate; and the separation region in the second portion is over a second portion of the first well region and over at least part of a second trench formed in the substrate.

3. The finFET device of claim 2, wherein: a third fin in the first portion is connected to a third fin in the third portion via a third fin in the second portion; a first region at a first end between the first and third fins in the first portion is over a first portion of a second well region and over at least part of a third trench; a second region at the first gate structure between the first and third fins in the first portion is over a second portion of the second well region and over a third portion of the first well region; a third region between the first and third fins in the second portion is over a fourth portion of the first well region and over at least part of a fourth trench; and ​ A fourth region between the first and third fins in the third portion is over a fifth portion of the first well region and over at least a portion of a fifth trench.

4. The finFET device of claim 1, wherein: at least a portion of the first portion is adjacent to the second portion; the second portion is adjacent to at least a portion of the third portion; and the first portion is at a first side of the second portion and the third portion is at a second side of the second portion opposite the first side of the second portion.

5. The finFET device of claim 1, wherein: the first portion includes two or more fins; the third portion includes two or more fins corresponding to the two or more fins of the first portion; all fins in the first, second, and third portions are parallel to each other; at least one of the two or more fins of the first portion is separated from at least a corresponding one of the two or more fins of the third portion; and at least another one of the two or more fins of the first portion is connected to at least a corresponding another one of the two or more fins of the third portion via at least one of the one or more fins of the second portion.

6. The finFET device of claim 5, wherein the at least one of the two or more fins of the first portion and the at least a corresponding one of the two or more fins of the third portion are separated from each other by at least one separation region in the second portion.

7. The finFET device of claim 1, wherein: the second portion includes a first outer portion, a middle portion, and a second outer portion parallel to each other; the first and second outer portions of the second portion and the middle portion are positioned between the first portion and the third portion; the first outer portion of the second portion is at a first side of the middle portion of the second portion and the second outer portion of the second portion is at a second side of the middle portion of the second portion opposite the first side of the middle portion of the second portion; the middle portion of the second portion includes one or some fins; and the first and second outer portions of the second portion are free of fins.

8. The finFET device of claim 7, wherein the one or some fins of the middle portion of the second portion are connected to corresponding one or some fins of the first portion and to corresponding one or some fins of the third portion.

9. The finFET device of claim 7, wherein: each of the first and third portions includes a first outer portion, a middle portion, and a second outer portion parallel to each other; the first and second outer portions of the second portion are respectively positioned between the first and second outer portions of the first portion and the first and second outer portions of the third portion; the first outer portion of the first portion is at a first side of the middle portion of the first portion, and the second outer portion of the first portion is at a second side of the middle portion of the first portion opposite the first side of the first portion; the first outer portion of the third portion is at a first side of the middle portion of the third portion, and the second outer portion of the third portion is at a second side of the middle portion of the third portion opposite the first side of the third portion; the one or some fins of the middle portion of the second portion are connected to corresponding one or some fins of the middle portion of the first portion and to corresponding one or some fins of the middle portion of the third portion; and some fins of the first and second outer portions of the first portion are separated from some fins of the corresponding first and second outer portions of the third portion by at least the corresponding first and second outer portions of the second portion.

10. The finFET device of claim 1, wherein: the total number of fins in the second portion is one or greater than one; the total number of fins in the second portion is the same as the total number of fins in the fourth portion; the total number of fins in the first portion is the same as the total number of fins in the third portion; and the total number of fins in the first portion is the same as the total number of fins in the fifth portion.

11. An integrated circuit comprising a plurality of devices, wherein each of the plurality of devices comprises the finFET device of claim 1 or 2.

12. A fin-based field effect transistor (finFET) device comprising: a fin structure comprising a first portion, a second portion, and a third portion, a fourth portion, and a fifth portion; a first gate structure disposed over at least a portion of the first portion and a second gate structure disposed over at least a portion of the fifth portion; a first source / drain region disposed in the first portion; a second drain / source region disposed in the third portion; and a third source / drain region disposed in the fifth portion; wherein: each of the first, third, and fifth portions comprises a plurality of fins; the first gate structure is disposed over the plurality of fins in the first portion; a total number of fins in the fourth portion is less than a total number of fins in the fifth portion; a first fin in the first portion is connected to a first fin in the third portion via a first fin in the second portion; and a second fin in the first portion is separated from a second fin in the third portion by at least one separation region in the second portion.

13. A fin-based field effect transistor (finFET) device comprising: a fin structure comprising a first portion, a second portion, a third portion, a fourth portion, and a fifth portion; a first gate structure disposed over at least a portion of the first portion and a second gate structure disposed over at least a portion of the fifth portion; a first source / drain region disposed in the first portion; a second drain / source region disposed in the third portion; and a third source / drain region disposed in the fifth portion; wherein: each of the first, third, and fifth portions comprises a plurality of fins; the first gate structure is disposed over the plurality of fins in the first portion; a total number of fins in the fourth portion is less than a total number of fins in the fifth portion; a first fin in the first portion is connected to a first fin in the third portion via a first fin in the second portion; and a second fin in the first portion is separated from a second fin in the third portion by at least one separation region in the second portion. a second drain / source region disposed in the third portion; and a third source / drain region disposed in the fifth portion; wherein: each of the first, third, and fifth portions comprises a plurality of fins; a total number of fins in the fourth portion is less than a total number of fins in the fifth portion; a first fin in the first portion is connected to a first fin in the third portion via a first fin in the second portion; a second fin in the first portion is separated from a second fin in the third portion by at least one separation region in the second portion; the first fin in the second portion is over the substrate and not over a trench formed in the substrate; and the separation region in the second portion is over the substrate and over at least a portion of a second trench formed in the substrate.

14. The finFET device of claim 13, wherein: a third fin in the first portion is connected to a third fin in the third portion via a third fin in the second portion; a first region between the first and third fins in the first portion is over the substrate and over at least a portion of a third trench; a second region between the first and third fins in the first portion is over the substrate and over at least another portion of the third trench and over at least a portion of a fourth trench; a third region between the first and third fins in the second portion is over the substrate and over at least another portion of the fourth trench; and a fourth region between the first and third fins in the third portion is over the substrate and over at least a portion of a fifth trench.

15. The finFET device of claim 12, wherein: the second portion comprises a first outer portion, a middle portion, and a second outer portion parallel to each other; the first and second outer portions of the second portion and the middle portion are positioned between the first portion and the third portion; the first outer portion of the second portion is at a first side of the middle portion of the second portion and the second outer portion of the second portion is at a second side of the middle portion of the second portion opposite the first side of the middle portion of the second portion; the middle portion of the second portion comprises one or some fins; and the first and second outer portions of the second portion are free of fins.

16. The finFET device of claim 15, wherein: each of the first and third portions comprises a first outer portion, a middle portion, and a second outer portion parallel to each other; the first and second outer portions of the second portion are respectively positioned between the first and second outer portions of the first portion and the first and second outer portions of the third portion; the first outer portion of the first portion is at a first side of the middle portion of the first portion and the second outer portion of the first portion is at a second side of the middle portion of the first portion opposite the first side of the first portion; the first outer portion of the third portion is at a first side of the middle portion of the third portion and the second outer portion of the third portion is at a second side of the middle portion of the third portion opposite the first side of the third portion; the one or some fins of the middle portion of the second portion are connected to corresponding one or some fins of the middle portion of the first portion and to corresponding one or some fins of the middle portion of the third portion; and fins of the first and second outer portions of the first portion are separated from corresponding first and second outer portions of the third portion by at least the corresponding first and second outer portions of the second portion.

17. A method of fabricating a fin-based field effect transistor (finFET) device, comprising: providing a fin structure comprising a first portion, a second portion, a third portion, a fourth portion, and a fifth portion; providing a first source / drain region in the first portion; providing a second drain / source region in the third portion and a third source / drain region disposed in the fifth portion; and providing a first gate structure over at least a portion of the first portion and a second gate structure disposed over at least a portion of the fifth portion, wherein: each of the first, third, and fifth portions comprises a plurality of fins; the first gate structure is disposed over the plurality of fins in the first portion; a total number of fins in the second portion is less than a total number of fins in the first portion; and a total number of fins in the fourth portion is less than a total number of fins in the fifth portion.

18. A method of fabricating a fin-based field effect transistor (finFET) device, comprising: providing a fin structure comprising a first portion, a second portion, a third portion, a fourth portion, and a fifth portion; providing a first source / drain region in the first portion; providing a second drain / source region in the third portion and a third source / drain region disposed in the fifth portion; and providing a first gate structure over at least a portion of the first portion and a second gate structure disposed over at least a portion of the fifth portion, wherein: each of the first, third, and fifth portions comprises a plurality of fins; a total number of fins in the second portion is less than a total number of fins in the first portion; and a total number of fins in the fourth portion is less than a total number of fins in the fifth portion; providing a first well region formed in a substrate and doped with dopants of a first type, wherein: a first fin in the first portion is connected to a first fin in the third portion via a first fin in the second portion; a second fin in the first portion is separated from a second fin in the third portion by at least one separation region in the second portion; the first fin in the second portion is over a first portion of the first well region and not over a trench formed in the substrate; and the separation region in the second portion is over a second portion of the first well region and over at least a portion of a second trench formed in the substrate.

19. The method of claim 18, further comprising: providing a second well region formed in the substrate and doped with dopants of a second type, wherein: a third fin in the first portion is connected to a third fin in the third portion via a third fin in the second portion; a first region at a first end between the first and third fins in the first portion is over a first portion of the second well region and over at least a portion of a third trench; a second region at the first gate structure between the first and third fins in the first portion is over a second portion of the second well region and over a third portion of the first well region; a third region between the first and third fins in the second portion is over a fourth portion of the first well region and over at least a portion of a fourth trench; and a fourth region between the first and third fins in the third portion is over a fifth portion of the first well region and over at least a portion of a fifth trench.

20. The method of claim 18, wherein: the first portion of the first well region is over a first portion of the second well region and over at least a portion of a first trench; the second portion of the first well region is over a second portion of the second well region and over at least a portion of a second trench; and the third portion of the first well region is over a third portion of the second well region and over at least a portion of a third trench.

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