A semiconductor structure and a method of manufacturing the same

Abstract

The application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a plurality of vertical transistors in an aligned arrangement are formed on the substrate, a channel material of the vertical transistors comprises an oxide semiconductor, a plurality of contact pads in a staggered arrangement are formed on the vertical transistors and connected with upper ends of the vertical transistors, a single contact pad is connected with the upper ends of an even number of vertical transistors, and a magnetic tunnel junction is formed above the contact pads. In this way, a plurality of transistors are combined with a single magnetic tunnel junction, a plurality of transistors are used to drive a magnetic tunnel junction, the driving current of the magnetic tunnel junction is increased, and the storage array of the magnetic random access memory is effectively driven.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] MRAM (Magnetoresistive Random Access Memory) has the high read and write capabilities of static random access memory and the high integration of dynamic random access memory, and can be written repeatedly indefinitely.

[0003] Currently, the capacity of MRAM is increased by combining MTJ (Magnetic Tunnel Junction) with transistors, so that the capacity of MRAM is expanded from the MB range to the GB range.

[0004] However, the driving current of the transistor is relatively small, which makes it difficult for the transistor to drive the MARM memory array. Summary of the Invention

[0005] The present application provides a semiconductor structure and a manufacturing method thereof, which are used to solve the problem that transistors are difficult to drive a MARM storage array.

[0006] In a first aspect, the present application provides a semiconductor structure, comprising:

[0007] substrate;

[0008] a plurality of vertical transistors arranged in an aligned manner on the substrate, wherein a channel material of the vertical transistors comprises an oxide semiconductor;

[0009] a plurality of contact pads connected to the upper ends of the vertical transistors and arranged in a staggered manner, wherein a single contact pad is connected to the upper ends of an even number of the vertical transistors;

[0010] A magnetic tunnel junction is located above the contact pad.

[0011] Optionally, the oxide semiconductor includes indium gallium zinc oxide.

[0012] Optionally, also include:

[0013] A plurality of word lines are arranged at intervals, and the plurality of vertical transistors connected to a single contact pad are respectively connected to at least two word lines.

[0014] Optionally, a single contact pad is connected to the upper ends of four vertical transistors.

[0015] Optionally, the four vertical transistors connected to a single contact pad are respectively connected to two word lines.

[0016] Optionally, the word line extends along a first direction;

[0017] The vertical transistors connected to the same word line are respectively connected to different contact pads, and adjacent contact pads are staggered and located on both sides of the word line.

[0018] Optionally, projections of side edges of adjacent staggered contact pads on the word line are located on the same straight line.

[0019] Optionally, the projection of the contact pad on the surface of the substrate covers the projection of the vertical transistor connected to the contact pad on the surface of the substrate.

[0020] Optionally, also include:

[0021] A plurality of bit lines extending along a second direction, the bit lines connecting the plurality of magnetic tunnel junctions, the second direction being perpendicular to the first direction.

[0022] In a second aspect, the present application provides a method for manufacturing a semiconductor structure, comprising:

[0023] Providing a substrate, forming a plurality of vertical transistors in an aligned arrangement on the substrate, wherein a channel material of the transistors comprises an oxide semiconductor;

[0024] forming a plurality of contact pads connected to the upper ends of the vertical transistors in a staggered arrangement, and connecting a single contact pad to the upper ends of an even number of the vertical transistors;

[0025] A magnetic tunnel junction is formed over the contact pad.

[0026] Optionally, the oxide semiconductor includes indium gallium zinc oxide.

[0027] Optionally, also include:

[0028] A plurality of word lines arranged at intervals are formed, and the plurality of vertical transistors connected to a single contact pad are respectively connected to at least two word lines.

[0029] Optionally, connecting a single contact pad to upper ends of an even number of vertical transistors specifically includes:

[0030] The single contact pad is connected to the upper ends of the four vertical transistors.

[0031] Optionally, the step of connecting the plurality of vertical transistors connected to the single contact pad to at least two word lines respectively includes:

[0032] The four vertical transistors connected to the single contact pad are connected to two word lines, respectively.

[0033] Optionally, the word line extends along a first direction;

[0034] The step of connecting the four vertical transistors connected to the single contact pad to the two word lines respectively includes:

[0035] The vertical transistors connected to the same word line are respectively connected to different contact pads, and adjacent contact pads are staggered and located on both sides of the word line.

[0036] Optionally, projections of side edges of the staggered adjacent contact pads on the word line are located on the same straight line.

[0037] Optionally, the projection of the contact pad on the surface of the substrate covers the projection of the vertical transistor connected to the contact pad on the surface of the substrate.

[0038] Optionally, also include:

[0039] A plurality of bit lines extending along a second direction are formed, the bit lines connecting the plurality of magnetic tunnel junctions, and the second direction is perpendicular to the first direction.

[0040] The present application provides a semiconductor structure comprising a substrate on which are formed a plurality of aligned vertical transistors. The channel material of the vertical transistors comprises an oxide semiconductor. A plurality of staggered contact pads connected to the top ends of the vertical transistors are formed on the vertical transistors. A single contact pad is connected to the top ends of an even number of vertical transistors, and a magnetic tunnel junction is formed above the contact pad. In this manner, multiple transistors are combined with a single magnetic tunnel junction, and the multiple transistors are used to drive the magnetic tunnel junction, thereby increasing the drive current of the magnetic tunnel junction and effectively driving the memory array of a magnetic random access memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0042] Figure 1-14 A schematic cross-sectional view of a semiconductor structure provided in one embodiment of the present application;

[0043] Figure 15 A schematic top view of a semiconductor structure provided in one embodiment of the present application;

[0044] Figure 16 A schematic cross-sectional view of a semiconductor structure provided in one embodiment of the present application;

[0045] Figure 17 A schematic top view of a semiconductor structure provided in one embodiment of the present application;

[0046] Figure 18 A schematic cross-sectional view of a semiconductor structure provided in accordance with an embodiment of the present application. DETAILED DESCRIPTION

[0047] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0048] At present, the capacity of MRAM is increased by combining MTJ (Magnetic Tunnel Junction) with transistors, so that the capacity of MRAM is expanded from the MB range to the GB range. That is, MRAM is improved to form STT-MRAM (spin-transfer torque Magnetoresistive Random Access Memory). STT-MRAM is a new type of non-volatile magnetic memory that writes information through spin current. It includes a magnetic tunnel junction and a transistor. The magnetic tunnel junction includes a fixed layer, an insulating layer and a free layer stacked in sequence. The magnetization direction of the fixed layer is fixed, and the magnetization direction of the free layer is easily changed under the action of a magnetic field or a spin-polarized current. The drain of the transistor is connected to one end of the magnetic tunnel junction, such as the fixed layer of the magnetic tunnel junction, and the other end of the magnetic tunnel junction is connected to the bit line. When the transistor is turned on, the source, drain, magnetic tunnel junction and bit line of the transistor form a loop.

[0049] When current flows from the fixed layer to the free layer, electrons whose spin direction is consistent with the magnetization direction of the fixed layer are more likely to pass through the fixed layer, so that after passing through the fixed layer, polarized electrons with the same magnetization direction as the fixed layer are generated. When the spin-polarized electrons pass through the fixed layer and reach the free layer, the electrons whose spin direction is consistent with the magnetization direction of the free layer enter the free layer and generate a torque on the magnetic moment of the free layer. This torque causes the magnetization direction of the free layer to turn in a direction parallel to the fixed layer. At the same time, electrons with the opposite magnetization direction to the free layer are reflected back to the fixed layer, generating a torque that rotates the magnetization direction of the fixed layer. However, this torque cannot rotate the magnetization direction of the fixed layer, and ultimately makes the magnetization direction of the free layer parallel to the magnetization direction of the fixed layer. The resistance of the magnetic tunnel junction is small, and the STT-MRAM completes writing the information "0".

[0050] When current flows from the free layer to the fixed layer, electrons whose spin direction is consistent with the magnetization direction of the free layer are more likely to pass through the free layer, so that after passing through the free layer, polarized electrons with the same magnetization direction as the free layer are generated. When the spin-polarized electrons pass through the free layer and reach the fixed layer, the electrons whose spin direction is consistent with the magnetization direction of the fixed layer enter the fixed layer and generate a torque on the magnetic moment of the fixed layer. This torque cannot rotate the magnetization direction of the fixed layer, while the electrons whose spin direction is opposite to the magnetization direction of the fixed layer are reflected back to the free layer, generating a torque that rotates the magnetization direction of the free layer. This torque causes the magnetization direction of the free layer to turn in a direction antiparallel to the magnetization direction of the fixed layer, and ultimately makes the magnetization direction of the free layer antiparallel to the magnetization direction of the fixed layer. The resistance of the magnetic tunnel junction is large, and the STT-MRAM completes writing the information "1".

[0051] STT-MARM writes information by generating a magnetic field through current, causing the free layer magnetic moment to reverse, changing the resistance of the magnetic tunnel junction and thus writing information. Writing information requires a large current to generate a magnetic field that flips the free layer magnetic moment of the magnetic tunnel junction. As the size of the memory cell decreases, a larger magnetic field is needed to flip the free layer magnetic moment, and therefore a larger current is required. However, the current drive current of transistors is relatively low, making it difficult for transistors to drive the MARM memory array.

[0052] To this end, the present application provides a semiconductor structure comprising: a plurality of vertical transistors aligned on a substrate, the channel material of the vertical transistors comprising an oxide semiconductor, a plurality of staggered contact pads connected to the upper ends of the vertical transistors formed at the upper ends of the vertical transistors, a single contact pad connected to the upper ends of an even number of the vertical transistors, and a magnetic tunnel junction formed above the contact pads. By connecting the plurality of vertical transistors to a single contact pad, i.e., connecting the plurality of vertical transistors to a single magnetic tunnel junction via the contact pad, the plurality of vertical transistors drives the magnetic tunnel junction, thereby increasing the drive current for driving the magnetic tunnel junction and effectively driving the storage array of a magnetic random access memory.

[0053] The following specific embodiments are used to describe the technical solution of the present application in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0054] The present application provides a semiconductor structure, referring to Figure 16 and Figure 17 Shown, including:

[0055] substrate 100;

[0056] A plurality of vertical transistors are arranged in an aligned manner on the substrate 100, wherein the channel material of the vertical transistors includes an oxide semiconductor;

[0057] a plurality of contact pads 112 connected to the upper ends of the vertical transistors and arranged in a staggered manner, wherein a single contact pad 112 is connected to the upper ends of an even number of vertical transistors;

[0058] A magnetic tunnel junction 113 is located above the contact pad 112 .

[0059] In the embodiment of the present application, the substrate 100 is a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) substrate, or a GOI (Germanium On Insulato). In other embodiments, the semiconductor substrate may also be a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. It may also be a stacked structure, such as Si / SiGe. It may also be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator). In this embodiment, the substrate 100 may be a single crystal silicon substrate for supporting a device structure thereon.

[0060] A plurality of vertical transistors are formed on the substrate 100 in an aligned arrangement. Figure 16 For ease of description, the end of the vertical transistor in contact with the substrate 100 is referred to as the lower end of the vertical transistor, and the end opposite to the lower end is referred to as the upper end of the vertical transistor. Aligning multiple vertical transistors means that the upper ends of the vertical transistors are on the same horizontal plane.

[0061] The vertical transistor includes a source, a drain, a gate and a channel. Multiple vertical transistors can share a source plate 101 to simplify the manufacturing process. Figure 12 As shown, a source plate 101 is formed on the substrate 100. The source plate 101 is the source of each vertical transistor. The material of the source plate 101 can be indium tin oxide (ITO), molybdenum (Mo), aluminum (Al), titanium aluminum alloy (Ti / Al), etc.

[0062] An isolation layer 102 is formed on the source plate 101 , and a word line 103 is formed on the isolation layer 102 . The isolation layer 102 isolates the source plate 101 from the word line 103 . The isolation layer 102 may be made of silicon oxide.

[0063] In this embodiment, a plurality of word lines 103 arranged at intervals can be formed on the isolation layer 102, and the intervals between adjacent word lines 103 can be determined according to actual needs. A plurality of channels 110 are formed in each word line 103, referring to Figure 13As shown, multiple channels 110 all pass through the word line 103 to the source plate 101. The material of the channel 110 may include an oxide semiconductor to improve the conductivity of the source plate 101. The oxide semiconductor may be, for example, indium gallium zinc oxide, to reduce the temperature of the channel 110 formation process and increase the ratio of the current when the channel 110 is open and closed. For example, the temperature of the channel 110 formation process is lower than 300°C, and the ratio of the current when the channel 110 is open and closed is greater than 10 8 At the same time, because indium gallium zinc oxide can be grown on any desired surface, when indium gallium zinc oxide is used as the channel material, the channel 110 can be extended from a two-dimensional direction to a three-dimensional direction. A drain 111 is formed on each channel 110.

[0064] Please refer to Figure 16 At this time, a channel 110, the word line 103 where the channel 110 is located, the source plate 101, and the drain 111 on the channel 110 form a vertical transistor. The word line 103 where the channel 110 is located is the gate of the vertical transistor. Obviously, since multiple word lines 103 are formed on the source plate 101 and multiple channels 110 are formed in one word line 103, multiple vertical transistors can be formed on the substrate 100, and the multiple vertical transistors are in a honeycomb array.

[0065] The end of the channel 110 that contacts the source plate 101 is called the bottom end of the channel 110, and the end opposite to the bottom end is called the top end of the channel 110. The drain 111 of the vertical transistor is formed at the top end of the channel 110. A gate oxide layer 109 is formed between the channel 110 and the word line 103, and between the channel 110 and the source plate 101. The gate oxide layer 109 surrounds the channel 110, and the height of the gate oxide layer 109 is consistent with the height of the channel 110. Figure 13 As shown, the material of the gate oxide layer 109 may include a high-k oxide, such as hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), hafnium oxynitride (HfON), etc.

[0066] A plurality of contact pads 112 are formed on the upper end of the vertical transistor in a staggered arrangement, and the number of the contact pads 112 is an even number, so that the shape of the contact pads 112 is a relatively regular square, which reduces the possibility of contact between the adjacent contact pads 112 and improves the performance of the device. Figure 14 and Figure 15 As shown, Figure 14 is a schematic diagram of the cross-sectional structure of a semiconductor structure. Figure 15 1 is a schematic top view of a semiconductor structure. Multiple columns of contact pads 112 are formed on the vertical transistor. Each column includes multiple contact pads 112 , and the contact pads 112 in adjacent columns do not overlap.

[0067] For example, multiple columns of contact pads are formed on a vertical transistor, such as a first column, a second column, and a third column. The contact pads 112 in the first column and the second column are staggered, and the contact pads 112 in the second column and the third column are staggered. Accordingly, the contact pads 112 in the first column and the third column can overlap, that is, the contact pads 112 in the first column and the third column can be on the same horizontal plane.

[0068] The number of vertical transistors and the number of contact pads 112 can be determined according to actual conditions and are not limited here. For example, a single contact pad 112 can be formed on the top of four vertical transistors, that is, a single contact pad 112 is connected to the top of four vertical transistors.

[0069] The four vertical transistors connected to a single contact pad 112 can be connected to two word lines 103 respectively, so that the shape of the contact pad 112 is quadrilateral, which is convenient for subsequent connection with the bit line. The two word lines 103 can be adjacent word lines, so that the shape of the contact pad 112 is rectangular, referring to Figure 15 Specifically, two of the four vertical transistors are connected to one word line 103, and the other two vertical transistors are connected to another word line 103. Since the four vertical transistors are rectangular, the shape of a contact pad 112 connected to the four vertical transistors can be rectangular.

[0070] The direction in which the word line 103 extends is referred to as the first direction. That is, the word line 103 extends in the first direction. In the first direction, the plurality of vertical transistors connected to the same word line are connected to different contact pads 112, and the adjacent contact pads 112 are staggered on both sides of the word line 103. For example, two vertical transistors connected to the same word line are connected to two contact pads 112, respectively. Figure 15 In the dotted area, the two contact pads 112 in the dotted area are called the first contact pad 1121 and the second contact pad 1122, and the two vertical transistors are called the first vertical transistor 1201 and the second vertical transistor 1202. The first vertical transistor 1201 is connected to the first contact pad 1121, and the second vertical transistor 1202 is connected to the second contact pad 1122, and the first contact pad 1121 and the second contact pad 1122 are staggered on both sides of the word line 103.

[0071] The projections of the sides of the adjacent staggered contact pads 112 onto the word line 103 are aligned, reducing the size of the contact pads 112 and saving costs. When the projections of the sides of the adjacent staggered first contact pads 1121 and second contact pads 1122 onto the word line 103 are aligned, the first contact pad 1121 can be connected to a portion of the first vertical transistor 1201, and the second contact pad 1122 can be connected to a portion of the second vertical transistor 1202. When the area of ​​the upper end surface of the first vertical transistor 1201 is equal to the area of ​​the upper end surface of the second vertical transistor 1202, the area of ​​the part of the first contact pad 1121 connected to the first vertical transistor 1201 and the area of ​​the part of the second contact pad 1122 connected to the second vertical transistor 1202 can be added together to be equal to the area of ​​the upper end surface of the first vertical transistor 1201. For example, the first contact pad 1121 is connected to half of the upper end surface of the first vertical transistor 1201, and the second contact pad 1122 is connected to half of the upper end surface of the second vertical transistor 1202. The first contact pad 1121 and the second contact pad 1122 can be formed using the same mask pattern to simplify the process.

[0072] The projection of the contact pad 112 on the surface of the substrate 100 covers the projection of the vertical transistor connected to the contact pad 112 on the surface of the substrate 100. At this time, the area of ​​the single contact pad 112 formed on the multiple vertical transistors is greater than or equal to the area of ​​the multiple vertical transistors, so that the contact pad 112 can cover the multiple vertical transistors connected to the contact pad 112, thereby effectively connecting the multiple vertical transistors together.

[0073] A magnetic tunnel junction 113 is formed above the contact pad 112. Figure 16 Shown to Figure 18 As shown, Figure 16 is a schematic diagram of the cross-sectional structure of a semiconductor structure. Figure 17 It is a schematic diagram of the top view of the semiconductor structure. Figure 18 The cross-sectional structure diagram of the semiconductor structure shows a magnetic tunnel junction 113 including a fixed layer 114, an insulating layer 115, and a free layer 116 stacked in sequence. The insulating layer 115 isolates the fixed layer 114 from the free layer 116. When the magnetization directions of the fixed layer 114 and the free layer 116 are the same, the magnetic tunnel junction 113 is in a low-resistance state. When the magnetization directions of the fixed layer 114 and the free layer 116 are opposite, the magnetic tunnel junction 113 is in a high-resistance state. The materials of the fixed layer 114 and the free layer 116 can be the same or different, such as iron (Fe), cobalt (Co), nickel (Ni), or alloys thereof. The fixed layer 114 and the free layer 116 can have the same or different thicknesses, the same or different sizes, and the same or different shapes, such as cylindrical or square columns.

[0074] Multiple bit lines 117 can also be formed on the magnetic tunnel junction 113 to improve the high resistance of the buried bit line. The direction in which the word line 103 extends is referred to as the first direction, and the direction in which the bit line 117 extends is referred to as the second direction. Multiple bit lines 117 extending along the second direction are formed on the magnetic tunnel junction 113. Each bit line 117 can connect multiple magnetic tunnel junctions 113, and the first and second directions can be perpendicular. Then, by selecting the address of the word line 103 and applying a voltage to the bit line 117, the magnetization direction of the free layer 116 is flipped through a spin transfer torque (STT) write method, enabling writing to the magnetic random access memory.

[0075] The present application provides a semiconductor structure in which a plurality of staggered contact pads connected to the upper ends of vertical transistors are formed on vertical transistors. A single contact pad is connected to the upper ends of an even number of vertical transistors. Multiple transistors are used to drive a magnetic tunnel junction, thereby increasing the drive current of the magnetic tunnel junction and effectively driving the storage array of a magnetic random access memory.

[0076] The present invention also provides a method for manufacturing a semiconductor structure, including:

[0077] S101 , providing a substrate 100 , and forming a plurality of vertical transistors in an aligned arrangement on the substrate 100 , wherein the channel material of the transistors includes an oxide semiconductor.

[0078] Please refer to Figure 1 The substrate 100 is a semiconductor substrate, a source plate 101 is formed on the substrate 100, and an isolation layer 102 is formed on the source plate 101. Specifically, a conductive material, such as indium tin oxide (ITO), molybdenum (Mo), aluminum (Al), titanium aluminum alloy (Ti / Al), etc., is deposited on the substrate 100 using an atomic layer deposition method (ALD) or a chemical vapor deposition method (CVD). A planarization process is performed on the deposited conductive material to form the source plate 101 on the substrate 100. Then, a dielectric material, such as silicon oxide, silicon nitride, etc., is deposited on the source plate 101, and a planarization process is performed on the deposited dielectric material to form the isolation layer 102 on the source plate 101.

[0079] Then, word lines 103 are formed on the isolation layer 102. First, a metal material is deposited on the isolation layer 102. The metal material may be tungsten (W), molybdenum (Mo), etc., and a planarization process is performed on the metal material to form an initial word line layer 103' on the isolation layer 102. Figure 1 shown.

[0080] The initial word line layer 103' is patterned using a self-aligned double patterning method or a self-aligned quadruple patterning method to obtain a plurality of word lines 103 with smaller sizes and spaced apart. The self-aligned double patterning method includes: forming a first photoresist layer 104 on the initial word line layer 103', referring to Figure 2 As shown, the material of the first photoresist layer 104 can be silicon oxide. A dielectric material is deposited on the surface of the first photoresist layer 104 and the surface of the initial word line layer 103'. Figure 3 As shown, the dielectric material can be, for example, silicon nitride. The dielectric material on the upper surface of the first photoresist layer 104 and the dielectric material on the surface of the initial word line layer 103' are removed, and the dielectric material on the sidewall of the first photoresist layer 104 is retained. Then, the first photoresist layer 104 can be removed using a hydrofluoric acid solution to form a first mask layer 105. Figure 4 shown.

[0081] The self-aligned quadruple patterning method is a technique of performing two self-aligned double patterning to obtain a smaller word line 103. Specifically, a dielectric material is deposited on the surface of the first mask layer 105 and the surface of the initial word line layer 103'. The dielectric material can be silicon oxide. Figure 5 The dielectric material on the surface of the first mask layer 105 and the surface of the initial word line layer 103' is removed, and the dielectric material on the sidewall of the first mask layer 105 is retained. The first mask layer 105 is removed by using a phosphoric acid solution, thereby forming a second mask layer 106 on the initial word line layer 103'. Figure 6 As shown. In this way, the size of the second mask layer 106 is small, and the initial word line layer 103' is etched with the second mask layer 106 as a shield, thereby forming a plurality of small word lines 103 on the isolation layer 102, referring to Figure 7 As shown, the storage density of the device is improved.

[0082] Subsequently, a dielectric material is deposited on the surface of the word line 103 to form a capping layer 107. Figure 8 and Figure 9 As shown, Figure 8 is a schematic diagram of the cross-sectional structure in the first direction, Figure 9 The thickness of the cover layer 107 is greater than the dimension of the word line 103 in the direction perpendicular to the substrate, so as to protect the word line 103.

[0083] For example, reactive ion etching is used to etch the cover layer 107, the word line 103 and the isolation layer 102 to the source plate 101, thereby forming a plurality of channel holes 108 penetrating the cover layer 107, the word line 103 and the isolation layer 102 to the source plate 101. Figure 10 As shown, the channel hole 108 may be located on or in the source plate 101 .

[0084] In the channel hole 108, a high-k dielectric material, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium oxynitride (HfON), etc., is deposited by ALD to form a gate oxide layer 109 on the sidewall of the channel hole 108. Figure 11 As shown. The channel hole 108 is filled with an oxide semiconductor material, such as indium gallium zinc oxide, and then planarized to form a channel 110. Figure 12 shown.

[0085] Then, a drain 111 is formed on the channel 110. Figure 13 As shown. Each channel 110 has a corresponding drain 111. The method for forming the drain 111 may be to remove a portion of the oxide semiconductor material at the top of the channel 110 to form a groove in the channel 110, and fill the groove with a conductive material to form the drain 111. The method for forming the drain 111 may also be to deposit a conductive material on the channel 110 and the cover layer 107, and then remove the conductive material on the cover layer 107 to form the drain 111 on the channel 110. The resistance of the portion of the oxide semiconductor material at the top of the channel 110 may also be reduced by doping, ion implantation, plasma treatment, metal induction, etc., so as to form the drain 111 on the channel 110.

[0086] A channel 110, the word line 103 on which the channel 110 resides, the source plate 101, and the drain 111 on the channel 110 form a vertical transistor. The word line 103 on which the channel resides serves as the gate of the vertical transistor. Since multiple word lines 103 are formed on the source plate 101, and multiple channels 110 are formed in a single word line 103, multiple vertical transistors can be formed on the substrate 100. Multiple channels 110 share a single source plate 101. In a direction perpendicular to the substrate 100, the multiple channels 110 have the same dimensions and the same drains, so that the top ends of the multiple vertical transistors are on the same horizontal plane, thereby forming multiple vertical transistors aligned on the substrate 100.

[0087] S102, forming a plurality of staggered contact pads 112 connected to the upper ends of the vertical transistors, connecting a single contact pad 112 to the upper ends of an even number of vertical transistors, referring to Figure 14 and 15 shown.

[0088] A metal material is deposited on the covering layer 107, and the deposited metal material is patterned to form a plurality of contact pads 112. Since the upper ends of the vertical transistors are aligned, the contact pads 112 effectively connect the plurality of vertical transistors together. The plurality of contact pads 112 are staggered to avoid contact between adjacent contact pads. For example, a plurality of columns of contact pads are formed in a direction parallel to the substrate 100, and the contact pads 112 in adjacent columns do not overlap. The projection of the contact pad 112 on the surface of the substrate 100 covers the projection of the vertical transistor connected to the contact pad 112 on the surface of the substrate 100. For example, the projection of each contact pad 112 in each column on the surface of the substrate 100 covers the projection of the vertical transistor connected to the contact pad 112 on the surface of the substrate 100.

[0089] Each contact pad 112 is connected to the top of an even number of vertical transistors, that is, each contact pad 112 is connected to the drains 111 of an even number of vertical transistors, so that the contact pads 112 have a relatively regular square shape, reducing the possibility of contact between connected contact pads 112. The multiple vertical transistors connected to a single contact pad 112 can be connected to at least two word lines. For example, a single contact pad 112 can be connected to the top of four vertical transistors. The four vertical transistors connected to a single contact pad 112 are each connected to two word lines.

[0090] The direction in which the word line extends is referred to as the first direction, and the vertical transistors connected to the same word line are connected to different contact pads 112, and adjacent contact pads 112 are staggered on both sides of the word line 103. Figure 15 In the dotted area, the two contact pads 112 in the dotted area are referred to as first contact pad 1121 and second contact pad 1122, and the two vertical transistors are referred to as first vertical transistor 1201 and second vertical transistor 1202. The first vertical transistor 1201 is connected to the first contact pad 1121, and the second vertical transistor 1202 is connected to the second contact pad 1122. The first contact pad 1121 and the second contact pad 1122 are staggered on both sides of the word line 103. The projections of the side edges of the staggered contact pads 112 on the word line 103 are on the same straight line, which reduces the size of the contact pads 112 and saves cost.

[0091] S103, forming a magnetic tunnel junction 113 above the contact pad 112, referring to Figures 16 to 18 shown.

[0092] A dielectric material, such as oxide, is deposited on the contact pad 112 and the cover layer 107 to form a dielectric layer 118 covering the contact pad 112, and then a fixed layer 114, an insulating layer 115 and a free layer 116 are sequentially formed on the dielectric layer 118. Figure 16 As shown, the fixed layer 114 is in contact with the contact pad 112 .

[0093] Specifically, the two directions parallel to the substrate 100 are referred to as the X direction and the Y direction, respectively. A fixed layer plate, an insulating layer plate, and a free layer plate are sequentially formed on the dielectric layer 118. The fixed layer plate, the insulating layer plate, and the free layer plate are patterned in the X direction and the Y direction to obtain a fixed layer 114, an insulating layer 115, and a free layer 116 stacked in sequence.

[0094] For example, a third photoresist layer is formed on the free layer, the third photoresist layer includes a plurality of strip structures spaced apart in the X direction, a third mask layer is formed on the sidewalls of the third photoresist layer, the third photoresist layer is removed, and the third mask layer is used as a shield to etch the free layer, the insulating layer, and the fixed layer until the contact pad 112, so that the free layer, the insulating layer, and the fixed layer include a plurality of strip structures in the X direction, and the strip structures extend in the Y direction. The third mask layer is removed, and then a fourth photoresist layer is formed on each of the multiple strip structures. The fourth photoresist layer includes multiple strip structures in the Y direction, and the size of the strip structures in the X direction is the same as the size of the third mask layer in the X direction. A fourth mask layer is formed on the sidewalls of the fourth photoresist layer. The third photoresist layer is removed, and the fourth mask layer is used as a shield to etch the free layer, the insulating layer, and the fixed layer to the contact pad 112, thereby forming a magnetic tunnel junction on each contact pad 112, namely, the fixed layer 114, the insulating layer 115, and the free layer 116 stacked in sequence.

[0095] refer to Figure 17 and Figure 18 As shown, in order to more clearly present the semiconductor structure of this application, Figure 17 The dielectric layer 118 is not shown. Multiple bit lines 117 can be formed on the magnetic tunnel junction 113 to improve the high resistance of the buried bit line. The direction in which the word line 103 extends is referred to as the first direction, and the direction in which the bit line 117 extends is referred to as the second direction. Multiple bit lines 117 extending along the second direction are formed on the magnetic tunnel junction 113. Each bit line 117 can connect multiple magnetic tunnel junctions 113. The first and second directions can be perpendicular. Then, by selecting a word line 103 and applying a voltage to the bit line 117, the magnetization direction of the free layer 116 is flipped through spin transfer torque writing, enabling writing to the magnetic random access memory.

[0096] The semiconductor structure provided by the embodiments of the present application forms multiple vertical transistors aligned on a substrate. The channel material of the vertical transistors comprises an oxide semiconductor. A plurality of staggered contact pads connected to the upper ends of the vertical transistors are formed at the upper ends of the vertical transistors. A single contact pad is connected to the upper ends of an even number of vertical transistors, forming a magnetic tunnel junction above the contact pads. Multiple vertical transistors are connected to a magnetic tunnel junction via the contact pads. This magnetic tunnel junction is driven by the multiple vertical transistors, increasing the drive current of the magnetic tunnel junction and effectively driving the memory array of a magnetic random access memory.

[0097] Finally, it should be noted that the above embodiments are intended only to illustrate the technical solutions of this application and are not intended to limit them. Although this application has been described in detail with reference to the aforementioned embodiments, those skilled in the art will appreciate that they may modify the technical solutions described in the aforementioned embodiments or replace some or all of the technical features therein with equivalents. However, such modifications or replacements do not deviate from the essence of the corresponding technical solutions within the scope of the various embodiments of this application.

Claims

1. A semiconductor structure, characterized in that include: substrate; a plurality of vertical transistors arranged in an aligned manner on the substrate, wherein a channel material of the vertical transistors comprises an oxide semiconductor; a plurality of contact pads connected to the upper ends of the vertical transistors and arranged in a staggered manner, wherein a single contact pad is connected to the upper ends of an even number of the vertical transistors; a magnetic tunnel junction located above the contact pad; A plurality of word lines are arranged at intervals, and the plurality of vertical transistors connected to a single contact pad are respectively connected to at least two word lines.

2. The semiconductor structure according to claim 1, wherein: The oxide semiconductor includes indium gallium zinc oxide.

3. The semiconductor structure according to claim 1, wherein: The single contact pad is connected to the upper ends of the four vertical transistors.

4. The semiconductor structure according to claim 3, wherein: The four vertical transistors connected to the single contact pad are respectively connected to two word lines.

5. The semiconductor structure according to claim 4, wherein: The word lines extend along a first direction; The vertical transistors connected to the same word line are respectively connected to different contact pads, and adjacent contact pads are staggered and located on both sides of the word line.

6. The semiconductor structure according to claim 5, wherein: Projections of side edges of the staggered adjacent contact pads on the word line are located on the same straight line.

7. The semiconductor structure according to claim 1, wherein: The projection of the contact pad on the substrate surface covers the projection of the vertical transistor connected to the contact pad on the substrate surface.

8. The semiconductor structure according to claim 5, wherein: Also includes: A plurality of bit lines extending along a second direction, the bit lines connecting the plurality of magnetic tunnel junctions, the second direction being perpendicular to the first direction.

9. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, forming a plurality of vertical transistors in an aligned arrangement on the substrate, wherein a channel material of the transistors comprises an oxide semiconductor; forming a plurality of contact pads connected to the upper ends of the vertical transistors in a staggered arrangement, and connecting a single contact pad to the upper ends of an even number of the vertical transistors; forming a plurality of word lines arranged at intervals, and connecting the plurality of vertical transistors connected to a single contact pad to at least two word lines respectively; A magnetic tunnel junction is formed over the contact pad.

10. The manufacturing method according to claim 9, characterized in that: The oxide semiconductor includes indium gallium zinc oxide.

11. The manufacturing method according to claim 10, characterized in that: Connecting the single contact pad to the upper ends of an even number of the vertical transistors specifically includes: The single contact pad is connected to the upper ends of the four vertical transistors.

12. The manufacturing method according to claim 11, characterized in that: The step of connecting the plurality of vertical transistors connected to the single contact pad to at least two word lines respectively includes: The four vertical transistors connected to the single contact pad are connected to two word lines, respectively.

13. The manufacturing method according to claim 12, characterized in that: The word lines extend along a first direction; The step of connecting the four vertical transistors connected to the single contact pad to the two word lines respectively includes: The vertical transistors connected to the same word line are respectively connected to different contact pads, and adjacent contact pads are staggered and located on both sides of the word line.

14. The manufacturing method according to claim 13, characterized in that: Projections of side edges of the staggered adjacent contact pads on the word line are located on the same straight line.

15. The manufacturing method according to claim 9, characterized in that: The projection of the contact pad on the substrate surface covers the projection of the vertical transistor connected to the contact pad on the substrate surface.

16. The manufacturing method according to claim 13, characterized in that: Also includes: A plurality of bit lines extending along a second direction are formed, wherein the bit lines connect the plurality of magnetic tunnel junctions, and the second direction is perpendicular to the first direction.

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