Semiconductor structure and method of making the same, memory

Abstract

The embodiment of the present application relates to the field of semiconductor, and provides a semiconductor structure, a manufacturing method thereof, and a memory, the semiconductor structure at least can include: a plurality of staggered arrangement transistors, the transistors share the same source plate, the channel of the transistor is located on the source plate, and the channel length direction of the transistor is perpendicular to the surface of the source plate, wherein the material of the channel includes oxide semiconductor;A plurality of drain contacts are electrically connected with the drain of the transistor, an odd number of the transistors share the same drain contact, and the transistors sharing the same drain contact are driven by the same word line;A plurality of magnetic tunnel junctions are located on the drain contact, and the magnetic tunnel junction is electrically connected with the drain contact one by one.The embodiment of the present application provides a new semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductors, and in particular to a semiconductor structure, a manufacturing method thereof, and a memory. Background Art

[0002] Semiconductor memory, including dynamic random access memory (DRAM) and magnetic random access memory (MRAM), is required for data storage in most electronic devices. Data storage requires a certain drive current. However, as semiconductor devices become increasingly miniaturized, the interconnection resistance between adjacent conductors increases as the contact area decreases. This reduces the drive current while maintaining the same drive voltage, making it impossible to maintain the original drive capability. Furthermore, increasing the voltage supplied by the voltage source to maintain the original drive current increases the power consumption of the semiconductor device. Summary of the Invention

[0003] The embodiments of the present application provide a new semiconductor structure that can at least maintain the original driving current level without increasing the overall power consumption.

[0004] According to some embodiments of the present application, on the one hand, the embodiments of the present application provide a semiconductor structure, including: a plurality of staggered transistors, the transistors sharing the same source plate, the channels of the transistors located on the source plate and the channel length direction of the transistors perpendicular to the surface of the source plate, wherein the material of the channel includes an oxide semiconductor; a plurality of drain contacts electrically connected to the drains of the transistors, an odd number of the transistors sharing the same drain contact, and the transistors sharing the same drain contact are driven by the same word line; a plurality of magnetic tunnel junctions located on the drain contacts, and the magnetic tunnel junctions are electrically connected to the drain contacts one-to-one.

[0005] According to some embodiments of the present application, another aspect of the present application further provides a memory comprising any of the semiconductor structures described above.

[0006] According to some embodiments of the present application, another aspect of the embodiments of the present application further provides a memory, comprising: forming a plurality of staggered transistors, the transistors sharing a same source plate, the channels of the transistors being located on the source plate and the channel length direction of the transistors being perpendicular to the surface of the source plate, wherein the material of the channel comprises an oxide semiconductor; forming a plurality of drain contacts electrically connected to the drains of the transistors, an odd number of the transistors sharing the same drain contact, and the transistors sharing the same drain contact being driven by the same word line; forming a plurality of magnetic tunnel junctions located on the drain contacts, the magnetic tunnel junctions being electrically connected to the drain contacts in a one-to-one correspondence.

[0007] The technical solution provided by the embodiments of the present application has at least the following advantages:

[0008] The above technical solution provides a new semiconductor structure, which uses oxide semiconductor as the channel material of the transistor. The transistor prepared based on oxide semiconductor has a higher switching current ratio, which is beneficial to improving the switching characteristics of the transistor; in addition, the drain contact can be connected to multiple transistors at the same time, which is beneficial to driving the magnetic tunnel junction through a large driving current without increasing the driving current of a single transistor, thereby realizing effective data storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] One or more embodiments are exemplarily described by the pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute proportional limitations.

[0010] Figures 1 to 4 A schematic structural diagram of a semiconductor structure provided in an embodiment of the present application;

[0011] Figures 5 to 12 This is a schematic structural diagram corresponding to each step of the method for manufacturing a semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0012] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0013] Figures 1 to 4 A schematic structural diagram of a semiconductor structure provided in an embodiment of the present application.

[0014] refer to Figures 1 to 4 The semiconductor structure includes: a plurality of transistors arranged in an interlaced manner, the transistors share a common source plate 12, the channels of the transistors are located on the source plate 12 and the length direction of the channels of the transistors is perpendicular to the surface of the source plate 12, wherein the material of the channels includes an oxide semiconductor; a plurality of drain contacts 18, electrically connected to the drains of the transistors, an odd number of transistors share the same drain contact 18, and the transistors sharing the same drain contact 18 are driven by the same word line 14; a plurality of magnetic tunnel junctions 20, located on the drain contacts 18, and the magnetic tunnel junctions 20 are electrically connected to the drain contacts 18 in a one-to-one correspondence.

[0015] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. In addition, for the sake of reading fluency, the different film layers or different structures of the semiconductor structure will be described below in a bottom-up order.

[0016] The semiconductor structure includes a substrate 11 and a source plate 12 located on the substrate 11. The substrate 11 can be composed of an insulating material to provide isolation. The substrate 11 can be a flexible substrate or a rigid substrate. The material of the flexible substrate includes polyimide, and the material of the rigid substrate includes glass. The source plate 12 can be independent of the transistor, serving as a source contact and providing a source signal for the transistor, or serving as the source of the transistor to receive a source signal. In any case, the material of the source plate 12 is a conductive material, such as at least one of doped polysilicon, indium tin oxide (ITO), metal molybdenum, metal aluminum, metal titanium, or metal copper.

[0017] In some embodiments, wordline 14, gate dielectric layer 16, and oxide semiconductor layer 17 constitute a transistor. Gate dielectric layer 16 surrounds the entire sidewall of oxide semiconductor layer 17. Wordline 14 surrounds a portion of the thickness of oxide semiconductor layer 17 and covers a portion of the sidewall of gate dielectric layer 16. The portion of oxide semiconductor layer 17 surrounded by wordline 14 serves as the transistor's channel. The portion of oxide semiconductor layer 17 located between the channel and source plate 12 serves as the transistor's source. Another portion of oxide semiconductor layer 17 located on the other side of the channel away from source plate 12 serves as the transistor's drain. In other words, gate dielectric layer 16 covers not only the transistor's channel sidewalls but also the source and drain sidewall surfaces of the transistor. In other embodiments, the gate dielectric layer is located only between the wordline and the channel, i.e., the gate dielectric layer only surrounds the channel sidewall surfaces.

[0018] It will be appreciated that regardless of whether the gate dielectric layer 16 covers the sidewall surfaces of the source and drain, the aforementioned transistors are all vertical gate-all-around (GAA) transistors, where vertical refers to the direction of the transistor's channel length being perpendicular to the plane extending from the underlying film layer. In some embodiments, as semiconductor structures shrink in size, the spacing between adjacent wordlines 14 decreases. In this case, wordlines 14 can be formed using an inverse self-aligned double patterning process.

[0019] In some embodiments, the oxide semiconductor material included in the oxide semiconductor layer 17 is indium gallium zinc oxide (IGZO). IGZO is composed of In2O3, Ga2O3, and ZnO, has a band gap of approximately 3.5 eV, and may have an amorphous structure. It should be noted that the oxide semiconductor layer 17 may be composed entirely of oxide semiconductor materials or may be predominantly oxide semiconductor materials, i.e., the oxide semiconductor layer 17 may also be doped with other materials that play a supporting role or serve as impurities.

[0020] In some embodiments, the gate dielectric layer 16 is made of a high-k material. For example, the gate dielectric layer 16 includes at least one of HfO2, ZrO2, or HfON. Using a high-k material for the gate dielectric layer 16 helps suppress gate leakage current caused by electron tunneling when the gate dielectric layer 16 is relatively thin.

[0021] In some embodiments, the semiconductor structure includes a substrate 11, a source plate 12, a first isolation layer 13, a word line 14 and a second isolation layer 15 stacked in sequence. The first isolation layer 13 is arranged between the word line 14 and the source plate 12 to isolate the source plate 12 and the word line 14; the second isolation layer 15 is arranged between adjacent word lines 14 and covers the top surface of the word line 14, mainly used to isolate adjacent word lines 14, and isolate the word line 14 and other stacked film layers located on the second isolation layer 15, and other stacked film layers include but are not limited to drain contacts 18.

[0022] It can be understood that the material of the first isolation layer 13 and the material of the second isolation layer 15 can be the same or different; at the same time, the second isolation layer 15 can be composed of a first part and a second part, the first part is arranged between adjacent word lines 14, and the second part is arranged between the word lines 14 and other stacked film layers. The material of the first part and the material of the second part can be the same or different, for example, the dielectric constant of the material of the first part is smaller than the dielectric constant of the material of the second part, the first part is mainly used to suppress signal crosstalk, and the second part is mainly used to prevent short circuit.

[0023] In addition, the gate dielectric layer 16 and the oxide semiconductor layer 17 sequentially penetrate the second isolation layer 15, the word line 14, and the first isolation layer 13. The bottoms of the gate dielectric layer 16 and the oxide semiconductor layer 17 are in direct contact with the surface of the source plate 12. In a direction perpendicular to the surface of the source plate 12, the thickness of the gate dielectric layer 16 and the oxide semiconductor layer 17 is equal to the sum of the thicknesses of the first isolation layer 13, the word line 14, and the second isolation layer 15. The thickness of the gate dielectric layer 16 is greater than the thickness of the channel and the thickness of the word line 14. The thickness of the word line 14 is equal to the thickness of the channel. In addition, in a direction perpendicular to the surface of the source plate 12, the thickness of the first isolation layer 13 is equal to the thickness of the second isolation layer 15.

[0024] refer to Figure 2 The transistors are arranged in a staggered array, with multiple word lines 14 extending along a first direction D1. Each word line 14 is connected to two adjacent rows of transistors. An odd number of transistors greater than 1 share a common drain contact 18. Transistors sharing the same drain contact 18 are driven by the same word line 14. Transistors sharing the same drain contact 18 are located in different rows of the transistor array, with the rows extending in the first direction D1.

[0025] The transistor array can be considered to be composed of different rows extending along the first direction D1 and arranged along the second direction D2. The first direction D1 is perpendicular to the second direction D2. The transistors in adjacent rows are staggered in the first direction D1. The transistors in different rows that are separated by one row overlap in the first direction D1. The spacing between adjacent rows in the second direction D2 is equal. The spacing between adjacent crystals in the same row can be equal to the spacing between adjacent rows in the second direction D2.

[0026] When transistors sharing the same drain contact 18 are located in different rows of the transistor array, they need to be driven by the same driving signal. Therefore, the word lines 14 used to drive the transistors in different rows can be connected to each other. Figure 2 A form of interconnection. In some embodiments, the width of each word line 14 in the second direction D2 is greater than the spacing between transistors in different rows in the second direction D2, and each word line 14 surrounds the channels of all transistors it drives. In other embodiments, each word line drives a row of transistors, and the width of each word line in the second direction is greater than the outer diameter of the gate dielectric layer. Two adjacent word lines are connected outside the transistor array to share the same drive signal. Compared to turning on transistors in different rows with two drive signals with the same parameters, turning on transistors in different rows with the same drive signal helps avoid differences in transistor turn-on time caused by differences in signal timing. In other words, it helps ensure that transistors in different rows are turned on at the same time, thereby achieving effective storage of data signals through large drive currents.

[0027] In some embodiments, the combination of any two adjacent drain contacts 18 on the transistors connected to the same word line 14 is a parallelogram. The shape of a single drain contact 18 can be a triangle or a trapezoid. Figure 3 , three adjacent transistors share the same drain contact 18, and the drain contact 18 is triangular; Figure 4 The five transistors share the same drain contact 18, which is trapezoidal in shape. It should be noted that the drain contact 18 may cover the entire top surface of the drain of the corresponding transistor, or may cover a portion of the top surface of the drain of the corresponding transistor.

[0028] In some embodiments, transistors sharing the same drain contact 18 are located in two adjacent rows of the transistor array. In other embodiments, transistors sharing the same drain contact are located in the same row of the transistor array, or in two alternate rows of the transistor array, or in n consecutive rows of the transistor array, where n is a natural number greater than 2, or in n discontinuous rows of the transistor array. In other words, which transistors share the same drain contact 18 can be determined based on actual needs, and the shape of the drain contact 18 can be adjusted based on actual needs, and different drain contacts 18 can have different shapes.

[0029] In some embodiments, the plurality of drain contacts 18 are arranged in an array. Figure 3 and Figure 4 , the shape of the drain contact 18 includes a triangle and a trapezoid; in other embodiments, reference Figure 2 The drain contact 18 is circular in shape, and the centers of different drain contacts 18 electrically connected to the same word line 14 are located on a straight line or two straight lines parallel to the first direction D1. By adjusting the center position of the drain contact 18, the drain contact 18 can cover a larger top surface area of ​​the corresponding transistor drain, thereby reducing contact resistance and increasing drive current.

[0030] In some embodiments, the semiconductor structure further includes: a plurality of bit lines 21 arranged in sequence, wherein the extending direction of the bit lines 21 is perpendicular to the extending direction of the word lines 14, and the bit lines 21 connect all magnetic tunnel junctions 20 in the extending direction thereof, and the bit lines 21 are located above the magnetic tunnel junctions 20. By arranging the bit lines 21 above the magnetic tunnel junctions 20, it is advantageous to prevent the cross-sectional dimensions of the bit lines 21 from being restricted by other structures on the same plane, thereby ensuring that the bit lines 21 have a relatively wide dimension in the arrangement direction and a relatively large cross-sectional area in the extending direction thereof, thereby ensuring that the bit lines 21 have a relatively low transmission resistance and a relatively good signal transmission performance.

[0031] In the above embodiment, the semiconductor structure uses oxide semiconductor as the channel material of the transistor. The transistor prepared based on oxide semiconductor has a higher switching current ratio, which is beneficial to improving the switching characteristics of the transistor; in addition, the drain contact can be connected to multiple transistors at the same time. This is beneficial to driving the magnetic tunnel junction through a large driving current without increasing the driving current of a single transistor, thereby realizing effective data storage.

[0032] The present application also provides a memory device comprising any of the aforementioned semiconductor structures. A memory device fabricated based on the aforementioned semiconductor structure has low drive voltage requirements and low inherent losses, thereby reducing heat generation during operation of electronic devices, lowering cooling costs, and improving the competitiveness of electronic devices.

[0033] Figures 5 to 12 The present invention provides a schematic diagram of the structure of each step of the method for manufacturing a semiconductor structure. Figures 5 to 12 The method for manufacturing a semiconductor structure provided in an embodiment of the present application includes the following steps:

[0034] refer to Figure 5 , providing a substrate 11, a source plate 12, a first isolation layer 13 and a conductive layer 14a stacked in sequence.

[0035] The substrate 11 can be either a supporting material for supporting the formation of subsequent film layers, or a base for all formed film layers. The substrate 11 is used as an illustration only. If the substrate 11 only plays a supporting role, the substrate 11 can be removed after the target structure is formed, or the substrate 11 is not formed; the source plate 12 can serve as the source of the subsequently formed transistor, or provide a source signal for the subsequently formed transistor. The material of the source plate 12 is a conductive material, such as at least one of doped polysilicon, indium tin oxide (ITO), metal molybdenum, metal aluminum, metal titanium or metal copper; the first isolation layer 13 is used to isolate the source plate 12 and the conductive layer 14a; the conductive layer 14a is used to prepare word lines.

[0036] refer to Figure 6 , etch the conductive layer 14a (refer to Figure 5 ), forming word line 14.

[0037] In some embodiments, word lines 14 extend in a first direction D1, and are arranged in a second direction D2 perpendicular to first direction D1. The width d of word lines 14 in second direction D2 is related to the position and size of the transistors driven by word lines 14. For ease of understanding, the relationship between width d and the position and size of transistors will be explained in conjunction with the accompanying drawings after the transistors are formed. It is understood that before forming word lines 14, the positions of the multiple transistors arranged in an interlaced manner must be determined.

[0038] In some embodiments, as the size of the semiconductor structure shrinks, the spacing between adjacent word lines 14 becomes smaller, and conventional processes cannot form such an opening mask. In this case, the word lines 14 can be formed by a reverse self-aligned double imaging process. The specific steps are as follows: Figure 7 First, a first mask 15a is formed on the conductive layer 14a. The first mask 15a is composed of a plurality of strip structures arranged in sequence. The spacing between adjacent strip structures is equal to the spacing between two spaced-apart word lines. A sacrificial layer 16a is formed. The sacrificial layer 16a covers the top surface and sidewalls of the first mask 15a and the surface of the conductive layer 14a. The thickness of the sacrificial layer 16a is equal to the spacing between adjacent word lines. The sacrificial layer 16a can be formed by an atomic layer deposition process to precisely control the thickness of the sacrificial layer 16a. A second mask 17a is formed. The second mask 17a completely fills the grooves formed by the sacrificial layer 16a. The material of the second mask 17a can be the same as that of the first mask 17a. Figure 8 , the sacrificial layer 16a is etched to expose the top surface of the conductive layer 14a. At this time, the mask layer composed of the first mask 15a, the remaining sacrificial layer 16a and the second mask 16a has a smaller opening spacing. The conductive layer 14 is etched using the opening spacing to form adjacent word lines 14 with a smaller spacing.

[0039] In other embodiments, before forming the second mask 17a, the sacrificial layer 16a may be subjected to a maskless dry etching process, retaining only the sacrificial layer 16a covering the sidewalls of the first mask 15a and removing the sacrificial layer 16a at other locations. It is understood that, regardless of the method used, the core of the inverse self-aligned dual imaging process lies in forming a sacrificial layer using a deposition process, with the thickness of the sacrificial layer being the same as the target opening spacing, and subsequently removing the corresponding sacrificial layer by etching to form the corresponding mask opening.

[0040] refer to Figure 9 , forming a second isolation layer 15.

[0041] The top surface of the second isolation layer 15 is higher than the top surface of the word line 14. The second isolation layer 15 fills between adjacent word lines 14 and covers the top surface of the word line 14. The material of the first isolation layer 13 and the material of the second isolation layer 15 can be the same or different. At the same time, the second isolation layer 15 can be composed of a first part and a second part. The first part is arranged between adjacent word lines 14, and the second part is arranged between the word line 14 and other stacked film layers. The material of the first part and the material of the second part can be the same or different. For example, the dielectric constant of the material of the first part is smaller than the dielectric constant of the material of the second part. The first part is mainly used to suppress signal crosstalk, and the second part is mainly used to prevent short circuit.

[0042] refer to Figure 10 , forming a gate dielectric layer 16 and an oxide semiconductor layer 17.

[0043] In some embodiments, the gate dielectric layer 16 and the oxide semiconductor layer 17 sequentially penetrate the second isolation layer 15, the word line 14, and the first isolation layer 13. The bottoms of the gate dielectric layer 16 and the oxide semiconductor layer 17 are in direct contact with the surface of the source plate 12. The word line 14 surrounds a portion of the thickness of the oxide semiconductor layer 17 and covers a portion of the sidewall of the gate dielectric layer 16. The word line 14, the gate dielectric layer 16, and the oxide semiconductor layer 17 constitute a transistor. The portion of the oxide semiconductor layer 17 surrounded by the word line 14 serves as the channel of the transistor, the portion of the oxide semiconductor layer 17 located between the channel and the source plate 12 serves as the source of the transistor, and another portion of the oxide semiconductor layer 17 located on the other side of the channel away from the source plate 12 serves as the drain of the transistor.

[0044] The above-mentioned gate dielectric layer 16 and oxide semiconductor layer 17 can be formed by the following process steps: performing patterned etching to form an opening that sequentially passes through the second isolation layer 15, the word line 14 and the first isolation layer 13; performing a deposition process to form a gate dielectric layer 16 covering the surface of the sidewall of the opening, and the portion of the gate dielectric layer 16 covering the surface of the source plate 12 and the surface of the second isolation layer 15 can be removed by a maskless dry etching process; performing another deposition process to form the oxide semiconductor layer 17 that fills the opening.

[0045] In other embodiments, the gate dielectric layer only surrounds the transistor channel but does not surround the transistor source and drain, and the process steps for forming the transistor include: performing patterned etching to form an opening that sequentially passes through the second isolation layer, the word line, and the first isolation layer; forming a first oxide semiconductor layer filling the opening, the bottom surface of the first oxide semiconductor layer is in direct contact with the source plate, and the top surface of the first oxide semiconductor layer is flush with the bottom surface of the word line; forming a gate dielectric film, the gate dielectric film covers the side walls and bottom surface of the opening, and covers the top surface of the second isolation layer; removing the gate dielectric film covering the bottom surface of the opening and the top surface of the word line, and the remaining gate dielectric film serves as the gate dielectric layer; forming a second oxide semiconductor layer filling the opening, the second oxide semiconductor layer and the first oxide semiconductor layer together constitute an oxide semiconductor layer.

[0046] In some embodiments, transistors are arranged in a staggered array. The transistor array can be considered to be composed of different rows extending along a first direction D1 and arranged along a second direction D2. The first direction D1 is perpendicular to the second direction D2. Adjacent rows of transistors are staggered in the first direction D1, and transistors in alternate rows overlap in the first direction D1. Multiple word lines 14 extend along the first direction D1, with each word line 14 connected to two adjacent rows of transistors. If each word line 14 is required to connect to two adjacent rows of transistors, the width d of each word line 14 in the second direction D2 must be at least greater than the pitch between the transistors in the adjacent rows. If each word line 14 is required to surround the channel of the corresponding transistor, the width d of each word line 14 must be at least greater than the sum of the pitch between the transistors in the adjacent rows and twice the outer diameter of the gate dielectric layer 16.

[0047] refer to Figure 11 , forming a drain contact 18 .

[0048] In some embodiments, the drain contact 18 is circular in shape, and three adjacent triangular transistors share the same drain contact 18, which serves as a storage node for the semiconductor structure. In other embodiments, the drain contact 18 can have other shapes, such as triangles or trapezoids, and the number of transistors sharing the same drain contact 18 can be an odd number, such as five or seven. Furthermore, in some embodiments, transistors sharing the same drain contact 18 are driven by the same word line 14, or by different word lines 14 that share the same drive signal. It should be noted that different drive signals with the same parameters do not constitute the "same drive signal" described above.

[0049] In some embodiments, the material of the drain contact 18 includes a conductive material such as tungsten. When setting the material of the drain contact 18, it is necessary to consider the contact area between the drain contact 18 and the transistor drain and the material of the transistor drain, so that there is a smaller contact resistance between the drain contact 18 and the transistor drain, thereby ensuring that the driving current flowing through the drain contact 18 is larger, so as to effectively realize data storage.

[0050] refer to Figure 12 , forming a third isolation layer 19 and a magnetic tunnel junction 20.

[0051] A third isolation layer 19 is disposed between adjacent drain contacts 18 to isolate adjacent drain contacts 18. A magnetic tunnel junction 20 is located on the drain contact 18 to implement data storage. The magnetic tunnel junction 20 is electrically connected to the drain contact 18 in a one-to-one correspondence. For example, the shapes of the magnetic tunnel junction 20 and the drain contact 18 may be the same or different. In a direction perpendicular to the surface of the source plate 12, the center of the magnetic tunnel junction 20 and the center of the drain contact 18 may overlap or be offset.

[0052] Exemplarily, in a direction perpendicular to the surface of the source plate 12, the magnetic tunnel junction 20 includes a fixed layer, a tunnel junction and a free layer in sequence, the fixed layer covers the surface of the drain contact 18, the fixed layer and the free layer are formed of ferromagnetic materials with in-plane magnetic anisotropy or perpendicular magnetic anisotropy, and the magnetic orientation of the fixed layer remains fixed. When the magnetic orientations of the free layer and the fixed layer are antiparallel to each other (AP), the first state (for example, logic "1") is stored, and when the magnetic orientations of the free layer and the fixed layer are parallel to each other (P), the second state (for example, logic "0") is stored. The magnetic orientation relationship between the free layer and the fixed layer can be judged by sensing the resistance when the current flows through the magnetic tunnel junction 20, thereby realizing data reading; accordingly, the transistor can be turned on by activating the word line 14 to generate a write current (that is, the above-mentioned drive current) flowing through the magnetic tunnel junction 20, and the write current can adjust the magnetic orientation of the free layer to realize data storage.

[0053] refer to Figure 1 , forming a bit line 21.

[0054] The bit line 21 extends in a direction perpendicular to the direction of extension of the word line 14, and is arranged in a direction perpendicular to the arrangement of the word line 14. The bit line 21 is located above the magnetic tunnel junction 20. Positioning the bit line 21 above the magnetic tunnel junction 20 helps prevent the size of the bit line 21 from being restricted by other functional structures on the same plane, ensuring that the bit line 21 has a relatively wide dimension in its arrangement direction and a large cross-sectional area in its extension direction, thereby ensuring that the bit line 21 has good signal transmission performance.

[0055] It is understandable that before forming the bit line 21 , a fourth isolation layer (not shown) may be further provided. The fourth isolation layer is provided between adjacent magnetic tunnel junctions 20 to isolate adjacent magnetic tunnel junctions 20 and to support the bit line 21 .

[0056] In the above embodiment, the semiconductor structure uses oxide semiconductor as the channel material of the transistor. The transistor prepared based on oxide semiconductor has a higher switching current ratio, which is beneficial to improving the switching characteristics of the transistor; in addition, the drain contact can be connected to multiple transistors at the same time. This is beneficial to driving the magnetic tunnel junction through a large driving current without increasing the driving current of a single transistor, thereby realizing effective data storage.

[0057] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present application, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present application. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that include: A plurality of staggered transistors, the transistors sharing a common source plate, the channels of the transistors being located on the source plate and having a length direction perpendicular to a surface of the source plate, wherein the material of the channels comprises an oxide semiconductor; a plurality of drain contacts electrically connected to the drains of the transistors, an odd number of the transistors sharing the same drain contact, the transistors sharing the same drain contact being driven by the same word line, the plurality of word lines extending along a first direction, each word line being connected to two adjacent rows of transistors, the combination of any two adjacent drain contacts on the transistors connected to the same word line forming a parallelogram, and three transistors sharing the same drain contact forming a triangle; A plurality of magnetic tunnel junctions are located on the drain contact, and the magnetic tunnel junctions are electrically connected to the drain contact in a one-to-one correspondence.

2. The semiconductor structure according to claim 1, wherein: The oxide semiconductor includes indium gallium zinc oxide.

3. The semiconductor structure according to claim 2, wherein: The transistor further includes a gate dielectric layer, which is located between the word line and the channel and surrounds the channel. The material of the gate dielectric layer includes at least one of HfO 2 , ZrO 2 or HfON.

4. The semiconductor structure according to claim 3, wherein: In a direction perpendicular to a surface of the source plate, the thickness of the gate dielectric layer is greater than the thickness of the channel and the thickness of the word line.

5. The semiconductor structure according to claim 3, wherein: The bottom of the gate dielectric layer is in direct contact with the surface of the source plate. The semiconductor structure according to claim 1 , wherein: The transistors are arranged in a staggered array.

7. The semiconductor structure according to claim 6, wherein: The word lines are arranged along a second direction perpendicular to the first direction. The width of each word line in the second direction is greater than the width of adjacent transistors in the second direction. Each word line surrounds channels of all the transistors it drives.

8. The semiconductor structure according to claim 1, wherein: The five transistors share the same drain contact, and the drain contact is trapezoidal.

9. The semiconductor structure according to claim 1, wherein: The material of the source plate includes at least one of indium tin oxide, molybdenum, aluminum, titanium or copper.

10. The semiconductor structure according to claim 1, wherein: Also includes: A plurality of bit lines are arranged in sequence, wherein an extending direction of the bit lines is perpendicular to an extending direction of the word lines, the bit lines connect all the magnetic tunnel junctions in the extending direction, and the bit lines are located above the magnetic tunnel junctions.

11. The semiconductor structure according to claim 1, wherein: The word lines are formed by an inverse self-aligned double patterning process.

12. A memory, characterized in that: A semiconductor structure comprising the semiconductor structure according to any one of claims 1 to 11.

13. A method for manufacturing a semiconductor structure according to claim 1, characterized in that: include: forming a plurality of staggered transistors, wherein the transistors share a common source plate, the channels of the transistors being located on the source plate and the length direction of the channels of the transistors being perpendicular to the surface of the source plate, wherein the material of the channels comprises an oxide semiconductor; forming a plurality of drain contacts electrically connected to the drains of the transistors, wherein an odd number of the transistors share the same drain contact, and the transistors sharing the same drain contact are driven by the same word line; A plurality of magnetic tunnel junctions are formed on the drain contacts, and the magnetic tunnel junctions are electrically connected to the drain contacts in a one-to-one correspondence.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein: The process steps for forming the transistor include: forming a first isolation layer and a conductive layer stacked in sequence on the source plate; Etching the conductive layer to form a plurality of word lines arranged in sequence; forming a second isolation layer, wherein the second isolation layer is filled between adjacent word lines and covers top surfaces of the word lines; etching the second isolation layer, the conductive layer, and the first isolation layer in sequence to form a via hole exposing the source plate; forming a gate dielectric layer, wherein the gate dielectric layer covers the sidewalls of the via hole; The oxide semiconductor is deposited to fill the via hole, the portion of the oxide semiconductor surrounded by the word line serves as a channel, the oxide semiconductor located between the channel and the source plate serves as a source, and the oxide semiconductor located on a side of the channel away from the source plate serves as a drain.

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