Method of manufacturing a capacitor and capacitor

Abstract

The present invention provides a method for manufacturing a capacitor and a capacitor, comprising: providing a substrate, a sacrificial layer being present on the surface of the substrate, an inverted trapezoidal capacitor via hole existing in the sacrificial layer, the substrate including a contact pad, the contact pad being located below the inverted trapezoidal capacitor via hole; forming a lower electrode on the surface of the sacrificial layer, the lower electrode covering the surface of the inverted trapezoidal capacitor via hole of the sacrificial layer; removing the sacrificial layer to expose the lower electrode; forming a dielectric layer, the dielectric layer being formed on the surface of the lower electrode and covering the lower electrode; forming an upper electrode, the upper electrode covering the dielectric layer. The present invention adopts a structure combining a columnar shape and a cylindrical shape, and increases the contact area of the electrode plate through the concave hole structure at the top, thereby improving the capacitance value of the capacitor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a method for manufacturing a capacitor and a capacitor. Background Art

[0002] With the miniaturization of semiconductor sizes, the storage capacity per unit area is increasing. In the prior art, the traditional method is to use a capacitor with a cylindrical or columnar structure. However, it is difficult for the traditional capacitor structure to achieve a higher capacitance value while using traditional dielectrics. Therefore, changing the structure of the capacitor in the prior art and increasing the contact area of the electrode plates is an important direction for technological innovation. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to increase the contact area of the electrode plates and improve the capacitance value of the capacitor, and to provide a method for manufacturing a capacitor and a capacitor.

[0004] To solve the above problems, the present invention provides a method for manufacturing a capacitor, including: providing a substrate, the surface of the substrate has a sacrificial layer, the sacrificial layer has an inverted trapezoidal capacitor via hole, the substrate includes a contact pad, and the contact pad is located below the inverted trapezoidal capacitor via hole; forming a lower electrode on the surface of the sacrificial layer, the lower electrode covering the surface of the inverted trapezoidal capacitor via hole of the sacrificial layer; removing the sacrificial layer to expose the lower electrode; forming a dielectric layer, the dielectric layer being formed on the surface of the lower electrode and coating the lower electrode; forming an upper electrode, the upper electrode covering the dielectric layer.

[0005] Optionally, the method for manufacturing the capacitor includes: the upper electrode fills the void left by removing the sacrificial layer.

[0006] Optionally, in the method for manufacturing the capacitor, the formation of the lower electrode further includes: depositing a first lower electrode layer on the surface of the sacrificial layer, the first lower electrode layer filling the inverted trapezoidal capacitor via hole; etching the first lower electrode layer to a predetermined height; depositing a second lower electrode layer on the first lower electrode layer, the second lower electrode layer coating the exposed sacrificial layer of the inverted trapezoidal capacitor via hole; etching the top of the second lower electrode layer so that the height of the second lower electrode layer is flush with the sacrificial layer, forming an inverted trapezoidal lower electrode with a concave hole at the top.

[0007] Optionally, in the method for manufacturing the capacitor, the sacrificial layer is made of one or more of silicon oxide, silicon oxynitride, organic carbon, and organic silicon materials.

[0008] Optionally, in the method for manufacturing the capacitor, the substrate is made of one or more of SiN, SiCN, and SION materials.

[0009] Optionally, in the method for manufacturing the capacitor, the contact pad is made of a metal material.

[0010] Optionally, in the method for manufacturing the capacitor, the first lower electrode layer, the second lower electrode layer, and the lower electrode are each made of one or more of Ti, TiN, doped polysilicon, SiGe, and metal W materials.

[0011] Optionally, in the method for manufacturing the capacitor, the dielectric layer is made of one or more of ZrO, Al2O3, and HfO materials.

[0012] Optionally, in the method for manufacturing the capacitor, the upper electrode is made of one or more of Ti, TiN, doped polysilicon, SiGe, and metal W materials.

[0013] To solve the above problems, the present invention provides a capacitor, comprising: a lower electrode having an inverted trapezoidal structure with a concave hole at the top; a dielectric layer wrapped around the surface of the lower electrode; and an upper electrode covering the dielectric layer.

[0014] Optionally, in the capacitor, the upper electrode fills the voids around the dielectric layer.

[0015] Optionally, in the capacitor, there is a substrate below the lower electrode, and the substrate includes a contact pad that forms an electrical connection with the lower electrode.

[0016] Optionally, in the capacitor, the substrate is made of one or more of SiN, SiCN, and SiON materials.

[0017] Optionally, in the capacitor, the contact pad is made of a metal material.

[0018] Optionally, in the capacitor, the lower electrode is made of one or more of Ti, TiN, doped polysilicon, SiGe, and metal W materials.

[0019] Optionally, in the capacitor, the dielectric layer is made of one or more of ZrO, Al2O3, and HfO materials.

[0020] Optionally, in the capacitor, the upper electrode is made of one or more of Ti, TiN, doped polysilicon, SiGe, and metal W materials.

[0021] The present invention adopts a structure combining columns and cylinders, and increases the contact area of the electrode plates through the concave hole structure at the top, thereby improving the capacitance value of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Attached Figure 1 Shows a schematic diagram of the steps of the method for manufacturing the capacitor according to a specific embodiment of the present invention.

[0023] Attached Figures 2A - 2H The figure shows a process schematic diagram of the manufacturing method of the capacitor according to a specific embodiment of the present invention.

[0024] Attached Figure 3 The figure shows a step schematic diagram of the formation of the lower electrode according to a specific embodiment of the present invention.

[0025] Attached Figures 4A - 4H The figure shows a process schematic diagram of the manufacturing method of the capacitor according to a specific embodiment of the present invention.

[0026] Attached Figures 5A - 5C The figure shows a cross-sectional structure schematic diagram of the capacitor according to a specific embodiment of the present invention.

[0027] Attached Figures 6A - 6C The figure shows a cross-sectional structure schematic diagram of the capacitor according to a specific embodiment of the present invention.

[0028] Attached Figures 7A - 7C The figure shows a cross-sectional structure schematic diagram of the capacitor according to a specific embodiment of the present invention.

[0029] Attached Figures 8A - 8C The figure shows a cross-sectional structure schematic diagram of the capacitor according to a specific embodiment of the present invention. Specific Embodiment

[0030] The following is a detailed description of the specific embodiment of a manufacturing method of a capacitor provided by the present invention with reference to the accompanying drawings.

[0031] Attached Figure 1 The figure shows a step schematic diagram of the manufacturing method of the capacitor according to a specific embodiment of the present invention, including: Step S10, providing a substrate, the surface of the substrate has a sacrificial layer, the sacrificial layer has an inverted trapezoidal capacitor through hole, the substrate includes a contact pad, and the contact pad is located below the inverted trapezoidal capacitor through hole; Step S11, forming a lower electrode on the surface of the sacrificial layer, the lower electrode covering the surface of the inverted trapezoidal capacitor through hole of the sacrificial layer; Step S12, removing the sacrificial layer to expose the lower electrode; Step S13, forming a dielectric layer, the dielectric layer being formed on the surface of the lower electrode and covering the lower electrode; Step S14, forming an upper electrode, the upper electrode covering the dielectric layer.

[0032] As shown in Step 2A, referring to Step S10, a substrate 21 is provided. The surface of the substrate 21 has a sacrificial layer 23. There are inverted trapezoidal capacitive vias 24 in the sacrificial layer 23. The substrate 21 includes contact pads 22, and the contact pads 22 are located below the inverted trapezoidal capacitive vias 24. In a specific embodiment of the present invention, the substrate 21 is made of one or more of SiN, SiCN, and SiON materials; the contact pads 22 are made of a metal material. The capacitive vias are used to form a lower electrode, a dielectric layer, and a part of the upper electrode in subsequent steps; the contact pads 22 are electrically connected to the subsequent lower electrode.

[0033] In Step S11, a lower electrode is formed on the surface of the sacrificial layer, and the lower electrode covers the surface of the inverted trapezoidal capacitive vias of the sacrificial layer. Attached Figure 3 The figure shows a schematic diagram of the steps for forming the lower electrode according to a specific embodiment of the present invention. The formation of the lower electrode further includes: Step S31, depositing a first lower electrode layer on the surface of the sacrificial layer, and the first lower electrode layer fills the inverted trapezoidal capacitive vias; Step S32, etching the first lower electrode layer to a predetermined height; Step S33, depositing a second lower electrode layer on the first lower electrode layer, and the second lower electrode layer covers the sacrificial layer exposed by the inverted trapezoidal capacitive vias; Step S34, etching the top of the second lower electrode layer to make the height of the second lower electrode layer flush with the sacrificial layer, forming an inverted trapezoidal lower electrode with a concave hole at the top.

[0034] As shown in Step 2B, referring to Step S31, a first lower electrode layer 25 is deposited on the surface of the sacrificial layer 23, and the first lower electrode layer 25 fills the inverted trapezoidal capacitive vias 24. In a specific embodiment of the present invention, the first lower electrode layer 25 is made of one or more of Ti, TiN, doped polysilicon, SiGe, and metal W materials. The height of the first lower electrode layer 25 protrudes from the sacrificial layer 23.

[0035] As shown in Step 2C, referring to Step S32, the first lower electrode layer 25 is etched to a predetermined height. Due to the limitations of the etching method, the etched area of the first lower electrode layer 25 is usually thinner, and subsequent electrode deposition is still required. In a specific embodiment of the present invention, wet etching is used to etch the first lower electrode layer 25.

[0036] As shown in step 2D, referring to step S33, a second lower electrode layer 26 is deposited on the first lower electrode layer 25. The second lower electrode layer 26 covers the sacrificial layer exposed by the inverted trapezoidal capacitor through hole. In a specific embodiment of the present invention, the second lower electrode layer 26 is deposited using the same material as the first lower electrode layer 25, and is selected from one or more of Ti, TiN, doped polysilicon, SiGe, and metal W materials. The height of the deposited second lower electrode layer 26 protrudes above the sacrificial layer 23.

[0037] As shown in step 2E, referring to step S34, the top of the second lower electrode layer 26 is etched so that the height of the second lower electrode layer 26 is flush with the sacrificial layer 23, forming an inverted trapezoidal lower electrode 27 with a concave hole at the top. The lower electrode 27 is electrically connected to the contact pad 22. In a specific embodiment of the present invention, the lower electrode layer 27 is made of one or more of Ti, TiN, doped polysilicon, SiGe, and metal W materials.

[0038] After the above steps are completed, the step of forming the lower electrode on the surface of the sacrificial layer is completed. Continue with the following steps to complete the manufacture of the capacitor.

[0039] As shown in step 2F, referring to step S12, the sacrificial layer 23 is removed, exposing the lower electrode 27. The lower electrode 23 is removed by wet etching. After removal, the substrate 21 and the discrete lower electrodes 27 located on the surface of the substrate 21 are obtained.

[0040] As shown in step 2G, referring to step S13, a dielectric layer 28 is formed. The dielectric layer 28 is formed on the surface of the lower electrode 27 and covers the lower electrode 27. In a specific embodiment of the present invention, the dielectric layer is made of one or more of ZrO, Al2O3, and HFO materials.

[0041] As shown in step 2H, referring to step S14, an upper electrode 29 is formed. The upper electrode 29 covers the dielectric layer 28. The upper electrode 29 fills the void left by removing the sacrificial layer. In a specific embodiment of the present invention, the upper electrode layer 29 is made of one or more of Ti, TiN, doped polysilicon, SiGe, and metal W materials. In a specific embodiment of the present invention, the upper electrode 29 fills the capacitor through hole 24 and remains horizontal. In other specific embodiments of the present invention, the upper electrode 29 may be other irregular shapes covering the dielectric layer 28, or may not fill the capacitor through hole 24.

[0042] Appendix Figure 2HThe following is a schematic structural diagram of a capacitor according to a specific embodiment of the present invention obtained after the above steps are implemented, including: a lower electrode 27, the lower electrode 27 being an inverted trapezoidal structure with a concave hole at the top; a dielectric layer 28, the dielectric layer 28 being wrapped on the surface of the lower electrode 27; and an upper electrode 29, the upper electrode 29 covering the dielectric layer 28.

[0043] In a specific embodiment of the present invention, the upper electrode 29 fills the voids around the dielectric layer 28. In other specific embodiments of the present invention, the upper electrode 29 may be other irregular shapes that fill the voids around the dielectric layer 28, or may not fill the capacitor through hole 24. There is a substrate 21 below the lower electrode 29, and the substrate 21 includes a contact pad 22, and the contact pad 22 forms an electrical connection with the lower electrode 27.

[0044] In a specific embodiment of the present invention, the substrate 21 is made of one or more of SiN, SiCN, and SiON materials. In a specific embodiment of the present invention, the contact pad 22 is made of a metal material. The lower electrode 27 is made of one or more of Ti, TiN, doped polysilicon, SiGe, and metal W materials. The dielectric layer 28 is made of one or more of ZrO, Al2O3, and HFO materials. The upper electrode 29 is made of one or more of Ti, TiN, doped polysilicon, SiGe, and metal W materials.

[0045] The following will give a detailed description of the specific embodiments of a method for manufacturing a capacitor provided by the present invention with reference to the accompanying drawings. Figures 4A - 4H The following is a process schematic diagram of a method for manufacturing a capacitor according to a specific embodiment of the present invention.

[0046] Figure 1 The following is a schematic diagram of the steps of a method for manufacturing a capacitor according to a specific embodiment of the present invention, including: Step S10, providing a substrate, the surface of the substrate having a sacrificial layer, the sacrificial layer having an inverted trapezoidal capacitor through hole, the substrate including a contact pad, and the contact pad being located below the inverted trapezoidal capacitor through hole; Step S11, forming a lower electrode on the surface of the sacrificial layer, the lower electrode covering the surface of the inverted trapezoidal capacitor through hole of the sacrificial layer; Step S12, removing the sacrificial layer to expose the lower electrode; Step S13, forming a dielectric layer, the dielectric layer being formed on the surface of the lower electrode and wrapping the lower electrode; Step S14, forming an upper electrode, the upper electrode covering the dielectric layer.

[0047] ​As shown in step 4A, referring to step S10, a substrate 41 is provided, the surface of the substrate 41 has a sacrificial layer 43, the sacrificial layer 43 has an inverted trapezoidal capacitor through hole 44, and the substrate 41 includes a contact pad 42, and the contact pad 42 is located below the inverted trapezoidal capacitor through hole 44. In a specific embodiment of the present invention, the substrate 41 is made of one or more of SiN, SiCN, and SiON materials; the contact pad 42 is made of metal material. The capacitor through hole is used to form a lower electrode, a dielectric layer, and a portion of an upper electrode in subsequent steps; the contact pad 42 is electrically connected to the subsequent lower electrode.

[0048] Step S11, forming a lower electrode on the surface of the sacrificial layer, wherein the lower electrode covers the surface of the inverted trapezoidal capacitor through hole of the sacrificial layer. Figure 3 The figure is a schematic diagram of the steps of forming the lower electrode according to a specific embodiment of the present invention, and the formation of the lower electrode further includes: step S31, depositing a first lower electrode layer on the surface of the sacrificial layer, the first lower electrode layer filling the inverted trapezoidal capacitor through hole; step S32, etching the first lower electrode layer to a predetermined height; step S33, depositing a second lower electrode layer on the first lower electrode layer, the second lower electrode layer covering the sacrificial layer exposed by the inverted trapezoidal capacitor through hole; step S34, etching the top of the second lower electrode layer so that the height of the second lower electrode layer is flush with the sacrificial layer, forming an inverted trapezoidal lower electrode with a concave hole on the top.

[0049] As shown in step 4B, referring to step S31, a first lower electrode layer 45 is deposited on the surface of the sacrificial layer 43, and the first lower electrode layer 45 fills the inverted trapezoidal capacitor through hole 44. In a specific embodiment of the present invention, the first lower electrode layer 45 is made of one or more materials selected from Ti, TiN, doped polysilicon, SiGe, and metal W. The height of the first lower electrode layer 45 protrudes from the sacrificial layer 43.

[0050] As shown in step 4C, referring to step S32, the first lower electrode layer 45 is etched to a predetermined height. Due to the limitation of the etching method, the etched area of ​​the first lower electrode layer 45 is usually thinner and requires subsequent electrode deposition. In this specific embodiment, two parallel recesses are etched in each inverted trapezoidal area. In other specific embodiments of the present invention, more than two recesses can be etched to increase the contact area of ​​the electrode plates of the capacitor to achieve the effect of increasing the capacitance value. In a specific embodiment of the present invention, the first lower electrode layer 45 is etched by wet etching.

[0051] As shown in step 4D, referring to step S33, a second lower electrode layer 46 is deposited on the first lower electrode layer 45, and the second lower electrode layer 46 covers the exposed sacrificial layer of the inverted trapezoidal capacitor through hole. In a specific embodiment of the present invention, the second lower electrode layer 46 is deposited using the same material as the first lower electrode layer 45, selected from one or more of Ti, TiN, doped polysilicon, SiGe, and metal W materials. The height of the deposited second lower electrode layer 46 protrudes above the sacrificial layer 43.

[0052] As shown in step 4E, referring to step S34, the top of the second lower electrode layer 46 is etched so that the height of the second lower electrode layer 46 is flush with the sacrificial layer 43, forming an inverted trapezoidal lower electrode 47 with a concave hole on the top. In this specific embodiment, each inverted trapezoidal lower electrode 47 is provided with two parallel concave holes. In other specific embodiments of the present invention, more than two concave holes can also be provided. The lower electrode 47 is electrically connected to the contact pad 42. In a specific embodiment of the present invention, the lower electrode layer 47 is made of one or more materials selected from Ti, TiN, doped polysilicon, SiGe, and metal W.

[0053] After the above steps are completed, the step of forming the lower electrode on the surface of the sacrificial layer is completed. The following steps are continued to complete the manufacturing of the capacitor.

[0054] As shown in step 4F, referring to step S12, the sacrificial layer 43 is removed to expose the lower electrode 47. The lower electrode 43 is removed by wet method, and after the removal, the substrate 41 and the lower electrode 47 located on the surface of the substrate 41 are obtained.

[0055] As shown in step 4G, referring to step S13, a dielectric layer 48 is formed, and the dielectric layer 48 is formed on the surface of the lower electrode 47 and covers the lower electrode 47. In a specific embodiment of the present invention, the dielectric layer is made of one or more materials selected from ZrO, Al2O3, and HFO.

[0056] As shown in step 4H, referring to step S14, an upper electrode 49 is formed, and the upper electrode 49 covers the dielectric layer 48. The upper electrode 49 fills the gap left by removing the sacrificial layer. In one embodiment of the present invention, the upper electrode layer 49 is made of one or more materials of Ti, TiN, doped polysilicon, SiGe, and metal W. In one embodiment of the present invention, the upper electrode 49 fills the capacitor through hole 44 and remains horizontal. In other embodiments of the present invention, the upper electrode 49 can be other irregular shapes covering the dielectric layer 48, and may not fill the capacitor through hole 44.

[0057] Attached Figure 4HThe figure is a schematic diagram of the structure of the capacitor of a specific embodiment of the present invention obtained after the above steps are implemented, including: a lower electrode 47, the lower electrode 47 is an inverted trapezoidal structure with a concave hole on the top; a dielectric layer 48, the dielectric layer 48 is wrapped on the surface of the lower electrode 47; and an upper electrode 49, the upper electrode 49 covers the dielectric layer 48. In this specific embodiment, the lower electrode 47 is an inverted trapezoidal structure with two parallel concave holes on the top. In other specific embodiments of the present invention, the number of concave holes on the top of the lower electrode 47 can be increased to multiple, so as to increase the contact area of ​​the electrode plate and improve the capacitance.

[0058] In one embodiment of the present invention, the upper electrode 49 fills the gap around the dielectric layer 48. In other embodiments of the present invention, the upper electrode 49 may be other irregular shapes that fill the gap around the dielectric layer 48, and may not fill the capacitor through hole 44. There is a substrate 41 below the lower electrode 49, and the substrate 41 includes a contact pad 42, and the contact pad 42 is electrically connected to the lower electrode 47.

[0059] In a specific embodiment of the present invention, the substrate 41 is made of one or more materials of SiN, SiCN, and SiON. In a specific embodiment of the present invention, the contact pad 42 is made of metal material. The lower electrode 47 is made of one or more materials of Ti, TiN, doped polysilicon, SiGe, and metal W. The dielectric layer 48 is made of one or more materials of ZrO, Al2O3, and HFO. The upper electrode 49 is made of one or more materials of Ti, TiN, doped polysilicon, SiGe, and metal W.

[0060] Attached Figures 5A - 5C FIG. 1 is a schematic diagram of the cross-sectional structure of a capacitor according to a specific embodiment of the present invention. Figure 5C As shown, attached Figure 5A Schematic diagram of the cross-sectional structure of the capacitor at the 5A position described in this specific implementation mode; Figure 5B Schematic diagram of the cross-sectional structure of the capacitor at position 5B in this specific implementation. Figure 2H The cross-sectional structure diagram of the capacitor shown in the figure comprises: a lower electrode 27, which is an inverted trapezoidal structure with a concave hole on the top; a dielectric layer 28, which is wrapped around the surface of the lower electrode 27; and an upper electrode 29, which is wrapped around the dielectric layer 28. In this specific embodiment, each of the contact pads 22 is connected to an inverted trapezoidal capacitor structure, and a complete capacitor is formed by arranging one, two, or more of the capacitor structures.

[0061] Attached Figure 5AThe figure shows a schematic diagram of the cross-sectional structure of the capacitor at the 5A position in a specific embodiment of the present invention, wherein the lower electrode 27 shown in the figure is the side wall portion of the top concave hole of the lower electrode 27; the figure shows that a portion of the upper electrode 29 fills the top concave hole of the lower electrode 27, and a portion wraps the lower electrode 27, and the upper electrode 29 is a continuous structure; the figure shows that the dielectric layer 28 wraps around the surface of the lower electrode 27 to separate the lower electrode 27 from the upper electrode 29.

[0062] Attached Figure 5B The figure shows a schematic diagram of the cross-sectional structure of the capacitor at the 5B position in a specific embodiment of the present invention, wherein the lower electrode 27 shown in the figure is the bottom of the inverted trapezoidal structure of the lower electrode 27; the upper electrode 29 shown in the figure is the portion of the lower electrode 29 that wraps the lower electrode 27; the dielectric layer 28 shown in the figure is wrapped around the surface of the lower electrode 27 to separate the lower electrode 27 from the upper electrode 29.

[0063] Attached Figures 6A - 6C FIG. 1 is a schematic diagram of the cross-sectional structure of a capacitor according to a specific embodiment of the present invention. Figure 6C As shown, attached Figure 6A Schematic diagram of the cross-sectional structure of the capacitor at the 6A position in this specific implementation mode; Figure 6B 6B is a schematic diagram of the cross-sectional structure of the capacitor in this specific implementation mode. Figure 4H The cross-sectional structure diagram of the capacitor shown includes: a lower electrode 47, the lower electrode 47 is an inverted trapezoidal structure with a concave hole on the top; a dielectric layer 48, the dielectric layer 48 is wrapped on the surface of the lower electrode 47; an upper electrode 49, the upper electrode 49 covers the dielectric layer 48. In this specific embodiment, each of the contact pads 42 is connected to an inverted trapezoidal capacitor structure, and a complete capacitor is composed of one, two, or more capacitor structures arranged. In this specific embodiment, the lower electrode 47 is an inverted trapezoidal structure with two parallel concave holes on the top. In other specific embodiments of the present invention, the number of concave holes on the top of the lower electrode 47 can also be increased to multiple, so as to increase the electrode area and improve the capacitance.

[0064] Attached Figure 6AThe figure shows a schematic diagram of the cross-sectional structure of the capacitor at the 6A position in a specific embodiment of the present invention. The lower electrode 47 shown in the figure is the side wall portion of the top recessed hole of the lower electrode 47. In the present specific embodiment, the lower electrode 47 is an inverted trapezoidal structure with two parallel recessed holes on the top. In other specific embodiments of the present invention, the number of top recessed holes of the lower electrode 47 can be increased to multiple, so as to increase the contact area of ​​the electrode plate and improve the capacitance. The figure shows that a portion of the upper electrode 49 fills the recessed hole at the top of the lower electrode 47, and a portion wraps the lower electrode 47. The upper electrode 49 is a continuous structure. The figure shows that the dielectric layer 48 wraps the surface of the lower electrode 47 to separate the lower electrode 47 from the upper electrode 49.

[0065] Attached Figure 6B The figure shows a schematic diagram of the cross-sectional structure of the capacitor at position 6B in a specific embodiment of the present invention, wherein the lower electrode 47 shown in the figure is the bottom of the inverted trapezoidal structure of the lower electrode 47; the upper electrode 49 shown in the figure is the portion of the lower electrode 49 that wraps the lower electrode 47; the dielectric layer 48 shown in the figure is wrapped around the surface of the lower electrode 47 to separate the lower electrode 47 from the upper electrode 49.

[0066] Attached Figures 7A - 7C FIG. 1 is a schematic diagram of the cross-sectional structure of a capacitor according to a specific embodiment of the present invention. Figure 7C As shown, attached Figure 7A Schematic diagram of the cross-sectional structure of the capacitor at the 7A position in this specific implementation mode; Figure 7B Schematic diagram of the cross-sectional structure of the capacitor at position 7B in this specific implementation. Figure 2H The cross-sectional structural diagram of the capacitor array arrangement shown includes: a lower electrode 27, the lower electrode 27 is an inverted trapezoidal structure with a concave hole on the top; a dielectric layer 28, the dielectric layer 28 is wrapped on the surface of the lower electrode 27; an upper electrode 29, the upper electrode 29 covers the dielectric layer 28. In this specific embodiment, the lower electrode 47 is an inverted trapezoidal structure with two parallel concave holes on the top. In other specific embodiments of the present invention, the number of concave holes on the top of the lower electrode 47 can also be increased to multiple, so as to increase the electrode area and improve the capacitance. In this specific embodiment, each of the contact pads 22 is connected to an inverted trapezoidal capacitor structure, and a complete capacitor is composed of multiple capacitor structures. In other specific embodiments of the present invention, the array of the capacitor can also be expanded according to needs.

[0067] Attached Figure 7AThe figure shows a schematic diagram of the cross-sectional structure of the capacitor at the 7A position in a specific embodiment of the present invention, wherein the lower electrode 27 shown in the figure is the side wall portion of the top concave hole of the lower electrode 27; the figure shows that a portion of the upper electrode 29 fills the top concave hole of the lower electrode 27, and a portion wraps the lower electrode 27, and the upper electrode 29 is a continuous structure; the figure shows that the dielectric layer 28 wraps around the surface of the lower electrode 27 to separate the lower electrode 27 from the upper electrode 29.

[0068] Attached Figure 7B The figure shows a schematic diagram of the cross-sectional structure of the capacitor at position 7B in a specific embodiment of the present invention, wherein the lower electrode 27 shown in the figure is the bottom of the inverted trapezoidal structure of the lower electrode 27; the upper electrode 29 shown in the figure is the portion of the lower electrode 29 that wraps the lower electrode 27; the dielectric layer 28 shown in the figure is wrapped around the surface of the lower electrode 27 to separate the lower electrode 27 from the upper electrode 29.

[0069] Attached Figures 8A - 8C FIG. 1 is a schematic diagram of the cross-sectional structure of a capacitor according to a specific embodiment of the present invention. Figure 8C As shown, attached Figure 8A Schematic diagram of the cross-sectional structure of the capacitor at the 8A position in this specific implementation mode; Figure 8B 8B is a schematic diagram of the cross-sectional structure of the capacitor in this specific embodiment. Figure 4H The cross-sectional structure diagram of the capacitor array arrangement shown includes: a lower electrode 47, the lower electrode 47 is an inverted trapezoidal structure with a concave hole on the top; a dielectric layer 48, the dielectric layer 48 is wrapped on the surface of the lower electrode 47; an upper electrode 49, the upper electrode 49 covers the dielectric layer 48. In this specific embodiment, each of the contact pads 42 is connected to an inverted trapezoidal capacitor structure, and a complete capacitor is formed by arranging one, two, or more of the capacitor structures. In this specific embodiment, the lower electrode 47 is an inverted trapezoidal structure with two parallel concave holes on the top. In other specific embodiments of the present invention, the number of concave holes on the top of the lower electrode 47 can also be increased to multiple, so as to increase the electrode area and improve the capacitance. In this specific embodiment, each of the contact pads 42 is connected to an inverted trapezoidal capacitor structure, and a complete capacitor is formed by arranging multiple capacitor structures. In other specific embodiments of the present invention, the array of the capacitor can also be expanded according to demand.

[0070] Attached Figure 8AThe figure shows a schematic diagram of the cross-sectional structure of the capacitor at the 8A position in a specific embodiment of the present invention. The lower electrode 47 shown in the figure is the side wall portion of the top recessed hole of the lower electrode 47. In the present specific embodiment, the lower electrode 47 is an inverted trapezoidal structure with two parallel recessed holes on the top. In other specific embodiments of the present invention, the number of top recessed holes of the lower electrode 47 can be increased to multiple, so as to increase the contact area of ​​the electrode plate and improve the capacitance. The figure shows that a portion of the upper electrode 49 fills the recessed hole at the top of the lower electrode 47, and a portion wraps the lower electrode 47. The upper electrode 49 is a continuous structure. The figure shows that the dielectric layer 48 wraps the surface of the lower electrode 47 to separate the lower electrode 47 from the upper electrode 49.

[0071] Attached Figure 8B The figure shows a schematic diagram of the cross-sectional structure of the capacitor at position 8B in a specific embodiment of the present invention, wherein the lower electrode 47 shown in the figure is the bottom of the inverted trapezoidal structure of the lower electrode 47; the upper electrode 49 shown in the figure is the portion of the lower electrode 49 that wraps the lower electrode 47; the dielectric layer 48 shown in the figure is wrapped around the surface of the lower electrode 47 to separate the lower electrode 47 from the upper electrode 49.

[0072] The above technical solution adopts a structure combining a columnar shape and a cylindrical shape, and increases the contact area of ​​the electrode plate through the concave hole structure on the top, thereby increasing the capacitance value of the capacitor. The capacitance value of the capacitor can be further increased by providing multiple concave hole structures on the top and arranging the capacitor in an array.

[0073] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A manufacturing method of a capacitor, characterized in that, comprising: providing a substrate, on the surface of which there is a sacrificial layer, and there are inverted trapezoidal capacitor vias in the sacrificial layer, and the substrate includes a contact pad located below the inverted trapezoidal capacitor vias; forming a lower electrode on the surface of the sacrificial layer, and the lower electrode covers the surface of the inverted trapezoidal capacitor vias in the sacrificial layer; removing the sacrificial layer to expose the lower electrode; forming a dielectric layer, and the dielectric layer is formed on the surface of the lower electrode and coats the lower electrode; forming an upper electrode, and the upper electrode covers the dielectric layer; the formation of the lower electrode further includes: depositing a first lower electrode layer on the surface of the sacrificial layer, and the first lower electrode layer fills the inverted trapezoidal capacitor vias; etching the first lower electrode layer to a predetermined height; depositing a second lower electrode layer on the first lower electrode layer, and the second lower electrode layer coats the exposed sacrificial layer of the inverted trapezoidal capacitor vias; etching the top of the second lower electrode layer to make the height of the second lower electrode layer flush with that of the sacrificial layer, forming an inverted trapezoidal lower electrode with a concave hole at the top.

2. The manufacturing method of the capacitor according to claim 1, characterized in that, the upper electrode fills the void left by removing the sacrificial layer.

3. The manufacturing method of the capacitor according to claim 1, characterized in that, the sacrificial layer is made of one or more of silicon oxide, silicon oxynitride, organic carbon, and organic silicon materials.

4. The manufacturing method of the capacitor according to claim 1, characterized in that, the substrate is made of one or more of SiN, SiCN, and SiON materials.

5. The manufacturing method of the capacitor according to claim 1, characterized in that, the contact pad is made of a metal material.

6. The manufacturing method of the capacitor according to claim 1, characterized in that, the first lower electrode layer, the second lower electrode layer, and the lower electrode are all made of one or more of Ti, TiN, doped polysilicon, SiGe, and metal W materials.

7. The manufacturing method of the capacitor according to claim 1, characterized in that, the dielectric layer is made of one or more of ZrO, Al2O3, and HFO materials.

8. The manufacturing method of the capacitor according to claim 1, characterized in that, the upper electrode is made of one or more of Ti, TiN, doped polysilicon, SiGe, and metal W materials.

9. A capacitor prepared by using the manufacturing method according to any one of claims 1-8, characterized in that, comprising: a lower electrode, which is an inverted trapezoidal structure with a concave hole at the top; a dielectric layer, which is wrapped on the surface of the lower electrode; an upper electrode, which coats the dielectric layer.

10. The capacitor according to claim 9, characterized in that, the upper electrode fills the voids around the dielectric layer.

11. The capacitor according to claim 9, characterized in that, there is a substrate below the lower electrode, and the substrate includes a contact pad, and the contact pad forms an electrical connection with the lower electrode.

12. The capacitor according to claim 11, characterized in that, The substrate is made of one or more of SiN, SiCN, and SiON materials.

13. The capacitor according to claim 11, wherein the contact pad is made of a metal material.

14. The capacitor according to claim 9, wherein the lower electrode is made of one or more of Ti, TiN, doped polysilicon, SiGe, and metal W materials.

15. The capacitor according to claim 9, wherein the dielectric layer is made of one or more of ZrO, Al2O3, and HFO materials.

16. The capacitor according to claim 9, wherein the upper electrode is made of one or more of Ti, TiN, doped polysilicon, SiGe, and metal W materials.

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