A method, device, storage medium and electronic equipment for silicon-based chip packaging

Abstract

The application provides a method, device, storage medium and electronic equipment for silicon-based chip packaging. First, image data of a grating in a silicon-based chip and a fiber array in a coupling process is obtained. Second, the posture of the fiber array is adjusted according to the image data, so that the adjusted fiber array is parallel to the silicon-based chip in a preset coordinate system. Then, an optical signal is input to the grating in the silicon-based chip, and the posture-adjusted fiber array is translated, so as to detect the optical power of the optical signal output by the translated fiber array after the optical signal is input from the grating in the silicon-based chip to the translated fiber array. Finally, if it is determined that the optical power meets a preset condition, the grating in the silicon-based chip and the fiber array are coupled, a coupled silicon-based chip is obtained, and the coupled silicon-based chip is packaged by a packaging device. The method can improve the coupling efficiency of the fiber array and the grating in the silicon-based chip.

Description

Technical Field

[0001] This specification relates to the field of integrated circuit packaging, and more particularly to a method, apparatus, storage medium, and electronic device for packaging silicon-based chips. Background Technology

[0002] Silicon-based optical switching chips offer advantages such as low power consumption, high performance, and low cost, making them widely used in high-performance computers, data centers, and other fields. Optical packaging is an essential step in the production of silicon-based optical switching chips. Due to limitations in equipment and manufacturing processes, the optical ports on silicon-based optical switching chips are typically packaged using grating coupling.

[0003] During grating coupling, the fiber array needs to be coupled to the grating on the silicon-based optical switching chip to maximize transmission efficiency. However, the alignment of the fiber array with the grating on the silicon-based optical switching chip often needs to be manually adjusted under a high-magnification optical lens. This process is very time-consuming and relies heavily on the experience of engineers.

[0004] Therefore, how to improve the efficiency of grating coupling between fiber arrays and silicon-based optical switching chips is an urgent problem to be solved. Summary of the Invention

[0005] This specification provides a method, apparatus, storage medium, and electronic device for packaging silicon-based chips, in order to partially solve the aforementioned problems existing in the prior art.

[0006] The following technical solution is adopted in this specification:

[0007] This specification provides a method for packaging silicon-based chips, including:

[0008] Acquire image data of the coupling process between the grating and the fiber array in a silicon-based chip;

[0009] Based on the image data, the orientation of the fiber optic array is adjusted so that the adjusted fiber optic array is parallel to the silicon-based chip in a preset coordinate system.

[0010] An optical signal is input into a grating in the silicon chip, and the optical fiber array after its orientation is adjusted is translated to detect the optical power corresponding to the optical signal output by the translated optical fiber array after the optical signal is input from the grating in the silicon chip to the translated optical fiber array.

[0011] If the optical power is determined to meet the preset conditions, the grating in the silicon chip is coupled with the optical fiber array to obtain the coupled silicon chip, and the coupled silicon chip is packaged by a packaging device.

[0012] Optionally, the image data includes: a frontal image of the silicon-based chip and the fiber array in a vertical plane;

[0013] Based on the image data, the orientation of the fiber optic array is adjusted so that the adjusted fiber optic array is parallel to the silicon-based chip in a preset coordinate system. Specifically, this includes:

[0014] Based on the front view of the silicon chip and the fiber array in a vertical plane, the upper edge contour of the front view of the silicon chip and the lower edge contour of the front view of the fiber array are determined.

[0015] Based on the upper edge contour of the front side of the silicon-based chip and the lower edge contour of the front side of the fiber array, the orientation of the fiber array is adjusted so that the vertical plane of the lower edge contour of the front side of the fiber array in the preset coordinate system is parallel to the upper edge contour of the front side of the silicon-based chip.

[0016] Optionally, the image data includes: a side view of the silicon-based chip and the fiber array in a vertical plane;

[0017] Based on the image data, the orientation of the fiber optic array is adjusted so that the adjusted fiber optic array is parallel to the silicon-based chip in a preset coordinate system. Specifically, this includes:

[0018] Based on the side views of the silicon chip and the fiber array in a vertical plane, the upper edge contour of the side of the silicon chip and the lower edge contour of the side of the fiber array are determined.

[0019] The orientation of the fiber array is adjusted based on the upper edge contour of the side of the silicon chip and the lower edge contour of the side of the fiber array, so that the vertical plane of the lower edge contour of the side of the fiber array in the preset coordinate system is parallel to the upper edge contour of the side of the silicon chip.

[0020] Optionally, the image data includes: an optical magnification image acquired by an optical magnification lens at a set angle, the optical magnification image containing images of the gratings and waveguides on the surface of the silicon-based chip and reflected images of the gratings and waveguides on the surface of the silicon-based chip based on reflection from the fiber array cover plate;

[0021] Based on the image data, the orientation of the fiber optic array is adjusted so that the adjusted fiber optic array is parallel to the silicon-based chip in a preset coordinate system. Specifically, this includes:

[0022] Based on the optical magnification image, determine the contour edges of the grating and waveguide on the surface of the silicon-based chip, as well as the contour edges of the reflected image of the grating and waveguide on the surface of the silicon-based chip.

[0023] Based on the contour edges of the grating and waveguide on the surface of the silicon chip and the contour edges of the reflected image of the grating and waveguide on the surface of the silicon chip, the orientation of the fiber array is adjusted to obtain a fiber array in which the grating and waveguide on the surface of the silicon chip are parallel to the reflected image of the grating and waveguide on the surface of the silicon chip, so that the adjusted fiber array is parallel to the silicon chip in a preset coordinate system.

[0024] Optionally, the orientation of the fiber array is adjusted based on the contour edges of the grating and waveguide on the surface of the silicon-based chip and the contour edges of the reflected image of the grating and waveguide on the surface of the silicon-based chip, to obtain a fiber array in which the grating and waveguide on the surface of the silicon-based chip are parallel to the reflected image of the grating and waveguide on the surface of the silicon-based chip, so that the adjusted fiber array is parallel to the silicon-based chip in a preset coordinate system. Specifically, this includes:

[0025] Based on the contour edges of the grating and waveguide on the surface of the silicon-based chip, the central axis corresponding to the grating and waveguide on the surface of the silicon-based chip is determined, and based on the contour edges of the reflected image of the grating and waveguide on the surface of the silicon-based chip, the central axis corresponding to the reflected image of the grating and waveguide on the surface of the silicon-based chip is determined.

[0026] The orientation of the fiber array is adjusted according to the central axis corresponding to the grating and waveguide on the surface of the silicon chip and the central axis corresponding to the reflected image of the grating and waveguide on the surface of the silicon chip, so that the central axis corresponding to the grating and waveguide on the surface of the silicon chip is parallel to the central axis corresponding to the reflected image of the grating and waveguide on the surface of the silicon chip, so that the adjusted fiber array is parallel to the silicon chip in a preset coordinate system.

[0027] Optionally, the orientation of the fiber array is adjusted according to the central axis corresponding to the grating and waveguide on the surface of the silicon-based chip and the central axis corresponding to the reflected image of the grating and waveguide on the surface of the silicon-based chip, so that the central axis corresponding to the grating and waveguide on the surface of the silicon-based chip is parallel to the central axis corresponding to the reflected image of the grating and waveguide on the surface of the silicon-based chip, so that the adjusted fiber array is parallel to the silicon-based chip in a preset coordinate system. Specifically, this includes:

[0028] For each grating on the surface of the silicon chip and the corresponding central axis of the waveguide, the parallelism of the central axis is calculated based on the central axis and the central axis of the reflected image of the grating on the surface of the silicon chip and the waveguide.

[0029] Determine the average parallelism based on the parallelism corresponding to each central axis;

[0030] Based on the average parallelism, the orientation of the fiber array is adjusted to obtain a fiber array in which the central axis corresponding to the grating and waveguide on the silicon chip surface is parallel to the central axis corresponding to the reflected image of the grating and waveguide on the silicon chip surface, so that the adjusted fiber array is parallel to the silicon chip in a preset coordinate system.

[0031] Optionally, the outer surface of the fiber array cover is perpendicular to the silicon-based chip, and the optical magnifying lens is at a 45-degree angle to the silicon-based chip.

[0032] Optionally, one end of the fiber array is coupled to a grating in the silicon-based chip, and the other end is provided with an optical power detection device, which is used to detect the optical power of the optical signal pair;

[0033] An optical signal is input into a grating in the silicon-based chip, and the optical fiber array, after its orientation has been adjusted, is translated to detect the optical power corresponding to the optical signal output by the translated optical fiber array after the optical signal is input from the grating in the silicon-based chip to the translated optical fiber array. Specifically, this includes:

[0034] An optical signal is input into a grating in the silicon chip, and the optical fiber array after its orientation is adjusted is translated to couple the grating in the silicon chip to one end of the optical fiber array. The optical power is then detected by the optical power detection device, which detects the optical power of the optical signal output by the translated optical fiber array after the optical signal is input from the grating in the silicon chip to the translated optical fiber array.

[0035] Optionally, based on the optical magnification image, determining the contour edges of the grating and waveguide on the surface of the silicon-based chip, as well as the contour edges of the reflected image of the grating and waveguide on the surface of the silicon-based chip, specifically includes:

[0036] The optical magnification image is binarized to obtain a black and white image, and the contour edges in the black and white image are extracted to determine the contour edges of the grating and waveguide on the surface of the silicon-based chip, as well as the contour edges of the reflected image of the grating and waveguide on the surface of the silicon-based chip.

[0037] This specification provides an apparatus for packaging a silicon-based chip, comprising:

[0038] The acquisition module is used to acquire image data of the coupling process between the grating and the fiber array in the silicon-based chip;

[0039] An adjustment module is used to adjust the orientation of the fiber array according to the image data, so that the adjusted fiber array is parallel to the silicon-based chip in a preset coordinate system.

[0040] The detection module is used to input an optical signal into the grating in the silicon chip and translate the fiber array after the orientation is adjusted, so as to detect the optical power corresponding to the optical signal output by the translated fiber array after the optical signal is input from the grating in the silicon chip to the translated fiber array.

[0041] A coupling module is used to couple the grating in the silicon-based chip to the fiber array if the optical power is determined to meet a preset condition, thereby obtaining a coupled silicon-based chip, and then package the coupled silicon-based chip using a packaging device.

[0042] Optionally, the image data includes: a frontal image of the silicon-based chip and the fiber array in a vertical plane;

[0043] The adjustment module is specifically used to determine the upper edge contour of the front side of the silicon-based chip and the lower edge contour of the front side of the fiber array based on the front images of the silicon-based chip and the fiber array in a vertical plane, and to adjust the orientation of the fiber array based on the upper edge contour of the front side of the silicon-based chip and the lower edge contour of the front side of the fiber array, so that the front side of the fiber array is parallel to the front side of the silicon-based chip in a vertical plane in a preset coordinate system.

[0044] Optionally, the image data includes: a side view of the silicon-based chip and the fiber array in a vertical plane;

[0045] The adjustment module is specifically used to determine the upper edge contour of the side of the silicon-based chip and the lower edge contour of the side of the fiber array based on the side images of the silicon-based chip and the fiber array in a vertical plane, and to adjust the orientation of the fiber array based on the upper edge contour of the side of the silicon-based chip and the lower edge contour of the side of the fiber array, so that the side of the adjusted fiber array is parallel to the side of the silicon-based chip in a vertical plane in a preset coordinate system.

[0046] Optionally, the image data includes: an optical magnification image acquired by an optical magnification lens at a set angle, the optical magnification image containing images of the gratings and waveguides on the surface of the silicon-based chip and reflected images of the gratings and waveguides on the surface of the silicon-based chip based on reflection from the fiber array cover plate;

[0047] The adjustment module is specifically used to determine the contour edges of the grating and waveguide on the surface of the silicon chip and the contour edges of the reflected image of the grating and waveguide on the surface of the silicon chip based on the optical magnification lens image. Based on the contour edges of the grating and waveguide on the surface of the silicon chip and the contour edges of the reflected image of the grating and waveguide on the surface of the silicon chip, the orientation of the fiber array is adjusted to obtain a fiber array in which the grating and waveguide on the surface of the silicon chip are parallel to the reflected image of the grating and waveguide on the surface of the silicon chip, so that the adjusted fiber array is parallel to the silicon chip in a preset coordinate system.

[0048] This specification provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method for silicon-based chip packaging.

[0049] This specification provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the above-described method for silicon-based chip packaging.

[0050] The above-mentioned technical solutions adopted in this specification can achieve the following beneficial effects:

[0051] In the silicon-based chip packaging method provided in this specification, image data of the coupling process between the grating in the silicon-based chip and the fiber array is acquired. Next, based on the image data, the orientation of the fiber array is adjusted so that the adjusted fiber array is parallel to the silicon-based chip in a preset coordinate system. Then, an optical signal is input to the grating in the silicon-based chip, and the orientation-adjusted fiber array is translated to detect the optical power corresponding to the optical signal output by the translated fiber array after the optical signal is input from the grating in the silicon-based chip to the translated fiber array. Finally, if the optical power is determined to meet a preset condition, the grating in the silicon-based chip and the fiber array are coupled, resulting in a coupled silicon-based chip, which is then packaged using a packaging device.

[0052] As can be seen from the above-described silicon-based chip packaging method, this method can adjust the orientation of the fiber optic array based on image data, so that the adjusted fiber optic array is parallel to the silicon-based chip in a preset coordinate system. Then, an optical signal is input to the grating in the silicon-based chip, and the orientation-adjusted fiber optic array is translated to detect the optical power corresponding to the optical signal output from the translated fiber optic array after the optical signal is input from the grating in the silicon-based chip to the translated fiber optic array. Finally, if the optical power meets the preset conditions, the grating in the silicon-based chip and the fiber optic array are coupled, resulting in a coupled silicon-based chip, which is then packaged using a packaging device. This method can improve the coupling efficiency between the fiber optic array and the grating in the silicon-based chip. Attached Figure Description

[0053] The accompanying drawings, which are included to provide a further understanding of this specification and form part of this specification, illustrate exemplary embodiments and are used to explain this specification, but do not constitute an undue limitation thereof. In the drawings:

[0054] Figure 1 A schematic flowchart illustrating the silicon-based chip packaging method provided in the embodiments of this specification;

[0055] Figure 2 A schematic diagram of a frontal view provided for an embodiment of this specification;

[0056] Figure 3 A schematic diagram of a side view provided for an embodiment of this specification;

[0057] Figure 4 A schematic diagram illustrating a process of acquiring an image using an optical magnifying glass, provided as an embodiment of this specification;

[0058] Figure 5 A schematic diagram of an optical magnification image provided in an embodiment of this specification;

[0059] Figure 6 A schematic diagram of the structure of the silicon-based chip packaging device provided in the embodiments of this specification;

[0060] Figure 7 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this specification. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of this specification clearer, the technical solutions of this specification will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of them. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0062] The technical solutions provided in the various embodiments of this specification are described in detail below with reference to the accompanying drawings.

[0063] Figure 1 This is a flowchart illustrating a silicon-based chip packaging method provided in the embodiments of this specification, specifically including the following steps:

[0064] S100: Acquire image data of the coupling process between the grating and the fiber array in the silicon-based chip.

[0065] S102: Based on the image data, adjust the orientation of the fiber array so that the adjusted fiber array is parallel to the silicon-based chip in a preset coordinate system.

[0066] In the embodiments of this specification, the execution subject of the silicon-based chip packaging method provided in this specification may be an electrically controlled displacement stage, which is equipped with electronic devices such as servers. For ease of description, the following description uses only the electrically controlled displacement stage as the execution subject to illustrate the silicon-based chip packaging method provided in this specification.

[0067] In the embodiments of this specification, the electrically controlled displacement stage can acquire image data of the coupling process between the grating and the fiber array in the silicon-based chip. The image data mentioned herein may include: a frontal image of the silicon-based chip and the fiber array in a vertical plane, a side image of the silicon-based chip and the fiber array in a vertical plane, and an optical magnification image acquired by an optical magnification lens at a set angle. The fiber array (FA) mentioned herein is an array constructed by mounting a bundle of optical fibers or a fiber ribbon at specified intervals on a V-groove substrate.

[0068] Secondly, the electrically controlled displacement stage can adjust the orientation of the fiber optic array based on image data, ensuring that the adjusted fiber optic array is parallel to the silicon-based chip in a preset coordinate system. This preset coordinate system can be a three-dimensional coordinate system predetermined by the electrically controlled displacement stage. The three-dimensional coordinate system includes X-axis, Y-axis, and Z-axis. Furthermore, the three-dimensional coordinate system contains XY-plane, XZ-plane, and YZ-plane.

[0069] In the embodiments of this specification, a first camera is provided on the electrically controlled displacement stage, and the first camera faces the front of the silicon-based chip and the fiber optic array in a vertical plane. The first camera can capture the front image of the silicon-based chip and the fiber optic array in the vertical plane. Specifically, as follows... Figure 2 As shown.

[0070] Figure 2 This is a schematic diagram of a frontal image provided for an embodiment of this specification.

[0071] exist Figure 2 In this design, a silicon-based chip 201 is fixed above the adapter board 200. Above the front of the silicon-based chip 201 is the front of the fiber optic array 202, which is controlled by an electrically controlled displacement stage. The electrically controlled displacement stage can adjust the camera so that the front of the silicon-based chip 201 and the front of the fiber optic array 202 are on the same focal plane, resulting in a clear image. The first camera captures the XZ plane in a three-dimensional coordinate system.

[0072] Furthermore, the electrically controlled displacement stage can determine the upper edge contour of the front side of the silicon-based chip and the lower edge contour of the front side of the fiber array based on the front images of the silicon-based chip and the fiber array in a vertical plane.

[0073] Then, the electrically controlled displacement stage can adjust the orientation of the fiber array according to the upper edge contour of the front side of the silicon chip and the lower edge contour of the front side of the fiber array, so that the vertical plane of the lower edge contour of the front side of the fiber array in the preset coordinate system is parallel to the upper edge contour of the front side of the silicon chip.

[0074] Specifically, the electrically controlled displacement stage can use image processing technology to extract the upper edge contour of the front side of the silicon-based chip and the lower edge contour of the front side of the fiber array, and determine the parallelism between the upper edge contour of the front side of the silicon-based chip and the lower edge contour of the front side of the fiber array.

[0075] Next, the electrically controlled displacement stage can adjust the orientation of the fiber array based on the parallelism between the upper edge contour of the front side of the silicon chip and the lower edge contour of the front side of the fiber array, so that the vertical plane of the lower edge contour of the front side of the fiber array in the preset coordinate system is parallel to the upper edge contour of the front side of the silicon chip.

[0076] The image processing technology mentioned here can refer to binarizing the front image of the silicon chip and the fiber array in a vertical plane to obtain a black and white image, and extracting the contour edges in the black and white image to determine the upper edge contour of the front of the silicon chip and the lower edge contour of the front of the fiber array.

[0077] In the embodiments described in this specification, a second camera is provided on the electrically controlled displacement stage. The second camera faces the side of the silicon-based chip and fiber optic array in a vertical plane. The second camera can capture side images of the silicon-based chip and fiber optic array in the vertical plane. Specifically, as follows... Figure 3 As shown.

[0078] Figure 3 This is a schematic diagram of a side view provided for an embodiment of this specification.

[0079] exist Figure 3 In this design, a silicon-based chip 201 is fixed above the adapter board 200, and the side of the silicon-based chip 201 is above the side of the fiber optic array 202, which is controlled by an electrically controlled displacement stage. The electrically controlled displacement stage can adjust the camera so that the side of the silicon-based chip 201 and the side of the fiber optic array 202 are on the same focal plane, resulting in a clear image. The second camera captures the YZ plane in a three-dimensional coordinate system.

[0080] Furthermore, the electrically controlled displacement stage can determine the upper edge contour of the silicon-based chip and the lower edge contour of the fiber array based on the side images of the silicon-based chip and the fiber array in a vertical plane.

[0081] Then, the electrically controlled displacement stage can adjust the orientation of the fiber array according to the upper edge contour of the side of the silicon chip and the lower edge contour of the side of the fiber array, so that the vertical plane of the lower edge contour of the side of the fiber array in the preset coordinate system is parallel to the upper edge contour of the side of the silicon chip.

[0082] Specifically, the electrically controlled displacement stage can use image processing technology to extract the upper edge contour of the side of the silicon-based chip and the lower edge contour of the side of the fiber array, and determine the parallelism between the upper edge contour of the side of the silicon-based chip and the lower edge contour of the side of the fiber array.

[0083] Next, the electrically controlled displacement stage can adjust the orientation of the fiber array based on the parallelism between the upper edge contour of the silicon chip side and the lower edge contour of the fiber array side, so that the vertical plane of the lower edge contour of the fiber array side in the preset coordinate system is parallel to the upper edge contour of the silicon chip side.

[0084] The image processing technology mentioned here can refer to binarizing the side images of silicon-based chips and fiber arrays in a vertical plane to obtain black and white images, and extracting the contour edges in the black and white images to determine the upper edge contour of the side of the silicon-based chip and the lower edge contour of the side of the fiber array.

[0085] In the embodiments of this specification, an optical magnifying lens with a set angle is provided on the electrically controlled displacement stage. The optical magnifying lens is at a set angle to the silicon-based chip. The fiber array cover plate is attached to the fiber array, and the outer surface of the fiber array cover plate satisfies the reflection angle with the silicon-based chip.

[0086] Specifically, the optical magnifying lens is positioned at a 45-degree angle to the silicon chip, and the outer surface of the fiber array cover is perpendicular to the silicon chip. This allows the optical magnifying lens to simultaneously capture images of the gratings and waveguides on the silicon chip surface, as well as reflected images of the gratings and waveguides on the silicon chip surface based on the reflection from the fiber array cover. For example... Figure 4 As shown.

[0087] Figure 4 This is a schematic diagram illustrating an embodiment of acquiring an image using an optical magnification lens, as provided in this specification.

[0088] exist Figure 4In this design, a silicon-based chip 201 is fixed above the adapter plate 200, and an optical fiber array 202 controlled by an electrically controlled displacement stage is positioned above the silicon-based chip 201. A cover plate 400 is attached to the optical fiber array 202, and the outer surface of the cover plate 400 is perpendicular to the silicon-based chip 201. An optical magnifying lens 401 is at a 45-degree angle to the silicon-based chip 201. The optical magnifying lens 401 captures the XY plane in a three-dimensional coordinate system.

[0089] It can be clearly seen that the optical magnifying lens 401 simultaneously captures images of the grating and waveguide on the surface of the silicon-based chip, as well as reflected images of the grating and waveguide on the surface of the silicon-based chip based on the reflection of the fiber array cover plate.

[0090] It should be noted that the angle between the optical magnifying lens and the silicon chip can also be other angles, as can the reflection angle between the outer surface of the fiber array cover and the silicon chip. The only requirement is that the optical magnifying lens can simultaneously acquire images of the grating and waveguide on the surface of the silicon chip, as well as the reflected images of the grating and waveguide on the surface of the silicon chip based on the reflection from the fiber array cover.

[0091] In the embodiments of this specification, the electrically controlled displacement stage can determine the contour edges of the grating and waveguide on the surface of the silicon-based chip, as well as the contour edges of the reflected image of the grating and waveguide on the surface of the silicon-based chip, based on the optical magnification lens image.

[0092] Then, the electrically controlled displacement stage can adjust the orientation of the fiber array based on the contour edges of the grating and waveguide on the silicon-based chip surface, as well as the contour edges of the reflected image of the grating and waveguide on the silicon-based chip surface. This results in a fiber array where the grating and waveguide on the silicon-based chip surface are parallel to the reflected image of the grating and waveguide on the silicon-based chip surface, ensuring that the adjusted fiber array is parallel to the silicon-based chip in a preset coordinate system. Specifically, as follows... Figure 5 As shown.

[0093] Figure 5 This is a schematic diagram of an optical magnification image provided in an embodiment of this specification.

[0094] exist Figure 5 In the image, the first rectangle represents the grating and waveguide on the surface of the silicon-based chip. The second rectangle represents the reflected image of the grating and waveguide on the surface of the silicon-based chip. Waveguide 500 appears as a triangle in the optical magnification image and is golden in the real world. Grating 501 appears as a black cuboid in the optical magnification image and is golden in the real world. Silicon-based chip 201 appears dark green in the real world.

[0095] Specifically, the electrically controlled displacement stage can use image processing technology to extract the contour edges of the grating and waveguide on the surface of the silicon-based chip, as well as the contour edges of the reflected images of the grating and waveguide on the surface of the silicon-based chip.

[0096] Secondly, the electrically controlled displacement stage can determine the central axis corresponding to the grating and waveguide on the silicon-based chip surface based on the contour edge of the grating and waveguide on the silicon-based chip surface, and determine the central axis corresponding to the reflected image of the grating and waveguide on the silicon-based chip surface based on the contour edge of the reflected image of the grating and waveguide on the silicon-based chip surface.

[0097] Next, the electrically controlled displacement stage can adjust the orientation of the fiber array according to the central axis corresponding to the grating and waveguide on the silicon chip surface and the central axis corresponding to the reflected image of the grating and waveguide on the silicon chip surface, so that the central axis corresponding to the grating and waveguide on the silicon chip surface is parallel to the central axis corresponding to the reflected image of the grating and waveguide on the silicon chip surface, so that the adjusted fiber array is parallel to the silicon chip in the preset coordinate system.

[0098] The image processing techniques mentioned here may refer to the binarization of images obtained through optical magnification.

[0099] Obtain a black and white image, extract the contour edges from the black and white image, and determine the contour edges of the grating and waveguide on the surface of the silicon-based chip, as well as the contour edges of the reflected image of the grating and waveguide on the surface of the silicon-based chip.

[0100] Furthermore, the electrically controlled displacement stage can calculate the parallelism of the central axis corresponding to the central axis of each grating and waveguide on the surface of the silicon-based chip, based on the central axis and the central axis corresponding to the reflected image of the grating and waveguide on the surface of the silicon-based chip.

[0101] Secondly, the electrically controlled displacement stage can determine the average parallelism based on the parallelism corresponding to each central axis. Finally, the electrically controlled displacement stage can adjust the orientation of the fiber array based on the average parallelism to obtain a fiber array in which the central axis corresponding to the grating and waveguide on the silicon chip surface is parallel to the central axis corresponding to the reflected image of the grating and waveguide on the silicon chip surface, so that the adjusted fiber array is parallel to the silicon chip in a preset coordinate system.

[0102] It should be noted that after the fiber array cover plate is attached to the fiber array, the cover plate and the five columns of the fiber array are parallel. If the grating and waveguide on the silicon-based chip surface are parallel to the reflected image of the grating and waveguide on the silicon-based chip surface, then the fiber array cover plate is parallel to the grating on the silicon-based chip surface. Therefore, it can be concluded that the fiber array is parallel to the grating on the silicon-based chip surface. Based on this, the electrically controlled displacement stage can translate the fiber array, thereby coupling the fiber array with the grating on the silicon-based chip surface.

[0103] In the embodiments of this specification, the electrically controlled displacement stage enables the adjusted fiber array to be parallel to the silicon chip in the XY plane of the preset coordinate system, parallel to the silicon chip in the XZ plane of the preset coordinate system, and parallel to the silicon chip in the YZ plane of the preset coordinate system. The electrically controlled displacement stage can then translate the fiber array after these three planes are aligned.

[0104] S104: Input the optical signal into the grating in the silicon chip and translate the fiber array after the attitude adjustment to detect the optical power corresponding to the optical signal output by the translated fiber array after the optical signal is input from the grating in the silicon chip to the translated fiber array.

[0105] In the embodiments of this specification, the electrically controlled displacement stage can input an optical signal into a grating in a silicon-based chip and translate and adjust the orientation of the fiber array to detect the optical power corresponding to the optical signal output by the translated fiber array after the optical signal is input from the grating in the silicon-based chip to the translated fiber array.

[0106] Specifically, one end of the fiber array is coupled to a grating in a silicon-based chip, and the other end is equipped with an optical power detection device, which is used to detect the optical power of the optical signal pair.

[0107] An electrically controlled displacement stage can input optical signals into a grating in a silicon-based chip and translate and adjust the orientation of a fiber array to couple the grating in the silicon-based chip to one end of the fiber array. Then, through an optical power detection device, the optical power corresponding to the optical signal output by the translated fiber array after the optical signal is input from the grating in the silicon-based chip to the translated fiber array is detected.

[0108] S106: If it is determined that the optical power meets the preset conditions, the grating in the silicon chip is coupled with the optical fiber array to obtain the coupled silicon chip, and the coupled silicon chip is packaged by a packaging device.

[0109] In the embodiments of this specification, if the optical power is determined to meet the preset conditions, the grating in the silicon-based chip is coupled with the fiber array to obtain the coupled silicon-based chip, and the coupled silicon-based chip is packaged by a packaging device.

[0110] Specifically, the electrically controlled displacement stage can determine the location of the fiber optic array when the optical power is at its maximum. The grating in the silicon-based chip is then coupled to the fiber optic array at that location.

[0111] As can be seen from the above process, this method can adjust the orientation of the fiber optic array based on image data, so that the adjusted fiber optic array is parallel to the silicon-based chip in a preset coordinate system. Then, an optical signal is input to the grating in the silicon-based chip, and the orientation-adjusted fiber optic array is translated to detect the optical power corresponding to the optical signal output from the translated fiber optic array after the optical signal is input from the grating in the silicon-based chip to the translated fiber optic array. Finally, if the optical power meets the preset conditions, the grating in the silicon-based chip and the fiber optic array are coupled, resulting in a coupled silicon-based chip, which is then packaged using a packaging device. This method can improve the coupling efficiency between the fiber optic array and the grating in the silicon-based chip.

[0112] The above describes one or more embodiments of silicon-based chip packaging methods provided in this specification. Based on the same concept, this specification also provides corresponding silicon-based chip packaging apparatus, such as... Figure 6 As shown.

[0113] Figure 6 This is a schematic diagram of the structure of the silicon-based chip packaging device provided in the embodiments of this specification, specifically including:

[0114] The acquisition module 600 is used to acquire image data of the coupling process between the grating and the fiber array in the silicon-based chip;

[0115] The adjustment module 602 is used to adjust the orientation of the fiber array according to the image data so that the adjusted fiber array is parallel to the silicon-based chip in a preset coordinate system.

[0116] The detection module 604 is used to input an optical signal into the grating in the silicon chip and translate the fiber array after the attitude is adjusted, so as to detect the optical power corresponding to the optical signal output by the translated fiber array after the optical signal is input from the grating in the silicon chip to the translated fiber array.

[0117] The coupling module 606 is used to couple the grating in the silicon-based chip to the fiber array if it is determined that the optical power meets the preset conditions, thereby obtaining a coupled silicon-based chip, and then package the coupled silicon-based chip through a packaging device.

[0118] Optionally, the image data includes: a frontal image of the silicon-based chip and the fiber array in a vertical plane;

[0119] The adjustment module 602 is specifically used to determine the upper edge contour of the front side of the silicon-based chip and the lower edge contour of the front side of the fiber array based on the front images of the silicon-based chip and the fiber array in a vertical plane, and adjust the orientation of the fiber array based on the upper edge contour of the front side of the silicon-based chip and the lower edge contour of the front side of the fiber array, so that the lower edge contour of the front side of the fiber array after adjustment is parallel to the upper edge contour of the front side of the silicon-based chip in a vertical plane under a preset coordinate system.

[0120] Optionally, the image data includes: a side view of the silicon-based chip and the fiber array in a vertical plane;

[0121] The adjustment module 602 is specifically used to determine the upper edge contour of the side of the silicon-based chip and the lower edge contour of the side of the fiber array based on the side images of the silicon-based chip and the fiber array in a vertical plane, and adjust the orientation of the fiber array based on the upper edge contour of the side of the silicon-based chip and the lower edge contour of the side of the fiber array, so that the lower edge contour of the side of the adjusted fiber array is parallel to the upper edge contour of the side of the silicon-based chip in a vertical plane of a preset coordinate system.

[0122] Optionally, the image data includes: an optical magnification image acquired by an optical magnification lens at a set angle, the optical magnification image containing images of the gratings and waveguides on the surface of the silicon-based chip and reflected images of the gratings and waveguides on the surface of the silicon-based chip based on reflection from the fiber array cover plate;

[0123] The adjustment module 602 is specifically used to determine the contour edges of the grating and waveguide on the surface of the silicon chip and the contour edges of the reflected image of the grating and waveguide on the surface of the silicon chip based on the optical magnification lens image, and to adjust the orientation of the fiber array based on the contour edges of the grating and waveguide on the surface of the silicon chip and the contour edges of the reflected image of the grating and waveguide on the surface of the silicon chip, so that the adjusted fiber array is parallel to the silicon chip in a preset coordinate system.

[0124] Optionally, the adjustment module 602 is specifically used to: determine the central axis corresponding to the grating and waveguide on the surface of the silicon-based chip based on the contour edge of the grating and waveguide on the surface of the silicon-based chip; determine the central axis corresponding to the reflected image of the grating and waveguide on the surface of the silicon-based chip based on the contour edge of the reflected image of the grating and waveguide on the surface of the silicon-based chip; and adjust the attitude of the fiber array based on the central axis corresponding to the grating and waveguide on the surface of the silicon-based chip and the central axis corresponding to the reflected image of the grating and waveguide on the surface of the silicon-based chip, so that the adjusted fiber array is parallel to the silicon-based chip in a preset coordinate system.

[0125] Optionally, the adjustment module 602 is specifically used to: for each grating on the surface of the silicon chip corresponding to the central axis of the waveguide, calculate the parallelism corresponding to the central axis and the central axis corresponding to the reflected image of the grating on the surface of the silicon chip; determine the average parallelism based on the parallelism of each central axis; and adjust the orientation of the fiber array based on the average parallelism to obtain a fiber array in which the central axis corresponding to the grating on the surface of the silicon chip is parallel to the central axis corresponding to the reflected image of the grating on the surface of the silicon chip, so that the adjusted fiber array is parallel to the silicon chip in a preset coordinate system.

[0126] Optionally, the outer surface of the fiber array cover is perpendicular to the silicon-based chip, and the optical magnifying lens is at a 45-degree angle to the silicon-based chip.

[0127] Optionally, one end of the fiber array is coupled to a grating in the silicon-based chip, and the other end is provided with an optical power detection device, which is used to detect the optical power of the optical signal pair;

[0128] The detection module 604 is specifically used to input an optical signal into the grating in the silicon-based chip and translate the fiber array after the attitude adjustment to couple the grating in the silicon-based chip to one end of the fiber array, and to detect the optical power corresponding to the optical signal output by the translated fiber array after the optical signal is input from the grating in the silicon-based chip to the translated fiber array through the optical power detection device.

[0129] Optionally, the adjustment module 602 is specifically used to perform binarization processing on the optical magnification image to obtain a black and white image, and extract the contour edges in the black and white image to determine the contour edges of the grating and waveguide on the surface of the silicon-based chip and the contour edges of the reflected image of the grating and waveguide on the surface of the silicon-based chip.

[0130] This specification also provides a computer-readable storage medium storing a computer program that can be used to execute the above-described... Figure 1 The provided method for packaging silicon-based chips.

[0131] This instruction manual also provides Figure 7 The diagram shows the structure of the electronic device. Figure 7 At the hardware level, the electronic device includes a processor, internal bus, network interface, memory, and non-volatile memory, and may also include other hardware required for the business operations. The processor reads the corresponding computer program from the non-volatile memory into memory and then runs it to achieve the above-mentioned functions. Figure 1 The provided method for packaging silicon-based chips.

[0132] Of course, in addition to software implementation, this specification does not exclude other implementation methods, such as logic devices or a combination of hardware and software. In other words, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0133] In the 1990s, improvements to a technology could be clearly distinguished as either hardware improvements (e.g., improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the methodology). However, with technological advancements, many methodological improvements today can be considered direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved methodology into the hardware circuit. Therefore, it cannot be said that a methodological improvement cannot be implemented using hardware physical modules. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. Designers can program and "integrate" a digital system onto a PLD themselves, without needing chip manufacturers to design and manufacture dedicated integrated circuit chips. Furthermore, nowadays, instead of manually manufacturing integrated circuit chips, this programming is mostly implemented using "logic compiler" software. Similar to the software compiler used in program development, the original code before compilation must be written in a specific programming language, called a Hardware Description Language (HDL). There are many HDLs, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language). Currently, the most commonly used are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should understand that by simply performing some logic programming on the method flow using one of these hardware description languages ​​and programming it into an integrated circuit, the hardware circuit implementing the logical method flow can be easily obtained.

[0134] The controller can be implemented in any suitable manner. For example, it can take the form of a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicon Labs C8051F320. A memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art will also recognize that, in addition to implementing the controller in purely computer-readable program code form, the same functionality can be achieved by logically programming the method steps to make the controller take the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the means included therein for implementing various functions can also be considered as structures within the hardware component. Alternatively, the means for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0135] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0136] For ease of description, the above devices are described in terms of function, divided into various units. Of course, in implementing this specification, the functions of each unit can be implemented in one or more software and / or hardware.

[0137] Those skilled in the art will understand that embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this specification may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0138] This specification is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this specification. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0139] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0140] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0141] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0142] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0143] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0144] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0145] Those skilled in the art will understand that the embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, this specification may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this specification may take the form of one or more computer-usable storage media (including, but not limited to, disk storage, etc.) containing computer-usable program code.

[0146] The form of a computer program product implemented on CD-ROM, optical storage, etc.

[0147] This specification may be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include those that perform a specific task or implement a specific abstract data type.

[0148] This manual describes routines, programs, objects, components, data structures, and so on. It can also be applied in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside on local and remote computer storage media, including storage devices.

[0149] The various embodiments in these five specifications are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0150] The above description is merely an embodiment of this specification and is not intended to limit this specification. Various modifications and variations can be made to this specification by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of the claims of this specification.

Claims

1. A method for packaging a silicon-based chip, characterized in that, include: Image data of the coupling process between the grating and the fiber array in the silicon-based chip is acquired; the image data includes: an optical magnification image acquired by an optical magnification lens at a set angle, the optical magnification image containing the image of the grating and waveguide on the surface of the silicon-based chip and the reflected image of the grating and waveguide on the surface of the silicon-based chip based on the reflection of the fiber array cover plate; Based on the image data, the orientation of the fiber array is adjusted so that the adjusted fiber array is parallel to the silicon-based chip in a preset coordinate system. An optical signal is input into a grating in the silicon chip, and the adjusted fiber array is shifted to detect the optical power corresponding to the optical signal output by the shifted fiber array after the optical signal is input from the grating in the silicon chip to the shifted fiber array. If the optical power is determined to meet the preset conditions, the grating in the silicon chip is coupled with the fiber array to obtain the coupled silicon chip, and the coupled silicon chip is packaged by a packaging device. The step of adjusting the orientation of the fiber optic array based on the image data so that the adjusted fiber optic array is parallel to the silicon-based chip in a preset coordinate system specifically includes: Based on the optical magnification image, determine the contour edges of the grating and waveguide on the surface of the silicon-based chip, as well as the contour edges of the reflected image of the grating and waveguide on the surface of the silicon-based chip. Based on the contour edges of the grating and waveguide on the surface of the silicon chip and the contour edges of the reflected image of the grating and waveguide on the surface of the silicon chip, the orientation of the fiber array is adjusted to obtain a fiber array in which the grating and waveguide on the surface of the silicon chip are parallel to the reflected image of the grating and waveguide on the surface of the silicon chip, so that the adjusted fiber array is parallel to the silicon chip in a preset coordinate system.

2. The method as described in claim 1, characterized in that, The image data also includes: a frontal image of the silicon-based chip and the fiber array in a vertical plane; Based on the image data, the orientation of the fiber optic array is adjusted so that the adjusted fiber optic array is parallel to the silicon-based chip in a preset coordinate system. The method further includes: Based on the front view of the silicon chip and the fiber array in a vertical plane, the upper edge contour of the front view of the silicon chip and the lower edge contour of the front view of the fiber array are determined. Based on the upper edge contour of the front side of the silicon-based chip and the lower edge contour of the front side of the fiber array, the orientation of the fiber array is adjusted so that the vertical plane of the lower edge contour of the front side of the fiber array in the preset coordinate system is parallel to the upper edge contour of the front side of the silicon-based chip.

3. The method as described in claim 2, characterized in that, The image data also includes: a side view of the silicon-based chip and the fiber array in a vertical plane; Based on the image data, the orientation of the fiber optic array is adjusted so that the adjusted fiber optic array is parallel to the silicon-based chip in a preset coordinate system. The method further includes: Based on the side views of the silicon chip and the fiber array in a vertical plane, the upper edge contour of the side of the silicon chip and the lower edge contour of the side of the fiber array are determined. The orientation of the fiber array is adjusted based on the upper edge contour of the side of the silicon chip and the lower edge contour of the side of the fiber array, so that the vertical plane of the lower edge contour of the side of the fiber array in the preset coordinate system is parallel to the upper edge contour of the side of the silicon chip.

4. The method as described in claim 3, characterized in that, Based on the contour edges of the grating and waveguide on the surface of the silicon-based chip and the contour edges of the reflected image of the grating and waveguide on the surface of the silicon-based chip, the orientation of the fiber array is adjusted to obtain a fiber array in which the grating and waveguide on the surface of the silicon-based chip are parallel to the reflected image of the grating and waveguide on the surface of the silicon-based chip, so that the adjusted fiber array is parallel to the silicon-based chip in a preset coordinate system. Specifically, this includes: Based on the contour edges of the grating and waveguide on the surface of the silicon-based chip, the central axis corresponding to the grating and waveguide on the surface of the silicon-based chip is determined, and based on the contour edges of the reflected image of the grating and waveguide on the surface of the silicon-based chip, the central axis corresponding to the reflected image of the grating and waveguide on the surface of the silicon-based chip is determined. The orientation of the fiber array is adjusted according to the central axis corresponding to the grating and waveguide on the surface of the silicon chip and the central axis corresponding to the reflected image of the grating and waveguide on the surface of the silicon chip, so that the central axis corresponding to the grating and waveguide on the surface of the silicon chip is parallel to the central axis corresponding to the reflected image of the grating and waveguide on the surface of the silicon chip, so that the adjusted fiber array is parallel to the silicon chip in a preset coordinate system.

5. The method as described in claim 4, characterized in that, Based on the central axis corresponding to the grating and waveguide on the surface of the silicon chip and the central axis corresponding to the reflected image of the grating and waveguide on the surface of the silicon chip, the orientation of the fiber array is adjusted to obtain a fiber array in which the central axis corresponding to the grating and waveguide on the surface of the silicon chip is parallel to the central axis corresponding to the reflected image of the grating and waveguide on the surface of the silicon chip, so that the adjusted fiber array is parallel to the silicon chip in a preset coordinate system. Specifically, this includes: For each grating on the surface of the silicon chip and the corresponding central axis of the waveguide, the parallelism of the central axis is calculated based on the central axis and the central axis of the reflected image of the grating on the surface of the silicon chip and the waveguide. Determine the average parallelism based on the parallelism corresponding to each central axis; Based on the average parallelism, the orientation of the fiber array is adjusted to obtain a fiber array in which the central axis corresponding to the grating and waveguide on the silicon chip surface is parallel to the central axis corresponding to the reflected image of the grating and waveguide on the silicon chip surface, so that the adjusted fiber array is parallel to the silicon chip in a preset coordinate system.

6. The method as described in claim 3, characterized in that, The outer surface of the fiber array cover is perpendicular to the silicon chip, and the optical magnifying lens is at a 45-degree angle to the silicon chip.

7. The method as described in claim 1, characterized in that, One end of the fiber array is coupled to a grating in the silicon chip, and the other end is provided with an optical power detection device, which is used to detect the optical power of the optical signal pair. An optical signal is input into a grating in the silicon-based chip, and the adjusted fiber array is shifted to detect the optical power corresponding to the optical signal output by the shifted fiber array after the optical signal is input from the grating in the silicon-based chip to the shifted fiber array. Specifically, this includes: An optical signal is input into a grating in the silicon chip, and the adjusted fiber array is shifted to couple the grating in the silicon chip to one end of the fiber array. The optical power is then detected by the optical power detection device, which detects the optical power of the optical signal output by the shifted fiber array after the optical signal is input from the grating in the silicon chip to the shifted fiber array.

8. The method as described in claim 3, characterized in that, Based on the optical magnification image, the contour edges of the grating and waveguide on the surface of the silicon-based chip, as well as the contour edges of the reflected image of the grating and waveguide on the surface of the silicon-based chip, are determined, specifically including: The optical magnification image is binarized to obtain a black and white image, and the contour edges in the black and white image are extracted to determine the contour edges of the grating and waveguide on the surface of the silicon-based chip, as well as the contour edges of the reflected image of the grating and waveguide on the surface of the silicon-based chip.

9. A device for packaging silicon-based chips, characterized in that, include: An acquisition module is used to acquire image data of the grating and fiber array in the silicon-based chip during the coupling process; the image data includes: an optical magnification image acquired by an optical magnification lens at a set angle, the optical magnification image containing images of the grating and waveguide on the surface of the silicon-based chip and reflected images of the grating and waveguide on the surface of the silicon-based chip based on the reflection of the fiber array cover plate; An adjustment module is used to adjust the orientation of the fiber array according to the image data, so that the adjusted fiber array is parallel to the silicon chip in a preset coordinate system. Specifically, the adjustment module is used to determine the contour edges of the grating and waveguide on the surface of the silicon chip and the contour edges of the reflected image of the grating and waveguide on the surface of the silicon chip according to the optical magnification lens image, and adjust the orientation of the fiber array according to the contour edges of the grating and waveguide on the surface of the silicon chip and the contour edges of the reflected image of the grating and waveguide on the surface of the silicon chip, so that the adjusted fiber array is parallel to the silicon chip in a preset coordinate system. The detection module is used to input an optical signal into the grating in the silicon chip and translate the adjusted fiber array to detect the optical power corresponding to the optical signal output by the translated fiber array after the optical signal is input from the grating in the silicon chip to the translated fiber array. A coupling module is used to couple the grating in the silicon-based chip to the fiber array if the optical power is determined to meet a preset condition, thereby obtaining a coupled silicon-based chip, and then package the coupled silicon-based chip using a packaging device.

10. The apparatus as claimed in claim 9, characterized in that, The image data also includes: a frontal image of the silicon-based chip and the fiber array in a vertical plane; The adjustment module is specifically used to determine the upper edge contour of the front side of the silicon-based chip and the lower edge contour of the front side of the fiber array based on the front images of the silicon-based chip and the fiber array in a vertical plane, and to adjust the orientation of the fiber array based on the upper edge contour of the front side of the silicon-based chip and the lower edge contour of the front side of the fiber array, so that the lower edge contour of the front side of the fiber array after adjustment is parallel to the upper edge contour of the front side of the silicon-based chip in a vertical plane under a preset coordinate system.

11. The apparatus as claimed in claim 9, characterized in that, The image data also includes: a side view of the silicon-based chip and the fiber array in a vertical plane; The adjustment module is specifically used to determine the upper edge contour of the side of the silicon-based chip and the lower edge contour of the side of the fiber array based on the side images of the silicon-based chip and the fiber array in a vertical plane, and to adjust the orientation of the fiber array based on the upper edge contour of the side of the silicon-based chip and the lower edge contour of the side of the fiber array, so that the lower edge contour of the side of the fiber array after adjustment is parallel to the upper edge contour of the side of the silicon-based chip in a vertical plane under a preset coordinate system.

12. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the method described in any one of claims 1 to 7.

13. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the method described in any one of claims 1 to 7.

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