Hardware Trojan Side-Channel Detection Method Based on Process Deviation Correction and Feature Matching

Abstract

The present invention discloses a hardware Trojan side-channel detection method based on process deviation correction and feature matching, which is applied to the fields of hardware security and integrated circuits. The present invention proposes to learn the circuit node features of the power consumption model using measured data and predict the circuit power consumption trajectory, and proposes a hardware Trojan side-channel detection method based on process deviation correction and feature matching; and organically combines the decision-making mechanism of the hardware Trojan with the circuit features to discriminate the hardware Trojan. The maximum relative error value of machine learning is used to measure the model matching degree, and together with the maximum relative error value of the pure circuit, a decision threshold is constructed. For test data outside the threshold range, it is considered that the hardware contains a hardware Trojan circuit.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits and hardware security, and particularly relates to a side-channel detection method for hardware Trojans based on machine learning. Background Art

[0002] A hardware Trojan refers to a general term for specific malicious circuits implanted by an attacker into an original circuit (or a pure circuit, a reference circuit) during the design or manufacturing process of an integrated circuit. Regardless of the type or category of the inserted hardware Trojan, without activation, it will not have any impact on the original circuit. Once activated under specific conditions, it will implement the functions preset by the attacker, such as leaking sensitive data in the circuit, denying service, reducing system reliability, or changing the working state of the circuit.

[0003] Hardware Trojan detection based on side-channel information (power consumption, current, path delay, electromagnetic radiation) is a commonly used hardware Trojan detection method. However, the detection technology based on side-channel information will produce certain errors under the dual influence of process variations and test noise. Moreover, the existing detection methods do not well separate and process the two. More often, process variations are treated as test noise, which may mask hardware Trojans with a small area ratio. Currently, the larger processing method is to use signal processing and probability statistics methods to reduce noise and extract information features, which has greatly improved the detection sensitivity and effect of hardware Trojans. However, the deviations caused by process noise during the chip manufacturing process cannot be eliminated by signal processing and probability statistics methods. The randomness and unpredictability of process variations are still a key issue in the process of side-channel information hardware Trojan detection. Summary of the Invention

[0004] The purpose of the present invention is to propose a side-channel detection method for hardware Trojans based on process variation correction and feature matching by restricting process variations within on-chip process variations.

[0005] The technical solution of the present invention is as follows:

[0006] (1) Construct a clock cycle power consumption model based on circuit nodes: Since the transient current model of MOS transistors in the circuit is too complex, and the short-circuit current during the inversion of the inverter causes fluctuations in the voltage of the power supply network, resulting in a very complex transient power consumption model in the circuit and containing a lot of interference information, a power consumption model used in this paper is proposed based on the internal node states of the circuit and the total power consumption of each clock cycle of the circuit.

[0007] (2) Measure on-chip process variations of the chip: Use an internal measurement structure (such as a ring oscillator, etc.) to measure the oscillation frequencies at different positions of the chip, and combine the HSPICE Monte Carlo simulation method to obtain the range of process variations inside the chip.

[0008] (3) Obtain the on-chip process variation: Map the on-chip process variation through process corners, and perform HSPICE simulation to backannotate the process corners into the process library of standard cells for subsequent power consumption analysis.

[0009] (4) Obtain circuit node information: Synthesize the RTL file embedded with the hardware Trojan to obtain a circuit structure (gate-level netlist, constraints, delay information) that meets the timing requirements and has consistent functions, and obtain relevant node information in the circuit for subsequent monitoring of the states of circuit nodes during the circuit operation.

[0010] (5) Obtain circuit node states: Through simulation verification experiments, obtain the circuit node states of the circuit in each clock cycle and obtain the simulation waveforms, so that when using the PTPX tool for subsequent power consumption analysis, the power consumption of the circuit can be correctly analyzed according to the flip states of the circuit nodes.

[0011] (6) Obtain circuit node power consumption: Use the backannotated process library generated in (3) and the waveform file obtained in (5), and use the PTPX tool to obtain the on-chip power consumption data of the chip for subsequent use in solving, verifying, and comparing power consumption models.

[0012] (7) Circuit power consumption prediction: Use machine learning methods to solve the small sample data set of the on-chip process variation obtained in (3). Since the power consumption data obtained during the test is a small sample data set relative to the entire input space, only machine learning methods can be used to solve complex circuit characteristics. After obtaining the circuit characteristics, predict the power consumption of the circuit.

[0013] (8) Hardware Trojan matching: Based on the method of data matching degree, organically combine the decision mechanism of the hardware Trojan with the circuit characteristics to discriminate the hardware Trojan. Since there are differences between the circuit characteristics of the pure circuit and the circuit characteristics of the hardware Trojan circuit, if the circuit characteristics of the pure circuit are used to learn the power consumption of the circuit containing the hardware Trojan, it will lead to a mismatch between the model and the data, resulting in a relatively large prediction error, thus determining that the circuit contains a suspicious circuit.

[0014] Advantages of the present invention: The advantages of the present invention are manifested in four aspects: (1) The present invention is a non-destructive hardware Trojan testing method based on side-channel information; (2) Initially limit the power consumption range of the chip within the on-chip process variation, providing test data and comparison data for subsequent solving of the power consumption model; improving the test accuracy; (3) The present invention only needs to test the chip to be tested and perform simulations in the design stage to complete the entire detection. Description of the Drawings

[0015] Figure 1 is the detection schematic diagram of the present invention. Detailed implementation mode

[0016] The present invention is based on two core models: constructing a clock cycle power consumption model based on circuit nodes and matching hardware Trojans based on circuit characteristics.

[0017] The clock cycle power consumption model based on circuit nodes according to the present invention: Assume that there are n+m+j+k nodes in the circuit during a certain period of time, where n nodes have an upward edge flip once, m nodes have a downward edge flip once, j nodes are at low level and do not flip, and k nodes are at high level and do not flip. Then the clock cycle power consumption based on circuit nodes can be expressed as:

[0018]

[0019] The integral of current is equal to electric charge, and the power consumption of the circuit is the product of voltage and electric charge. In digital circuits, the circuit operation process satisfies the timing constraints, and there are only switching changes in digital logic circuits. In a real circuit, once the circuit is determined, no matter what actions the circuit generates and how complex the transient current model is, the electric charge generated by an action of any node in the circuit is determined and will not change. If the electric charge generated by each node in different states and different operations can be known, then the energy consumed by the circuit in a certain period of time can be judged according to the circuit state. In circuit design, the node states of the circuit network are known at each moment. Then, for each clock cycle, the energy consumed by the circuit is the voltage multiplied by the electric charge in different states. Assume that the circuit has n nodes, and the number of upward edge flips of the i-th node in a clock cycle is n1(i); the number of downward edge flips is n2(i); if it does not flip and is in the low-level state, record n3(i) as 1, otherwise as 0; if it does not flip and is in the high-level state, record n4(i) as 1, otherwise as 0. An upward edge flip consumes Q1(i) electric charge, a downward edge flip consumes Q2(i) electric charge, maintaining the low-level state consumes Q3(i) electric charge, and maintaining the high-level state consumes Q4(i) electric charge. Then the energy consumed by the circuit in a clock cycle is the formula:

[0020]

[0021] The matching of hardware Trojans based on circuit characteristics according to the present invention: A neural network can be used to extract data characteristics and build a mathematical model. An artificial neural network imitates the brain neurons and uses multiple layers of neural units to build a complex and large neural network. In a single neuron, there are n inputs, and the n inputs can come from external inputs (input layer) or from the outputs of the previous-level neurons (middle layer, output layer); there is one output, and the output expression is that each input signal is multiplied by the corresponding weight w and summed, then compared with the threshold θ, and finally output. The output expression is shown as: Since there is a correlation between the internal node states of a circuit and the circuit power consumption, the circuit power consumption is predicted by means of the internal node states of the circuit, and the circuit power consumption is collected, so as to find out whether there is a suspicious circuit in the circuit.

[0022] Those of ordinary skill in the art will realize that the embodiments described herein are to assist the reader in understanding the principles of the present invention and should be understood that the scope of protection of the present invention is not limited to such specific statements and embodiments. Various modifications and variations can be made to the present invention for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the scope of the claims of the present invention.

Claims

1. A hardware Trojan side-channel detection method based on process deviation correction and feature matching, characterized in that Including: S1. Construct a clock cycle power consumption model based on circuit nodes; S2. Chip on-chip process variation measurement: Use the built-in measurement structure to measure the oscillation frequencies at different positions of the chip, and combine with the HSPICE Monte Carlo simulation method to obtain the on-chip process variation range; S3. Obtain on-chip process variations: Map the on-chip process variations through process corners, and use HSPICE simulation to backannotate the process corners to the process library of standard cells; S4. Obtain circuit node information: Synthesize the RTL file embedded with the hardware Trojan to obtain a circuit structure that meets the timing requirements and has consistent functions, and obtain the relevant node information in the circuit; S5. Obtain circuit node states: Through simulation verification experiments, the circuit node states in each clock cycle can be obtained, and the simulation waveforms can be obtained; S6. Obtain circuit node power consumption: Use the backannotated process library generated in step S3 and the waveform file obtained in step S5, and use the PTPX tool to obtain the on-chip power consumption data of the chip; S7. Circuit power consumption prediction: Use the machine learning method to solve the small sample data set of the on-chip process variations obtained in step S3 to obtain circuit characteristics, and predict the power consumption of the circuit according to the circuit characteristics; The circuit characteristics are specifically the internal node states of the circuit; S8. Hardware Trojan matching: Based on the method of data matching degree, combine the decision-making mechanism of the hardware Trojan with the circuit characteristics organically to discriminate the hardware Trojan.

2. The hardware Trojan side-channel detection method based on process deviation correction and feature matching according to claim 1, characterized in that The built-in measurement structure described in step S2 is a ring oscillator.

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