Pseudo-gate processing method

Abstract

The application provides a pseudo-gate processing method, which comprises sequentially depositing a nitrided medium layer and a first loose oxidized medium layer on a base of a first pseudo-gate, grinding the first loose oxidized medium layer until the vertical distance between the top surface of the first loose oxidized medium layer and the top surface of the pseudo-gate medium layer of the first pseudo-gate reaches a preset value, the preset value is greater than 0, and then removing the pseudo-gate medium layer and part of the side wall structure of the first pseudo-gate through an etching and grinding cross process. After the nitrided medium layer covering the exposed surface of the first pseudo-gate is deposited on the base, the first loose oxidized medium layer covering the exposed surface of the nitrided medium layer is deposited to replace the photoresist, defects caused by the etching and photoetching back-etching process of the pseudo-gate are avoided through the grinding and etching process, the damage to the base is reduced, and the influence of the residual defects of the polysilicon layer on the subsequent metal gate filling is avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for fabricating dummy gates. Background Technology

[0002] As the requirements for integrated circuit design and manufacturing become increasingly stringent, the feature size of MOSFETs is shrinking. Because metal gates are not heat-resistant, a gate-last process is now commonly used to form metal gates. In the gate-last process, the amorphous silicon in the gate is first subjected to multiple chemical mechanical polishing processes of the interlayer dielectric layers. After high-temperature annealing, the amorphous silicon in the dummy gate region is removed, and then metal is filled in to form the metal gate.

[0003] Before etching the dummy gate, photoresist is typically applied to define the etching area before etching back. Because the process window is relatively narrow on the SiGe substrate, if the SiGe layer is high, the photoresist cannot effectively block it, making the etching process difficult to control. When the substrate also contains NiSi, NiSi depression damage often occurs. Furthermore, in the first step of photoresist etching back, insufficient etching often results in excessively high "horns," causing premature termination of chemical mechanical polishing (CMP) or significant burrs during CMP due to differences in hardness. This can lead to incomplete removal of the polysilicon layer of the dummy gate, affecting subsequent metal gate filling and ultimately reducing the electrical performance and reliability of the transistor device.

[0004] Therefore, it is necessary to develop new technologies to solve the aforementioned problems existing in the prior art. Summary of the Invention

[0005] The purpose of this invention is to provide a pseudo-gate fabrication method to avoid defects generated during the pseudo-gate etching photolithography re-etching process, reduce substrate damage, and prevent residual defects in the polysilicon layer from affecting subsequent metal gate filling.

[0006] To achieve the above objectives, the pseudo-gate fabrication method of the present invention includes:

[0007] S0: Provide a substrate, the top surface of which is provided with a first dummy gate, the first dummy gate including a first dummy gate and a first sidewall structure disposed opposite to both sides of the first dummy gate, the first dummy gate including a first amorphous silicon layer and a first dummy gate dielectric layer stacked sequentially, and the top of the first dummy gate dielectric layer is exposed.

[0008] S1: A nitrided dielectric layer covering the exposed surface of the first pseudogate and a first loose oxide dielectric layer covering the exposed surface of the nitrided dielectric layer are sequentially deposited on the substrate;

[0009] S2: Grind the first loose oxide dielectric layer until the vertical distance between the top surface of the first loose oxide dielectric layer and the top surface of the first pseudo gate dielectric layer reaches a preset value, and then etch the first loose oxide dielectric layer and part of the nitride dielectric layer with the first pseudo gate dielectric layer as the stop layer, wherein the preset value is greater than 0.

[0010] S3: Using the first amorphous silicon layer as a stop layer, etch the first pseudo-gate dielectric layer, part of the first sidewall structure and part of the nitride dielectric layer to form a groove, and deposit a second loose oxide dielectric layer on the substrate to fill the groove;

[0011] S4: Grind the first amorphous silicon layer as the stop layer, and then etch away the remaining second loose oxide dielectric layer.

[0012] The beneficial effects of the dummy gate processing method of the present invention are as follows: after the nitride dielectric layer covering the exposed surface of the first dummy gate and the first loose oxide dielectric layer covering the exposed surface of the nitride dielectric layer are sequentially deposited on the substrate in step S1, the grinding and etching processes in steps S2 and S3 avoid defects generated by the photolithography back-etching process of the dummy gate, reduce substrate damage and avoid residual defects of the polysilicon layer affecting the subsequent metal gate filling.

[0013] Preferably, in step S2, the step of etching the first loose oxide dielectric layer and part of the nitride dielectric layer with the first pseudo-gate dielectric layer as the stop layer includes: selecting an etching gas such that the etching selectivity ratio of the first loose oxide dielectric layer and the nitride dielectric layer is 1:1 for dry etching.

[0014] Preferably, the first dummy gate dielectric layer includes a first dummy gate nitride dielectric layer and a first dummy gate oxide dielectric layer stacked sequentially from the top surface of the first amorphous silicon layer, and the top of the first dummy gate oxide dielectric layer is exposed. In step S3, the step of etching the first dummy gate dielectric layer, part of the first sidewall structure and part of the nitride dielectric layer with the first amorphous silicon layer as the stop layer includes: after etching the first dummy gate oxide dielectric layer with the first dummy gate nitride dielectric layer as the stop layer, etching the first dummy gate nitride dielectric layer, part of the first sidewall structure and part of the nitride dielectric layer with the first amorphous silicon layer as the stop layer.

[0015] Preferably, the top surface of the substrate is further provided with a second dummy gate, the second dummy gate including a second dummy gate and a second sidewall structure disposed opposite to both sides of the second dummy gate, the second dummy gate including a second amorphous silicon layer and a second dummy gate dielectric layer stacked sequentially from the top surface of the substrate, the top of the second dummy gate dielectric layer is exposed and the top surface is lower than the top surface of the first dummy gate dielectric layer, in step S1, the step of sequential deposition on the substrate is performed so that the formed nitride dielectric layer also covers the exposed surface of the second dummy gate and the exposed surface of the substrate.

[0016] Preferably, after step S2 is completed, grinding is performed with the second pseudo-gate dielectric as the stopping position until the top surface of the remaining first pseudo-gate dielectric layer and the top surface of the second pseudo-gate dielectric layer are flush, and then step S3 is performed.

[0017] Preferably, in step S3, during the etching step with the first amorphous silicon layer as the stop layer, the second pseudo-gate dielectric layer, part of the second sidewall structure, and part of the nitride dielectric layer are also removed to form a corresponding groove. The step of depositing on the substrate further causes the second loose oxide dielectric layer to fill the corresponding groove.

[0018] Preferably, the second pseudo-gate dielectric layer includes a second pseudo-gate nitride dielectric layer and a second pseudo-gate oxide dielectric layer stacked sequentially from the top surface of the second amorphous silicon layer. In step S3, the step of etching with the first pseudo-gate nitride dielectric layer as the stop layer also removes the second pseudo-gate oxide dielectric layer. The step of etching with the first amorphous silicon layer as the stop layer also removes the second pseudo-gate nitride dielectric layer, a portion of the second sidewall structure, and a portion of the nitride dielectric layer.

[0019] Preferably, in step S4, performing the grinding step with the first amorphous silicon layer as the stop layer also exposes the top surface of the second amorphous silicon layer.

[0020] Preferably, before performing step S1, a nickel-silicon layer is deposited on the substrate to form a layer covering the exposed surface of the substrate, the first dummy gate exposed surface, and / or the second dummy gate exposed surface. Attached Figure Description

[0021] Figure 1 This is a flowchart of the pseudo-gate fabrication method according to an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of the substrate and a plurality of pseudo-gates disposed on the substrate, according to an embodiment of the present invention.

[0023] Figure 3 In order to be in Figure 2 A schematic diagram of the structure obtained after depositing a nitrided medium layer on the structure shown;

[0024] Figure 4 In order to be in Figure 3 A schematic diagram of the structure obtained after depositing the first loose oxide medium layer on the structure shown.

[0025] Figure 5 In order to be in Figure 4 A schematic diagram of the structure obtained after removing part of the first loose oxide medium layer based on the structure shown.

[0026] Figure 6 In order to be in Figure 5 A schematic diagram of the structure obtained after removing part of the first loose oxide medium layer based on the structure shown.

[0027] Figure 7 In order to be in Figure 6 A schematic diagram of the structure obtained by dry etching with each first pseudo-gate oxide dielectric layer as a stop layer based on the structure shown.

[0028] Figure 8 In order to be in Figure 7 A schematic diagram of the structure obtained after grinding with each second pseudo-gate oxide dielectric layer as a stop layer based on the structure shown;

[0029] Figure 9 In order to be in Figure 8 A schematic diagram of the structure obtained after dry etching of each first pseudo-gate oxide dielectric layer and each second pseudo-gate oxide dielectric layer based on the structure shown.

[0030] Figure 10 In order to be in Figure 9 A schematic diagram of the structure obtained by dry etching of each first pseudo-gate nitride dielectric layer, each second pseudo-gate nitride dielectric layer, each first sidewall structure and each second sidewall structure based on the structure shown.

[0031] Figure 11 In order to be in Figure 10 A schematic diagram of the structure obtained after depositing a second loose oxide medium layer on the basis of the structure shown.

[0032] Figure 12 In order to be in Figure 11 A schematic diagram of the structure obtained after grinding based on the structure shown, with each first amorphous silicon layer and each second amorphous silicon layer as the stopping position;

[0033] Figure 13 In order to be in Figure 12 A schematic diagram of the structure obtained after wet etching of the remaining nitrided dielectric layer based on the structure shown. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0035] This invention provides a method for fabricating a pseudo-gate to avoid defects generated during the pseudo-gate etching photolithography re-etching process, reduce substrate damage, and prevent residual defects in the polysilicon layer from affecting subsequent metal gate filling.

[0036] The dummy gate fabrication method of this invention is performed on a substrate. A first dummy gate is disposed on the top surface of the substrate. The first dummy gate includes a first dummy gate and first sidewall structures disposed opposite to each other on both sides of the first dummy gate. The first dummy gate includes a first amorphous silicon layer and a first dummy gate dielectric layer stacked sequentially, with the top of the first dummy gate dielectric layer exposed.

[0037] Reference Figure 1 The pseudo-gate fabrication method of the present invention includes:

[0038] S1: A nitrided dielectric layer covering the exposed surface of the first pseudogate and a first loose oxide dielectric layer covering the exposed surface of the nitrided dielectric layer are sequentially deposited on the substrate;

[0039] S2: Grind the first loose oxide dielectric layer until the vertical distance between the top surface of the first loose oxide dielectric layer and the top surface of the first pseudo gate dielectric layer reaches a preset value, and then dry etch the first loose oxide dielectric layer and part of the nitride dielectric layer with the first pseudo gate dielectric layer as the stop layer.

[0040] S3: Using the first amorphous silicon layer as a stop layer, dry etch the first pseudo-gate dielectric layer, part of the first sidewall structure and part of the nitride dielectric layer to form a groove, and deposit a second loose oxide dielectric layer on the substrate to fill the groove.

[0041] S4: Using the first amorphous silicon layer as a stop layer, perform grinding, and then wet etch to remove the remaining second loose oxide dielectric layer.

[0042] In this embodiment of the invention, the preset value is greater than 0.

[0043] In some embodiments, reference is made to Figure 2 A first dummy gate 2 is disposed on the top surface of substrate 1. The first dummy gate 2 comprises a first amorphous silicon layer 21, a first dummy gate nitride dielectric layer 22, and a first dummy gate oxide dielectric layer 23, which are sequentially stacked from the top surface of substrate 1, forming a first dummy gate. The first sidewall structure (not shown in the figure) is composed of a first sidewall 241 and a second sidewall 242 disposed on opposite sides of the first dummy gate. Both the first sidewall 241 and the second sidewall 242 cover a portion of the side surface of the first amorphous silicon layer 21, a portion of the side surface of the first dummy gate nitride dielectric layer 22, and a portion of the side surface of the first dummy gate oxide dielectric layer 23, with the top of the first dummy gate oxide dielectric layer 23 exposed.

[0044] In some embodiments, reference is made to Figure 2 The top surface of the substrate 1 is further provided with a second dummy gate 3. The second dummy gate 3 comprises a second amorphous silicon layer 31, a second dummy gate nitride dielectric layer 32, and a second dummy gate oxide dielectric layer 33, which are sequentially stacked from the top surface of the substrate 1, forming a second dummy gate. The second sidewall structure (not shown in the figure) is composed of a third sidewall 341 and a fourth sidewall 342 disposed on opposite sides of the second dummy gate. Both the third sidewall 341 and the fourth sidewall 342 cover a portion of the side surface of the second amorphous silicon layer 32, a portion of the side surface of the second dummy gate nitride dielectric layer 32, and a portion of the side surface of the second dummy gate oxide dielectric layer 33, with the top of the second dummy gate oxide dielectric layer 33 exposed.

[0045] In some embodiments, the substrate 1 is a silicon substrate.

[0046] In some embodiments, both the first pseudo-gate nitride dielectric layer 22 and the second pseudo-gate nitride dielectric layer 32 are composed of silicon nitride.

[0047] In some embodiments, the first pseudo-gate oxide dielectric layer 23 and the second pseudo-gate oxide dielectric layer 33 are both composed of silicon oxide.

[0048] In some embodiments, the first sidewall 241, the second sidewall 242, the third sidewall 341, and the fourth sidewall 342 are all made of silicon nitride.

[0049] In some embodiments, reference is made to Figure 2The substrate 1 includes a core region 11 and an input / output region 12. The core region 11 is used to integrate core components to realize the main functions of the integrated circuit. For example, the core region 11 includes a Core nFET region corresponding to the second pseudo-gate 3 and an adjacent Core pFET region. The input / output region 12 provides corresponding input signals to the core components set in the core region 11 or allows the core components to output corresponding signals. For example, the input / output region 12 includes an IO pFET region corresponding to the first pseudo-gate 2 and an adjacent IO nFET region.

[0050] In some embodiments, reference is made to Figure 2 The pseudo-gate adjacent to the second pseudo-gate 3 also includes a silicon-germanium region 35. Specifically, the silicon-germanium region 35 may be disposed in the Core pFET region.

[0051] In some embodiments, reference is made to Figure 2 The core area 11 and the input / output area 12 are separated by an isolation area 13. Specifically, the isolation area 13 is made of silicon oxide.

[0052] In some embodiments, reference is made to Figure 2 The number and arrangement of the first pseudo-gate 2 and the second pseudo-gate 3 set on the substrate 1 can be flexibly selected according to process requirements.

[0053] In step S1 of some embodiments, reference is made to Figures 2 to 4 The pseudo-gate fabrication method involves setting a plurality of first pseudo-gates 2 on the top surface of a substrate, depositing a nitrided dielectric layer 4 on the substrate 1 to cover the exposed surface of each of the first pseudo-gates 2, and then depositing a first loose oxide dielectric layer 5 to cover the exposed surface of the nitrided dielectric layer 4.

[0054] In step S1 of some embodiments, reference is made to Figures 2 to 4 The pseudo-gate fabrication method involves setting a plurality of first pseudo-gates 2 and a plurality of second pseudo-gates 3 on the top surface of a substrate. After depositing a nitrided dielectric layer 4 on the substrate 1 to cover the exposed surfaces of each of the first pseudo-gates 3, each of the second pseudo-gates 3, and the exposed surfaces of the substrate 1, a first loose oxide dielectric layer 5 is then deposited to cover the exposed surfaces of the nitrided dielectric layer 4.

[0055] When the height of the core region 11 is lower than the height of the input / output region 12, and the height of each second pseudo gate 3 is lower than the height of each first pseudo gate 2, the height of the first loose oxide medium layer 5 deposited corresponding to the core region 11 is less than the height of the first loose oxide medium layer 5 deposited corresponding to the first input / output region 12.

[0056] In some embodiments, the nitride dielectric layer 4, which is composed of silicon nitride, is deposited by LPCVD, and the specific implementation method is a conventional technique used by those skilled in the art.

[0057] In traditional pseudo-gate etch-back processes, a silicon nitride dielectric layer is typically deposited as a buffer before photoresist is coated, followed by etch-back. However, insufficient etching during the etch-back process can easily lead to excessively high "horn" shapes, causing premature termination or incomplete removal of the kerf during subsequent chemical mechanical polishing. In some embodiments, the first porous oxide dielectric layer 5 is formed by wet oxidation deposition. Compared to oxide dielectric layers prepared by dry oxidation, the first porous oxide dielectric layer 5 has a faster growth rate and a looser structure. Using it to replace photoresist, combined with subsequent polishing and dry etching processes, can avoid defects generated in the pseudo-gate etching photoresist etch-back process.

[0058] In some embodiments, the first loose oxide medium layer 5 is formed by pure water bubbling wet oxidation or flash evaporation wet oxidation deposition, which is a conventional technique used by those skilled in the art.

[0059] In some embodiments, prior to performing step S1, a nickel-silicon layer is deposited on the substrate 1 to cover the exposed surface of the substrate 1, the exposed surface of the first dummy gate 2, and / or the exposed surface of the second dummy gate 3.

[0060] In step S2 of some embodiments, when the substrate 1 is provided with a plurality of the first dummy gates 2, refer to Figure 2 , Figure 4 and Figure 5 The first loose oxide dielectric layer 5 is ground until the vertical distance H between the top surface of the first loose oxide dielectric layer 5 and the top surface of the nitride dielectric layer 4 reaches a preset value. Then, the first loose oxide dielectric layer 5 and the nitride dielectric layer 4 are dry etched using the first pseudo-gate oxide dielectric layer 23 as a stop layer. Specifically, the first loose oxide dielectric layer 5 is ground using chemical mechanical polishing (CMP). The first loose oxide dielectric layer 5 and the nitride dielectric layer 4 are etched using a dry etching process.

[0061] In some embodiments, H is 50-150 angstroms.

[0062] In step S2 of some embodiments, when the substrate 1 is provided with a plurality of first pseudo-gates 2 and a plurality of second pseudo-gates 3, refer to Figure 2 , Figure 4 and Figure 5Since the height of each second pseudo gate 3 is lower than the height of each first pseudo gate 2, the first loose oxide medium layer 5 is ground until the vertical distance between the top surface of the first loose oxide medium layer 5 and the top surface of the nitrided medium layer 4 reaches a preset value. At the same time, the first loose oxide medium layer 5 above several second pseudo gates 3 is also thinned synchronously. After grinding, the vertical distance between the top surface of the first loose oxide medium layer 5 and the top surface of the nitrided medium layer 4 covering the second pseudo gate 3 is greater than H.

[0063] In step S2 of some embodiments, reference is made to Figure 2 , Figure 5 and Figure 6 After the first porous oxide dielectric layer 5 is etched using a dry etching process with the top surface of the nitride dielectric layer 4 covering the top surface of the first pseudo gate oxide dielectric layer 23 as the stopping position, the top surface of the nitride dielectric layer 4 covering the top surface of the first pseudo gate oxide dielectric layer 23 is exposed, while the top surface of the second pseudo gate oxide dielectric layer 33 is still covered by the nitride dielectric layer 4.

[0064] In step S2 of some embodiments, reference is made to Figure 2 , Figure 6 and Figure 7 Using the top surface of the first pseudo-gate oxide dielectric layer 23 as the stopping position, the dry etching process is used to continue etching, and the nitride dielectric layer 4 covering the top surface of each of the first pseudo-gate oxide dielectric layers 23 is gradually thinned until the top surface of each of the first pseudo-gate oxide dielectric layers 23 is exposed.

[0065] In step S2 of some embodiments, the first loose oxide layer 5 and the nitride layer 4 are dry-etched using an etching gas with an etching selectivity ratio of 1:1 for the material composition of the first loose oxide layer 5 and the material composition of the nitride layer 4.

[0066] In some specific embodiments, the first loose oxide dielectric layer 5 is composed of silicon oxide, the nitride dielectric layer 4 is composed of silicon nitride, and the etching gas is CF4.

[0067] In some embodiments, when the substrate 1 is provided with a plurality of first pseudo-gates 2 and a plurality of second pseudo-gates 3, after step S2 in some embodiments is completed, refer to Figure 2 , Figure 7 and Figure 8Since the top surface of each of the first pseudo-gate oxide dielectric layers 23 is exposed, while the top surface of each of the second pseudo-gate oxide dielectric layers 33 is still covered by the nitrided dielectric layer 4, and the top surface of the nitrided dielectric layer 4 corresponding to the core region 11 is still covered by the first loose oxide dielectric layer 5, after step S2 is completed, chemical mechanical polishing (CMP) is performed with the top surface of the second pseudo-gate oxide dielectric layer 33 as the stop position until the top surface of the first pseudo-gate oxide dielectric layer 23 of each of the first pseudo-gates 2 and the top surface of the second pseudo-gate oxide dielectric layer 33 of each of the second pseudo-gates 3 are flush, and then step S3 is executed.

[0068] In step S3 of some embodiments, when the substrate 1 is provided with a plurality of the first dummy gates 2, referring to Figure 2 as well as Figures 8 to 10 After dry etching to remove each of the first pseudo-gate oxide dielectric layers 23 with the top surface of each of the first pseudo-gate nitride dielectric layers 22 as the stop position, dry etching is then performed to remove each of the first pseudo-gate nitride dielectric layers 22, a portion of each of the first sidewalls 241, a portion of each of the second sidewalls 242, and a portion of the nitride dielectric layer 4 covering each of the first sidewalls 241 and the second sidewalls 242, forming a plurality of grooves 61.

[0069] In step S3 of some embodiments, when the substrate 1 is provided with a plurality of first pseudo-gates 2 and a plurality of second pseudo-gates 3, refer to Figure 2 as well as Figures 8 to 10 The process of dry etching to remove the first pseudo-gate oxide dielectric layer 23 with the top surface of each first pseudo-gate nitride dielectric layer 22 as the stop position also simultaneously removes the second pseudo-gate oxide dielectric layer 33; the process of dry etching to remove the second pseudo-gate nitride dielectric layer 32, a portion of each third sidewall 243, a portion of each fourth sidewall 244, and a portion of the nitride dielectric layer 4 covering each third sidewall 243 and each fourth sidewall 244 simultaneously forms a plurality of corresponding grooves 62.

[0070] In step S3 of some embodiments, the constituent material of each of the pseudo gate oxide dielectric layers 23 and each of the second pseudo gate oxide dielectric layers 33 is silicon oxide, and the etching gases used for dry etching of each of the pseudo gate oxide dielectric layers 23 and each of the second pseudo gate oxide dielectric layers 33 are CF4 and O2.

[0071] In step S3 of some embodiments, the constituent materials of each of the first pseudo-gate nitride dielectric layer 22, each of the second pseudo-gate nitride dielectric layer 32, each of the first sidewall 241, each of the second sidewall 242, each of the third sidewall 243 and each of the fourth sidewall 244, and the nitride dielectric layer 4 are all silicon nitride. The etching gas used for dry etching of each of the first pseudo-gate nitride dielectric layer 22 and each of the second pseudo-gate nitride dielectric layer 32, as well as for dry etching of each of the first sidewall 241, each of the second sidewall 242, each of the third sidewall 243 and each of the fourth sidewall 244, and the nitride dielectric layer 4 disposed on the corresponding sidewalls, is CHF3.

[0072] In step S3 of some embodiments, when the substrate 1 is provided with a plurality of the first dummy gates 2, referring to Figure 2 , Figure 10 and Figure 11 A second loose oxide medium layer 7 is deposited on the substrate 1 to fill each of the grooves 61. The second loose oxide medium layer 7 also covers the remaining first sidewall 241, the remaining second sidewall 242 of each of the first pseudo gates 2, and the top surface of the nitride medium layer 4 covering the respective remaining first sidewall 241 and the remaining second sidewall 242.

[0073] In step S3 of some embodiments, when the substrate 1 is provided with a plurality of first pseudo-gates 2 and a plurality of second pseudo-gates 3, refer to Figure 2 , Figure 10 and Figure 11 A second loose oxide medium layer 7 is deposited on the substrate 1 to fill each of the grooves 61, and also fills each of the corresponding grooves 62, and covers the top surface of the remaining third sidewall 243, the remaining fourth sidewall 244 of each of the second pseudo gates 3, and the respective remaining third sidewall 243 and the remaining fourth sidewall 244 of the nitride medium layer 4.

[0074] In step S3 of some embodiments, the second loose oxide medium layer 7 is formed by pure water bubbling wet oxidation or flash evaporation wet oxidation deposition, which is a conventional technique used by those skilled in the art.

[0075] In step S4 of some embodiments, when the substrate 1 is provided with a plurality of the first dummy gates 2, refer to Figure 2 , Figures 11 to 13Chemical mechanical polishing (CMP) is performed with the top surface of each of the first amorphous silicon layers 21 as the stopping position to expose the top surface of each of the first amorphous silicon layers 21 and further reduce the distance between the remaining first sidewalls 241, each of the second sidewalls 242, and the nitride dielectric layer 4 corresponding to the remaining first sidewalls 241 and each of the second sidewalls 242 and the top surface of the substrate 1. Then, the remaining second loose oxide dielectric layer 5 is wet etched.

[0076] In step S4 of some embodiments, when the substrate 1 is provided with a plurality of first pseudo-gates 2 and a plurality of second pseudo-gates 3, refer to Figure 2 , Figures 11 to 13 During the chemical mechanical polishing (CMP) process with the top surface of each of the first amorphous silicon layers 21 as the stopping position, the top surface of each of the second amorphous silicon layers 31 is also exposed, and the distance between the remaining third sidewalls 243, each of the fourth sidewalls 244, and the nitride dielectric layer 4 corresponding to covering the remaining third sidewalls 243 and each of the fourth sidewalls 244 and the top surface of the substrate 1 is further reduced.

[0077] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A method for fabricating a pseudo-gate, characterized in that, include: S0: Provide a substrate, the top surface of which is provided with a first dummy gate, the first dummy gate including a first dummy gate and a first sidewall structure disposed opposite to both sides of the first dummy gate, the first dummy gate including a first amorphous silicon layer and a first dummy gate dielectric layer stacked sequentially, and the top of the first dummy gate dielectric layer is exposed. S1: A nitrided dielectric layer covering the exposed surface of the first pseudogate and a first loose oxide dielectric layer covering the exposed surface of the nitrided dielectric layer are sequentially deposited on the substrate; S2: Grind the first loose oxide dielectric layer until the vertical distance between the top surface of the first loose oxide dielectric layer and the top surface of the first pseudo gate dielectric layer reaches a preset value, and then etch the first loose oxide dielectric layer and part of the nitride dielectric layer with the first pseudo gate dielectric layer as the stop layer, wherein the preset value is greater than 0. S3: Using the first amorphous silicon layer as a stop layer, etch the first pseudo-gate dielectric layer, part of the first sidewall structure and part of the nitride dielectric layer to form a groove, and deposit a second loose oxide dielectric layer on the substrate to fill the groove; S4: Grind the first amorphous silicon layer as the stop layer, and then etch away the remaining second loose oxide dielectric layer.

2. The pseudo-gate fabrication method according to claim 1, characterized in that, In step S2, the step of grinding the first loose oxide medium layer includes: Grind the first loose oxide dielectric layer until the vertical distance between the top surface of the first loose oxide dielectric layer and the top surface of the first pseudo gate dielectric layer is 50-150 angstroms.

3. The pseudo-gate fabrication method according to claim 1, characterized in that, In step S2, the step of etching the first loose oxide dielectric layer and part of the nitride dielectric layer using the first pseudo-gate dielectric layer as a stop layer includes: Dry etching is performed using an etching gas with an etching selectivity ratio of 1:1 between the first porous oxide dielectric layer and the nitride dielectric layer.

4. The pseudo-gate fabrication method according to claim 1, characterized in that, The first dummy gate dielectric layer includes a first dummy gate nitride dielectric layer and a first dummy gate oxide dielectric layer stacked sequentially from the top surface of the first amorphous silicon layer, with the top of the first dummy gate oxide dielectric layer exposed. In step S3, the step of etching the first dummy gate dielectric layer, a portion of the first sidewall structure, and a portion of the nitride dielectric layer using the first amorphous silicon layer as a stop layer includes: After etching the first pseudo-gate oxide dielectric layer with the first pseudo-gate nitrided dielectric layer as the stop layer, the first pseudo-gate nitrided dielectric layer, part of the first sidewall structure, and part of the nitrided dielectric layer are etched with the first amorphous silicon layer as the stop layer.

5. The pseudo-gate fabrication method according to claim 4, characterized in that, The top surface of the substrate is further provided with a second dummy gate, which includes a second dummy gate and a second sidewall structure disposed opposite to both sides of the second dummy gate. The second dummy gate includes a second amorphous silicon layer and a second dummy gate dielectric layer stacked sequentially from the top surface of the substrate. The top of the second dummy gate dielectric layer is exposed and its top surface is lower than the top surface of the first dummy gate dielectric layer. In step S1, the step of sequential deposition on the substrate is performed so that the formed nitride dielectric layer also covers the exposed surface of the second dummy gate and the exposed surface of the substrate.

6. The pseudo-gate fabrication method according to claim 5, characterized in that, After step S2 is completed, grinding is performed with the second pseudo-gate dielectric as the stopping position until the top surface of the remaining first pseudo-gate dielectric layer and the top surface of the second pseudo-gate dielectric layer are flush, and then step S3 is performed.

7. The pseudo-gate fabrication method according to claim 6, characterized in that, In step S3, during the etching step with the first amorphous silicon layer as the stop layer, the second pseudo-gate dielectric layer, part of the second sidewall structure, and part of the nitride dielectric layer are also removed to form a corresponding groove. The step of depositing on the substrate further causes the second loose oxide dielectric layer to fill the corresponding groove.

8. The pseudo-gate fabrication method according to any one of claims 5 or 7, characterized in that, The second pseudo-gate dielectric layer includes a second pseudo-gate nitride dielectric layer and a second pseudo-gate oxide dielectric layer stacked sequentially from the top surface of the second amorphous silicon layer. In step S3, the step of etching with the first pseudo-gate nitride dielectric layer as the stop layer also removes the second pseudo-gate oxide dielectric layer. The step of etching with the first amorphous silicon layer as the stop layer also removes the second pseudo-gate nitride dielectric layer, part of the second sidewall structure, and part of the nitride dielectric layer.

9. The pseudo-gate fabrication method according to claim 7, characterized in that, In step S4, the grinding step with the first amorphous silicon layer as the stop layer also exposes the top surface of the second amorphous silicon layer.

10. The pseudo-gate fabrication method according to any one of claims 1 or 5, characterized in that, Before performing step S1, a nickel-silicon layer is deposited on the substrate to cover the exposed surface of the substrate, the first dummy gate exposed surface, and / or the second dummy gate exposed surface.

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