Si-sic power integrated module with low parasitic inductance

Abstract

This invention discloses a low parasitic inductance Si-SiC power integrated module, whose circuit structure includes a three-phase inverter circuit, a braking circuit, and a three-phase rectifier circuit. Specific components include silicon-based IGBT chips, silicon carbide SBD chips, silicon-based FRD chips, silicon-based rectifier diode chips, copper-clad ceramic substrates, solder layers, bonding wires, copper pads, and lead electrodes. The three-phase inverter circuit of this invention uses three sets of DC bus lead electrodes connected to the collectors of each phase of the upper bridge arm, ensuring low parasitic inductance in the three-phase power commutation circuit and meeting the requirements for balanced three-phase operation. In the braking circuit, the gate of the IGBT chip is placed near the edge of the lead frame of the copper-clad ceramic substrate, and a partial double-layer substrate structure is adopted, i.e., copper sheets are used instead of the emitter bonding wires of the braking circuit, reducing the parasitic inductance of the gate circuit and the parasitic inductance of the power commutation circuit.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a Si-SiC power integrated module with low parasitic inductance. Background Technology

[0002] Power integrated modules (PIMs) encapsulate rectifier circuits, braking circuits, and inverter circuits within a single module to meet the requirements of high-current, high-power applications. They offer advantages such as small size, light weight, and low switching losses, and have garnered significant attention in recent years. With the development of third-generation semiconductors, the use of silicon carbide (SiC) devices instead of silicon (Si) devices in power modules can improve power density and reduce power losses. However, this also places higher demands on the packaging technology of power integrated modules. Hu Juan et al., in Chinese patent application 202110426392.8, increased the internal layout space of the Si-SiC power integrated module by replacing the silicon-based FRD chip in the inverter circuit with a silicon carbide-based SBD chip. They also used Cu / GN heterostructure thin films instead of local bonding wires to dissipate localized heat from the IGBT chip in the chopper circuit of the high-power PIM through two thermal conduction paths, reducing the temperature of localized hot spots on the chip. Simultaneously, graphene was uniformly added to epoxy resin as a potting material, thereby reducing the overall thermal resistance of the high-power PIM from the chip to the environment and improving heat dissipation efficiency. The increasing switching frequency of silicon carbide-based power semiconductor devices leads to a greater impact from parasitic parameters, increased switching losses, and increased EMI. At the instants of device switching on and off, parasitic inductance generates a significant voltage, which, combined with the device's own voltage or current, affects its normal operation and increases EMI. This accelerates device aging and may even cause device failure. Furthermore, the presence of parasitic parameters also increases device losses.

[0003] To reduce the parasitic inductance of the power module caused by packaging and maintain the ease of processing of traditional packaging structures, this invention optimizes the internal chip layout of the Si-SiC power module, rationally sets the pin electrode positions, and adopts a local double-layer substrate method to reduce the parasitic inductance of the inverter circuit's commutation loop and ensure the balance of the three-phase circuit inductance. It also reduces the gate circuit inductance and common-source parasitic inductance of the braking circuit, thereby improving the electrical performance of the Si-SiC power integrated module. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, this invention provides a low-parasitic-inductance Si-SiC power integrated module. The inverter circuit effectively ensures consistent U, V, and W phase routing internally, with a smaller power commutation loop, resulting in low and balanced parasitic inductance. Furthermore, the gate circuit parasitic inductance and common-emitter parasitic inductance are further reduced in the braking circuit.

[0005] To achieve the above objectives, this invention discloses a Si-SiC power integrated module with low parasitic inductance, which includes a three-phase inverter circuit, a braking circuit, and a three-phase rectifier circuit in terms of circuit structure.

[0006] All circuits are fabricated on a copper-clad ceramic substrate. Several copper substrates are etched onto the surface of the copper-clad ceramic substrate as wiring layers, and pin electrodes are soldered onto a portion of these copper substrates as lead frames. In the three-phase inverter circuit, each phase (U, V, W) has a dedicated DC bus pin electrode. The upper bridge arm is soldered to the same copper substrate, with three sets of pin electrodes leading out and connected to the positive terminal of an external DC voltage source. The lower bridge arm is soldered to three different copper substrates. Each phase is connected to three different lead frame copper substrates via bonding wires, with three sets of pin electrodes leading out and connected to the negative terminal of an external DC voltage source. The cathode of the silicon-based FRD chip in the braking circuit... The collector of the silicon-based IGBT chip in the braking circuit is soldered onto a copper substrate on the upper bridge arm of the three-phase inverter circuit, close to the upper bridge arm chip of the U phase, and shares the same pin electrode with the upper bridge arm of the U phase to connect to the positive terminal of the external DC voltage source; the collector of the silicon-based IGBT chip in the braking circuit is soldered onto another copper substrate, which is connected to the anode of the silicon-based FRD chip through a bonding wire and leads out the output pin electrode of the braking circuit; next to the emitter of the silicon-based IGBT chip in the braking circuit, there is a lead frame copper substrate with the negative terminal of the external DC voltage source, and the emitter of the silicon-based IGBT chip and the lead frame copper substrate with the negative terminal of the external DC voltage source are connected by a copper sheet.

[0007] The three-phase inverter circuit, braking circuit, and three-phase rectifier circuit are arranged from left to right on the copper-clad ceramic substrate.

[0008] In the three-phase inverter circuit, the collectors of the three silicon-based IGBT chips and the cathodes of the three silicon carbide-based SBD chips in the upper arms of the U, V, and W phases are soldered onto the same copper substrate. The three sets of chips are arranged side by side from left to right with the same layout. The three silicon-based IGBT chips are located near the upper edge of the copper-clad ceramic substrate, with the gates of the IGBT chips facing outwards. The three silicon carbide-based SBD chips are located at equal intervals below the three silicon-based IGBT chips. Three sets of pin electrodes are led out from the copper substrate to the right of the three silicon carbide-based SBD chips, serving as the positive pins of the DC voltage source for the U, V, and W phases. Each set of pin electrodes has two electrodes. The emitters of the three IGBT chips in the upper arms and the anodes of the three silicon carbide-based SBD chips are connected by bonding wires, and the anodes of the silicon carbide SBD chips are connected to the copper substrate of the lower arm by bonding wires.

[0009] In the lower arm of the three-phase inverter circuit, three silicon-based IGBT chips and three silicon carbide-based SBD chips are paired up and located below the main phase chip in the upper arm. The three groups of chips are arranged side by side from left to right with the same layout. The three silicon-based IGBT chips are located near the lower edge of the copper-clad ceramic substrate, with the gates of the silicon-based IGBT chips facing outwards. The three silicon carbide-based SBD chips are located at equal intervals above the three silicon-based IGBT chips. The three groups of chips are located on three different copper substrates. The collectors of the silicon-based IGBT chips and the cathodes of the SBD chips are soldered to their respective copper substrates. The emitters of the silicon-based IGBT chips and the anodes of the silicon carbide SBD chips are connected by bonding wires. The emitters of the IGBT chips are also connected to the three lead frame copper substrates by bonding wires. Each copper substrate has a set of pin electrodes connected to the negative terminal of a DC voltage source.

[0010] In a three-phase inverter circuit, the U, V, and W phases use different DC bus pin electrodes, and the DC bus pin electrodes are located at the edge of the copper-clad ceramic substrate, close to their respective silicon-based IGBT chips. The power commutation circuits of each phase are independent of each other, and the commutation circuit path shape remains consistent.

[0011] In the braking circuit, the copper substrate of the lead frame of the external DC voltage source negative terminal is located between the silicon-based IGBT chip and the three-phase rectifier circuit. A copper pad with the same thickness as the silicon-based IGBT chip is placed on the copper substrate of the lead frame of the external DC voltage source negative terminal. A copper sheet is welded to the emitter of the silicon-based IGBT chip and the upper surface of the copper pad to connect the two, forming a double-layer substrate structure. The emitter pin electrode of the silicon-based IGBT chip in the braking circuit is led out through the copper substrate of the lead frame of the external DC voltage source negative terminal, and connected to the negative terminal of the external DC bus. The gate of the silicon-based IGBT chip in the braking circuit is close to the lower edge of the copper-clad ceramic substrate and is connected to the lead frame copper substrate at the lower edge through bonding wires.

[0012] In the three-phase rectifier circuit, the cathodes of the three silicon-based rectifier diode chips in the upper arm common cathode group are soldered onto the same copper substrate. The copper substrate has lead-out electrodes as the positive terminal of the rectified output. The cathodes of the three silicon-based rectifier diode chips in the lower arm common anode group are soldered onto three copper substrates respectively. The anodes of the upper arm silicon-based rectifier diode chips are connected to the three copper substrates where the lower arm silicon-based rectifier diode chips are located via bonding wires. The three copper substrates have lead-out electrodes of three sets, which are connected to a three-phase AC power supply. The anodes of the three diodes in the lower arm are connected together via bonding wires and connected to another separate copper substrate. The copper substrate has lead-out electrodes as the negative terminal of the rectified output.

[0013] Compared with the prior art, the beneficial effects of the present invention are:

[0014] 1. The upper arm of the three-phase inverter circuit of this invention uses three sets of pin electrodes as the positive DC bus pins for the U-phase, V-phase, and W-phase, respectively. This ensures that the internal wiring of the U, V, and W phases of the inverter circuit is identical when an external DC voltage source is applied, resulting in a uniform three-phase power commutation circuit structure and minimizing the current return path. This reduces the parasitic inductance of the three-phase inverter circuit's commutation circuit, minimizing overshoot and oscillation during IGBT turn-on and turn-off, and ensuring safe operation of the inverter circuit. Furthermore, the identical return path ensures that the parasitic inductance of the three phases is essentially the same, thereby guaranteeing balanced operation of the three-phase current.

[0015] 2. This invention employs a silicon carbide-based SBD to reduce switching losses and simplify the layout of the braking circuit. A partial double-layer substrate structure is used in the braking circuit, replacing the traditional copper bonding wire from the emitter to the pin electrode in the package. This partial double-layer substrate structure reduces the gate loop inductance and common-emitter parasitic inductance of the braking circuit. Consequently, the switching overshoot caused by parasitic inductance during braking circuit operation is reduced.

[0016] 3. The present invention employs the aforementioned partial double-layer substrate structure in the braking circuit, which allows the heat generated by the IGBT chip to be dissipated simultaneously from the upper and lower surfaces of the chip, thereby improving the heat dissipation efficiency of the module. Attached Figure Description

[0017] Figure 1 This is the internal equivalent circuit diagram of the present invention.

[0018] Figure 2 This is a top view of the internal layout of the present invention.

[0019] Figure 3 This is a side view of the internal layout of the present invention.

[0020] Figure 4 This is a diagram showing the internal planar layout and pin position markings of an embodiment of the invention that does not display the bonding wires.

[0021] Figure 5 This is a cross-sectional schematic diagram of the present invention.

[0022] Figure 6 Side view of the layout structure of a braking circuit with low parasitic inductance without pins.

[0023] Figure 7 It is a converter circuit for the inverter circuit of a Si-SiC power integrated module with low parasitic inductance.

[0024] Figure 8 The inverter circuit converter loop of the Si-SiC power integrated module has a conventional layout. Detailed Implementation

[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0026] In the various figures, the same components are represented by the same reference numerals. For ease of explanation, the pin names appearing in this invention are specifically described in the following table, see below. Figure 4 .

[0027] Table 1 Pin Description of Si-SiC Power Integrated Module

[0028] Pin Name describe P The positive terminal of the DC voltage source output by the rectifier circuit N The negative terminal of the DC voltage source output by the rectifier circuit L1, L2, L3 Three-phase AC power input terminal of rectifier circuit P1 The U-phase of the inverter circuit and the positive terminal of the external DC voltage source are connected to the braking circuit. P2 The inverter circuit has an external DC voltage source connected to the positive terminal of phase V. P3 The positive terminal of the external DC voltage source for the W phase of the inverter circuit NB The negative terminal of the external DC voltage source for the braking circuit EU The inverter circuit's U-phase is connected to the negative terminal of an external DC voltage source. EV The inverter circuit is connected to the negative terminal of an external DC voltage source in phase V. EW The inverter circuit is connected to the negative terminal of an external DC voltage source in phase W. U U-phase output of inverter circuit V Inverter circuit V-phase output W Inverter circuit W-phase output B Braking circuit output GB Braking circuit gate input G1 Inverter circuit U-phase upper bridge arm gate input G2 Inverter circuit U-phase lower bridge arm gate input G3 Inverter circuit V-phase upper bridge arm gate input G4 Inverter circuit V-phase lower bridge arm gate input G5 Inverter circuit W-phase upper bridge arm gate input G6 Inverter circuit W-phase lower bridge arm gate input

[0029] The internal equivalent circuit of the low parasitic inductance Si-SiC power integrated module proposed in this invention is as follows: Figure 1 As shown, from left to right, they are a three-phase rectifier circuit 3, a braking circuit 2, and a three-phase inverter circuit 1.

[0030] The three-phase AC power supply is connected to the AC input pins L1, L2 and L3 of the three-phase rectifier circuit 3. The three-phase rectifier circuit 3 is composed of six silicon-based rectifier diodes. The rectified DC signal is led out through the DC voltage source pins P and N.

[0031] The braking circuit 2 consists of a silicon-based IGBT chip and a silicon-based FRD chip. The gate GB of the IGBT is connected to an external control signal to control the on / off state of the IGBT. The emitter NB of the IGBT is connected to the negative terminal of an external DC voltage source. The cathode P1 of the silicon-based FRD chip is connected to the positive terminal of an external DC voltage source. The anode of the silicon-based FRD chip is connected to the collector of the silicon-based IGBT chip and is led out through pin B.

[0032] The three-phase inverter circuit 1 consists of six silicon-based IGBT chips and six silicon carbide-based SBDs, divided into three phases: U, V, and W. Each IGBT is connected in parallel with an SBD to form a bridge arm, and the upper and lower bridge arms are connected in series to form a phase. Each IGBT is controlled to turn on and off by an external gate drive signal. The collector of the upper bridge arm IGBT is connected to the positive terminal P1, P2, P3 of the external DC voltage source, and the emitter of the lower bridge arm IGBT is connected to the negative terminal EU, EV, EW of the external DC voltage source. The pin electrodes U, V, and W are led out through the connection point of the upper and lower bridge arms (i.e., the connection point of the emitter of the upper bridge arm IGBT and the collector of the lower bridge arm IGBT) and connected to the three-phase load. The gate pins G1, G2, G3, G4, G5, and G6 of the six IGBTs are connected to external control signals to control the on and off of the IGBTs. When the three-phase inverter circuit 1 is working, the power commutation loops of each phase are staggered. That is, the upper bridge arm IGBT and the lower bridge arm SBD form one power commutation loop, while the lower bridge arm IGBT and the upper bridge arm diode IGBT form another power commutation loop. The entire inverter circuit has a total of six power commutation loops. To reduce the parasitic inductance of the loop, it is necessary to reduce the corresponding power commutation loop path.

[0033] The top and side views of the internal layout of the low parasitic inductance Si-SiC power integrated module proposed in this invention are as follows: Figure 2 and Figure 3 As shown, in order to present the internal layout structure more clearly, Figure 4 The bonding wires have been removed and the pin names are labeled. The internal structure of this invention module includes a silicon-based IGBT chip, a silicon carbide SBD chip, a silicon-based FRD chip, a silicon-based rectifier diode chip, a copper-clad ceramic substrate (DBC), a solder layer, bonding wires, copper pads, and pin electrodes. Pins U, V, W, G1, G3, and L1 are located at the upper edge of the DBC, while EU, EV, EW, G2, G4, G6, GB, and N are located at the lower edge of the DBC.

[0034] A three-phase inverter circuit 1, a braking circuit 2, and a three-phase rectifier circuit 3 are distributed sequentially from left to right on the copper-clad ceramic substrate 11, with the three-phase inverter circuit 1 occupying more than half of the area. Several copper substrates are etched onto the copper-clad ceramic substrate 11 as wiring layers. A solder layer 13 is coated on the surface of the copper substrate wiring layers. Silicon-based diode FRD chips, silicon carbide diodes SBDs, silicon-based rectifier diode chips, and silicon-based IGBT chips are mounted face down on their respective positions on the DBC copper substrate. Leads 16 are soldered to corresponding positions on the copper substrate wiring layers. The copper substrate with soldered lead electrodes is also called a lead frame copper substrate. The connection relationship of each copper substrate will be described in the embodiment, and the reference numerals are 4-9, 15, and 17-21. Copper substrates 4-7 are located on the left side of the copper-clad ceramic substrate 11, copper substrates 17-21 are located on the right side of the copper-clad ceramic substrate 11, and copper substrates 8, 9, and 15 are sandwiched between them.

[0035] like Figure 4 As shown, the three-phase inverter circuit 1 includes three phases: U, V, and W. Each phase consists of two bridge arms, an upper arm and an lower arm. The third IGBT chip 1-3 and the third SBD chip 1-9 form the upper arm of phase U, and the sixth IGBT chip 1-6 and the sixth SBD chip 1-12 form the lower arm of phase U. The second IGBT chip 1-2 and the second SBD chip 1-8 form the upper arm of phase V, and the fifth IGBT chip 1-5 and the fifth SBD chip 1-11 form the lower arm of phase V. The first IGBT chip 1-1 and the first SBD chip 1-7 form the upper arm of phase W, and the fourth IGBT chip 1-4 and the fourth SBD chip 1-10 form the lower arm of phase W.

[0036] In the three-phase inverter circuit 1, the IGBT chips and SBD chips of the three upper arms of phases U, V, and W are soldered onto the same copper substrate 7. The collectors of the third IGBT chip 1-3 of phase U, the second IGBT chip 1-2 of phase V, and the first IGBT chip 1-1 of phase W are soldered onto the copper substrate 7. The cathodes of the third SBD chip 1-9 of phase U, the second SBD chip 1-8 of phase V, and the first SBD chip 1-7 of phase W are soldered onto the copper substrate 7. A pin electrode P3 is led out from the right side of the first SBD chip 1-7 as the positive terminal of the external DC voltage for phase W. A pin electrode P2 is led out from the right side of the second SBD chip 1-8 as the positive terminal of the external DC voltage for phase V. A pin electrode P1 is led out from the right side of the second SBD chip 1-9 as the positive terminal of the external DC voltage for phase U. Since the current passing through electrodes P1, P2, and P3 is very large, two electrodes are used as a group to improve the current carrying capacity. To reduce loop inductance, the three pin electrodes should be placed as close as possible to the SBD chip, and the spacing between the U, V, and W phase chips and pin electrodes should be as equal as possible to ensure consistent three-phase loop area. This effectively ensures that the internal wiring of the external DC voltage source entering the inverter circuit is identical, resulting in a similar three-phase power commutation circuit structure and minimizing the current return path. This reduces the parasitic inductance of the three-phase inverter circuit commutation circuit, and the three-phase parasitic inductances are essentially the same, thus ensuring balanced three-phase operation. The spacing between the three sets of pin electrodes should be kept as consistent as possible. Since the U phase and the braking circuit FRD share a set of electrodes, the positions can be slightly different while considering minimizing the U phase loop inductance and also minimizing the braking circuit loop inductance.

[0037] The emitters of the IGBT chips in the upper arms of the U, V, and W phases are connected to the anodes of the SBD chips via bonding wires. Each emitter is also connected to the corresponding leadframe copper substrate via three bonding wires, with corresponding pins U, V, and W extending from the leadframe copper substrate. Similarly, the gates of the IGBT chips in the upper arms of the U, V, and W phases are connected to the corresponding leadframe copper substrate via bonding wires, with corresponding pins G1, G3, and G5 extending from the leadframe copper substrate. The IGBT chips in each phase are distributed on both sides of the substrate, with the SBD chips placed closer to the center. The gates of the IGBT chips are positioned closer to the outside to minimize the length of the gate leads and reduce gate inductance. Furthermore, the layout of each phase remains largely consistent to ensure uniform three-phase electrothermal parameters and balanced operation.

[0038] The anode of the third SBD chip 1-9 in the upper arm of the U phase is connected to the copper substrate 6 of the lower arm via a bonding wire. The collector of the sixth IGBT chip 1-6 and the cathode of the sixth SBD chip 1-12 in the lower arm of the U phase are soldered to the copper substrate 6. The emitter of the sixth IGBT chip 1-6 and the anode of the sixth SBD chip 1-12 are connected via a bonding wire. The emitter and gate of the sixth IGBT chip 1-6 are connected to the corresponding lead frame copper substrate via a bonding wire. The corresponding pin electrodes EU and G2 are led out from the copper substrate.

[0039] The anode of the second SBD chip 1-8 in the upper arm of the V phase is connected to the copper substrate 5 of the lower arm via a bonding wire. The collector of the fifth IGBT chip 1-5 and the cathode of the fifth SBD chip 1-11 in the lower arm of the V phase are soldered to the copper substrate 5. The emitter of the fifth IGBT chip 1-5 and the anode of the fifth SBD chip 1-11 are connected via a bonding wire. The emitter and gate of the fifth IGBT chip 1-5 are connected to the corresponding lead frame copper substrate via a bonding wire. The corresponding pin electrodes EV and G4 are led out from the copper substrate.

[0040] The anode of the first SBD chip 1-7 in the upper arm of phase W is connected to the copper substrate 4 of the lower arm via a bonding wire. The collector of the fourth IGBT chip 1-4 and the cathode of the fourth SBD chip 1-10 in the lower arm of phase W are soldered to the copper substrate 4. The emitter of the fourth IGBT chip 1-4 and the anode of the fourth SBD chip 1-10 are connected via a bonding wire. The emitter and gate of the fourth IGBT chip 1-4 are connected to the corresponding lead frame copper substrate via a bonding wire. The corresponding pin electrodes EW and G6 are led out from the lead frame copper substrate.

[0041] The braking circuit 2 is composed of a seventh silicon-based IGBT chip 2-1 and a silicon-based FRD chip 2-2, and adopts a partial double-layer substrate structure.

[0042] In braking circuit 2, the cathode of FRD chip 2-2 is soldered to the upper bridge arm of three-phase inverter circuit 1 on the same copper substrate 7. FRD chip 2-2 is located to the right of SBD chip 1-9. A pin electrode P1, the positive terminal of the external DC voltage source shared by the U phase of three-phase inverter circuit 1 and braking circuit 2, is led out between FRD chip 2-2 and SBD chip 1-9. The collector of the seventh silicon-based IGBT chip 2-1 in braking circuit 2 is soldered to copper substrate 8, and this copper substrate 8 is connected to the anode of silicon-based FRD chip 2-2 via bonding wires. The gate of the seventh silicon-based IGBT chip 2-1 is connected to the corresponding lead frame copper substrate 15 via bonding wires, and the corresponding pin electrode GB is led out. Figure 5As shown in Figure 6, the emitter of the seventh silicon-based IGBT chip 2-1 is connected to the copper pad 14 via a copper sheet 10. The copper pad 14 has the same thickness as the seventh silicon-based IGBT chip 2-1. The copper pad 14 is then soldered to the copper substrate 9, and the pin electrode NB is led out from the copper substrate 9 to connect to the negative terminal of the external DC bus. The copper sheet 10 is equivalent to a copper substrate replacing the bonding wire from the emitter to the copper substrate of the lead frame in the traditional packaging method, so that the module forms a partial double-layer substrate structure, thereby reducing the common-emitter parasitic inductance of the braking circuit 2. At the same time, the gate is located at the lower right corner of the IGBT chip, near the lower edge of the DBC, and is connected to the copper substrate at the lower edge of the DBC via a bonding wire, thereby reducing the gate loop parasitic inductance of the braking circuit.

[0043] The three-phase rectifier circuit 3 consists of six silicon-based rectifier diode chips, arranged in pairs to form three phases. Each pair is divided into an upper arm and a lower arm. The cathodes of the three silicon-based rectifier diodes in the upper arm are connected together to form a common cathode group, and the anodes of the three silicon-based rectifier diodes in the lower arm are connected together to form a common anode group. The common cathode group in the upper arm consists of silicon-based rectifier diode chips 3-4, 3-5, and 3-6, and the common anode group in the lower arm consists of silicon-based rectifier diode chips 3-1, 3-2, and 3-3.

[0044] In the upper arm of the three-phase rectifier circuit 3, the cathodes of the three silicon-based rectifier diode chips in the common cathode group are soldered onto the same copper substrate 20. A lead electrode P is led out from the lower part of the copper substrate 20 as the positive terminal of the rectified output. In the lower arm, the cathodes of the silicon-based rectifier diode chips in the common anode group are soldered onto three different copper substrates 17, 18, and 19. Copper substrate 17 is connected to silicon-based rectifier diode chip 3-4 via bonding wires, copper substrate 18 is connected to silicon-based rectifier diode chip 3-5 via bonding wires, and copper substrate 19 is connected to silicon-based rectifier diode chip 3-6 via bonding wires. Lead electrodes L1, L2, and L3 are led out from copper substrates 17, 18, and 19, respectively, for connection to an external three-phase AC power supply. The anodes of the common anode silicon-based rectifier diode chips 3-1, 3-2, and 3-3 are connected together by bonding wires and finally connected to the relatively large lead frame copper substrate 21 (the larger the area in a limited space, the lower the loss resistance). The copper substrate 21 leads out the pin electrode N as the negative terminal of the rectified output.

[0045] In an embodiment of the present invention, in order to improve thermal performance, increase the area of ​​the inverter circuit module, and enable independent operation of the three phases, the copper substrate 7 of the upper bridge arm of the inverter circuit does not use a standard rectangular area. Instead, five small rectangles (hereafter, length represents the horizontal dimension and width represents the vertical dimension) are cut off from a rectangular area with a length of 36-37mm and a width of 15-16mm. The rectangle cut off at the lower left corner has a length of 10-10.5mm and a width of 1.9-2.1mm, the rectangle cut off at the upper right corner has a length of 6-6.4mm and a width of 6-6.4mm, and a rectangle cut off at the lower right corner has a length of 2.8-3.1mm and a width of 6.8-7.2mm. A rectangle with a length of 13.8-14.2mm and a width of 1.9-2.1mm is then cut off to the left of this rectangle. The IGBT chip is 8mm × 8mm in size, and the SBD chip is 3mm × 3mm in size. The first IGBT chip 1-1 is 0.5-0.6mm from the left and top edge of the copper substrate 7, and the spacing between each IGBT chip is approximately 2-2.4mm. The first SBD chip 1-7 is 3-3.4mm from the left and bottom edge of the copper substrate, and the spacing between each diode is 7-7.5mm. A rectangle with a length of 11-11.5mm and a width of 1.4mm-1.6mm is cut off from the copper substrate 7 between the first IGBT chip 1-1 and the third IGBT chip 1-3, so that the position of the upper bridge arm V phase chip is slightly offset from the U and W phases.

[0046] Below the upper bridge arm copper substrate 7, from right to left, are the U-phase lower bridge arm copper substrate 6, the V-phase lower bridge arm copper substrate 5, and the W-phase lower bridge arm copper substrate 4. The U-phase lower bridge arm copper substrate 6 is 9-9.5mm long and 15-16mm wide, with a square cut out from the upper right corner, with a side length of 4-4.3mm. The V-phase lower bridge arm copper substrate 5 is 9-9.5mm long and 13-14mm wide. The W-phase lower bridge arm copper substrate 4 is 9-9.5mm long and 15-16mm wide. The spacing between each lower bridge arm copper substrate is 0.8-1.1mm.

[0047] The copper substrate 8 of the braking circuit IGBT chip is located on the right side of the copper substrate 6 of the lower bridge arm of the U phase. Two rectangles are cut out in a rectangular area with a length of 13.5-14mm and a width of 15-16mm. A rectangle with a length of 5.5-6mm and a width of 3-3.5mm is cut out from the lower left corner, and a rectangle with a length of 10-11mm and a width of 7-7.5mm is cut out vertically from the upper right corner.

[0048] The copper substrate 20 containing the common cathode group of the upper bridge arm in the three-phase rectifier circuit 3 is 4.9-5.1mm long and 22-23mm wide, located at the right edge of the DBC. The copper substrates 17, 18, and 19 of the common anode group of the lower bridge arm on its left side are arranged from top to bottom. Three small rectangles are cut from a rectangular area of ​​15-16mm long and 9.5-10mm wide on copper substrate 17. The rectangle cut from the upper left corner is 3-3.5mm long and 3.8-4.4mm wide, and the rectangle cut from the lower right corner is 9.5-10mm long and 2.8-3.1mm wide. Adjacent to the lower right rectangle, another rectangle with a length of 5.8-6.3mm and a width of 3.8-4.1mm is cut upwards. In the lower bridge arm common anode group copper substrate 18, two small rectangles are cut out from a rectangular area with a length of 12.5-13.1 mm and a width of 8.8-9.1 mm. A rectangle with a length of 9.8-10.1 mm and a width of 2.8-3.1 mm is cut out from the upper left corner. Adjacent to this rectangle, a rectangle with a length of 2.8-3.1 mm and a width of 5.4-5.6 mm is then cut downwards. The lower bridge arm common anode group copper substrate 19 has a length of 12.8-13.2 mm and a width of 5.8-6.2 mm. The minimum spacing between each copper substrate is 0.9-1.1 mm.

[0049] In this embodiment, the pin electrode 16 is cylindrical with a diameter of 0.64-0.70 mm and a height of 10-14 mm. There is one gate pin electrode, one emitter pin electrode of the braking circuit IGBT chip, and other pin electrodes are in pairs, with a spacing of 1.8-2.4 mm between the two pins.

[0050] In this embodiment, the IGBT chip gate current is very small, so it is connected using a single bonding wire. The power loop current in the three-phase inverter circuit 1 is very large, so three bonding wires are connected in a group to improve current carrying capacity and simultaneously reduce loop inductance. The power loop current of the braking circuit 2 is smaller than that of the three-phase inverter circuit 1, so two bonding wires are used in a group to bond the silicon-based FRD chip to the copper substrate. The rectifier circuit 3 carries a large current, so four bonding wires are used in a group. The bonding wires are made of aluminum, with a diameter of 0.3-0.32 mm, a length of 4.8-5.2 mm, and a height of 0.3-0.56 mm.

[0051] The upper arm power commutation circuit of the three-phase inverter circuit 1 of the present invention is as follows: Figure 7 As shown, Figure 8This paper presents the upper arm power commutation circuit of a conventional three-phase inverter circuit. The power commutation path is the path with the least power loop impedance. Under DC excitation, the impedance is mainly resistance; therefore, the return path is the path with the least resistance, which is the straight segment connecting the terminals of each power device. This invention considers the parasitic inductance caused by the internal layout of the module and applies excitation at the positive and negative terminals of the external DC voltage source, i.e., the input (Source) and output (Sink) terminals of the excitation source marked in the figure. In conventional modules, the upper arm and the braking circuit share a DC bus positive pin electrode. This pin electrode is close to the collector of the U-phase upper arm IGBT chip but far away from the V and W phases. Therefore, the U-phase power commutation circuit is the smallest, while the W-phase commutation circuit is the largest. Furthermore, the power commutation circuits of the V and W phases partially overlap, meaning that the current in this part is twice the single-phase current. Therefore, the parasitic inductance of the power commutation circuit in phase W will be very large, while the parasitic inductance of phase U will be relatively small. This will result in a large voltage overshoot when the IGBT chips in phases W and V are turned off. In addition, the current in the overlapping part is doubled, and the change in current is doubled, which will further increase the voltage overshoot of phases V and W. Figure 7 In the inverter circuit of the Si-SiC power integrated module with low to medium parasitic inductance, the U, V, and W phases use different DC bus pins, and each power commutation circuit is completely independent. The positive pin of the DC bus is close to the collector of the upper bridge arm IGBT chip. The power commutation circuits of each phase are very small, and the three phases have basically the same shape, resulting in low parasitic inductance and small differences in parasitic inductance between phases. The voltage overshoot generated at the moment of collector turn-off of the U, V, and W phase IGBT chips is relatively small, and the operating state of the three phase IGBT chips is relatively balanced.

[0052] The power commutation circuit of the lower arm of the three-phase inverter circuit is not shown because the IGBT chip of the lower arm and the SBD chip of the upper arm form a commutation circuit. Therefore, when the commutation circuit passes through the upper arm, it only needs to pass through the silicon carbide-based SBD chips 1-7, 1-8, and 1-9, and does not need the topmost IGBT chips 1-1, 1-2, and 1-3. The commutation circuit is not much different from the commutation circuit of the IGBT chip of the upper arm.

[0053] In this embodiment, the gate of the braking circuit IGBT chip is placed on the lower right side, making the distance between the gate and the lead frame closer. Using shorter bonding wires reduces the parasitic inductance of the gate. The emitter of the braking circuit IGBT chip uses a copper sheet instead of bonding wires. While the current path length remains relatively unchanged, the conductive area is increased, thereby reducing the parasitic inductance of the emitter.

[0054] To verify the low parasitic inductance characteristic of the embodiments of the present invention, the parasitic inductance of a commercial module and the embodiments of the present invention were simulated using software modeling. The parasitic inductance of the power circuit given in the datasheet of the commercial module is 30nH. The parasitic inductances of the upper arm power circuits of the U, V, and W phases of the commercial module in the modeling simulation are 18.88nH, 23.40nH, and 29.48nH, respectively, and the parasitic inductances of the lower arm power circuits of the U, V, and W phases are 15.82nH, 20.24nH, and 26.41nH, respectively. The parasitic inductances of the upper arm power circuits of the U, V, and W phases of the embodiments of the present invention in the modeling simulation are 14.22nH, 12.92nH, and 14.496nH, respectively, and the parasitic inductances of the lower arm power circuits of the U, V, and W phases are 17.56nH, 16.08nH, and 17.68nH, respectively. The simulated commercial module braking circuit has a gate parasitic inductance of 9.28 nH and a common-emitter parasitic inductance of 3.77 nH. The simulated braking circuit of this invention has a gate parasitic inductance of 3.80 nH and a common-emitter parasitic inductance of 1.77 nH. The average parasitic inductance of the inverter circuit power loops decreased by 30.8%, and the maximum decreased by 40.0%. Simultaneously, the difference in parasitic inductance among the six power loops in the three phases decreased from 46.4% to 26.9%. The gate inductance and emitter inductance of the braking circuit decreased by 59.1% and 53.1%, respectively.

[0055] The proposed low parasitic inductance Si-SiC power integrated module structure utilizes a silicon carbide-based SBD in the inverter circuit to reduce recovery losses while providing more space for other circuits and expanding the heat dissipation area. Three pin electrodes are led out from the upper bridge arm of the inverter circuit, making the U, V, and W phase power commutation circuits independent, reducing the commutation circuit length, and ensuring uniformity across the three phases, thus achieving reduced and uniform parasitic inductance. The optimized layout in the braking circuit reduces the gate conductor length and parasitic inductance. A partial double-layer substrate structure replaces the emitter bonding wire, significantly reducing the common-emitter parasitic inductance, thereby improving the switching performance of the power module, minimizing voltage fluctuations during switching, reducing losses, and utilizing the power module's heat dissipation capabilities.

Claims

1. A low parasitic inductance Si-SiC power integrated module, comprising a three-phase inverter circuit (1), a braking circuit (2), and a three-phase rectifier circuit (3) fabricated on a copper-clad ceramic substrate (11), wherein the three-phase inverter circuit (1) comprises six silicon-based IGBT chips and six silicon carbide SBD chips, one silicon-based IGBT chip and one silicon carbide SBD chip constitute a group, a total of six groups, two groups constitute one phase circuit, a total of three phases, referred to as U phase, V phase and W phase respectively, the upper and lower groups in each phase are referred to as upper bridge arm and lower bridge arm respectively; the braking circuit (2) comprises one silicon-based IGBT chip and one silicon-based FRD chip; the three-phase rectifier circuit (3) comprises six silicon-based rectifier diodes, two in a group to form three phases, each group is divided into upper arm and lower arm, the cathodes of the three silicon-based rectifier diodes in the upper arm of the three phases are connected together to form a common cathode group, and the anodes of the three silicon-based rectifier diodes in the lower arm of the three phases are connected together to form a common anode group; characterized in that, The surface of the copper-clad ceramic substrate (11) is etched with several copper substrates as wiring layers, and pin electrodes are soldered on a portion of the copper substrates as lead frames; in the three-phase inverter circuit (1), each phase U, V, and W has a dedicated DC bus pin electrode, the upper bridge arm is soldered on the same copper substrate, and three sets of pin electrodes are led out to the positive terminal of the external DC voltage source, the lower bridge arm is soldered on three different copper substrates, and each phase is connected to three different lead frame copper substrates through bonding wires, and three sets of pin electrodes are led out to the negative terminal of the external DC voltage source; the cathode of the silicon-based FRD chip in the braking circuit (2) is soldered on the upper bridge of the three-phase inverter circuit (1). On the copper substrate where the arm is located, it is close to the U-phase upper bridge arm chip and shares the same pin electrode with the U-phase upper bridge arm to the positive terminal of the external DC voltage source; the collector of the silicon-based IGBT chip in the braking circuit (2) is soldered on another copper substrate, which is connected to the anode of the silicon-based FRD chip through a bonding wire and leads out the output pin electrode of the braking circuit (2); a lead frame copper substrate (9) with the negative terminal of the external DC voltage source is provided next to the emitter of the silicon-based IGBT chip in the braking circuit (2), and a copper sheet (10) is used to connect the emitter of the silicon-based IGBT chip to the lead frame copper substrate (9) with the negative terminal of the external DC voltage source.

2. The low parasitic inductance Si-SiC power integrated module according to claim 1, characterized in that: The three-phase inverter circuit (1), braking circuit (2) and three-phase rectifier circuit (3) are arranged from left to right on the copper-clad ceramic substrate (11).

3. The low parasitic inductance Si-SiC power integrated module according to claim 2, characterized in that: In the three-phase inverter circuit (1), the collectors of the three silicon-based IGBT chips and the cathodes of the three silicon carbide-based SBD chips in the upper arm of the U, V, and W phases are soldered onto the same copper substrate. The three sets of chips are arranged side by side from left to right with the same layout. The three silicon-based IGBT chips are located near the upper edge of the copper-clad ceramic substrate (11), and the gates of the IGBT chips face outward. The three silicon carbide-based SBD chips are located at equal intervals below the three silicon-based IGBT chips. Three sets of pin electrodes are led out from the copper substrate on the right side of the three silicon carbide-based SBD chips to serve as the positive pins of the DC voltage source for the U, V, and W phases. There are two pin electrodes in each set. The emitters of the three IGBT chips in the upper arm and the anodes of the three silicon carbide-based SBD chips are connected by bonding wires, and the anodes of the silicon carbide SBD chips are connected to the copper substrate of the lower arm by bonding wires.

4. The low parasitic inductance Si-SiC power integrated module according to claim 3, characterized in that: In the three-phase inverter circuit (1), the three silicon-based IGBT chips and the three silicon carbide-based SBD chips in the lower bridge arm are arranged in pairs below the main phase chip in the upper bridge arm. The three groups of chips are also arranged side by side from left to right with the same layout. The three silicon-based IGBT chips are located near the lower edge of the copper-clad ceramic substrate (11), and the gates of the silicon-based IGBT chips face outwards. The three silicon carbide-based SBD chips are located at equal intervals above the three silicon-based IGBT chips. The three groups of chips are located on three different copper substrates. The collector of the silicon-based IGBT chip and the cathode of the SBD chip are soldered to the copper substrate on which they are located. The emitter of the silicon-based IGBT chip and the anode of the silicon carbide SBD chip are connected by bonding wires. The emitter of the IGBT chip is connected to the three lead frame copper substrates by bonding wires. Each copper substrate leads out a set of pin electrodes to the negative terminal of the DC voltage source.

5. The low parasitic inductance Si-SiC power integrated module according to claim 1, characterized in that: In the three-phase inverter circuit (1), the U, V and W phases adopt different DC bus pin electrodes, and the DC bus pin electrodes are located at the edge of the copper-clad ceramic substrate (11), close to their respective silicon-based IGBT chips. The power converter circuits of each phase are independent of each other, and the converter circuit path shape remains consistent.

6. The low parasitic inductance Si-SiC power integrated module according to claim 2, characterized in that: In the braking circuit (2), the lead frame copper substrate (9) of the external DC voltage source negative terminal is located between the silicon-based IGBT chip and the three-phase rectifier circuit (3). A copper pad (14) with the same thickness as the silicon-based IGBT chip is provided on the lead frame copper substrate (9) of the external DC voltage source negative terminal. A copper sheet (10) is welded to the upper surface of the silicon-based IGBT chip emitter and the copper pad (14) to connect the two, forming a double-layer substrate structure. The emitter pin electrode of the silicon-based IGBT chip of the braking circuit (2) is led out through the lead frame copper substrate (9) of the external DC voltage source negative terminal, and the negative terminal of the external DC bus is connected. The gate of the silicon-based IGBT chip of the braking circuit (2) is close to the lower edge of the copper-clad ceramic substrate (11) and is connected to the lead frame copper substrate at the lower edge through bonding wires.

7. The low parasitic inductance Si-SiC power integrated module according to claim 2, characterized in that: In the three-phase rectifier circuit (3), the cathodes of the three silicon-based rectifier diode chips in the upper arm common cathode group are soldered on the same copper substrate. The copper substrate leads out pin electrodes as the positive terminal of the rectified output. The cathodes of the three silicon-based rectifier diode chips in the lower arm common anode group are soldered on three copper substrates respectively. The anodes of the upper arm silicon-based rectifier diode chips are connected to the three copper substrates where the lower arm silicon-based rectifier diode chips are located through bonding wires. The three copper substrates lead out three sets of corresponding pin electrodes and are connected to a three-phase AC power supply. The anodes of the three diodes in the lower arm are connected together through bonding wires and connected to another separate copper substrate. The copper substrate leads out pin electrodes as the negative terminal of the rectified output.

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