Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises a first transistor, a second transistor and a first interlayer insulating layer between the first transistor and the second transistor. The first transistor comprises a first active layer, and the material of the first active layer is amorphous oxide semiconductor. The second transistor comprises a second active layer, and the material of the second active layer is polycrystalline oxide semiconductor. The display panel and the display device provided by the application have a mixed driving circuit of polycrystalline oxide semiconductor and amorphous oxide semiconductor, the amorphous oxide semiconductor transistor with low leakage current and high uniformity is used as a switching transistor, and the high mobility and low off-leakage current are used as a driving transistor, so that the leakage current is reduced, the first transistor and the second transistor are arranged in different layers, and the first active layer and the second active layer are separated by the first interlayer insulating layer, so that the probability of the two being simultaneously invaded by water and oxygen is reduced, and the stability of the driving circuit is improved.

Description

Technical Field

[0001] This application relates to the field of displays, and more particularly to a display panel and a display device. Background Technology

[0002] LTPO (Low Temperature Poly-Si and Oxide) backplane technology is currently widely used in small-sized wearable devices. Combining the low cutoff current of oxide semiconductor materials with the high carrier mobility of low-temperature poly-silicon (LTPS), LTPO backplane technology can achieve features such as variable refresh rates and always-on displays. However, in large-sized products, uniformity issues arise when manufacturing LTPS using excimer laser annealing (ELA). The non-uniformity of LTPS leading to non-uniformity in thin-film transistor (TFT) characteristics degrades display quality. Furthermore, LTPO backplane technology is costly, hindering mass production of large-sized products. Additionally, the high cutoff current of TFTs driven by polysilicon semiconductor materials remains a problem. Summary of the Invention

[0003] In view of this, this application provides a display panel that can improve the uniformity of thin-film transistor characteristics and reduce the cutoff current.

[0004] This application provides a display panel including a substrate, a first transistor, a first interlayer insulating layer, a second transistor, and a second active layer. The first transistor is disposed on the substrate and includes a first active layer made of amorphous oxide semiconductor. The first interlayer insulating layer covers the side of the first transistor away from the substrate. The second transistor is disposed on the side of the first interlayer insulating layer away from the first transistor and includes a second active layer made of polycrystalline oxide semiconductor.

[0005] Optionally, in some embodiments, the first transistor further includes a first gate insulating layer covering the first active layer, wherein the first gate, first source, and first drain of the first transistor are all located on the side of the interlayer insulating layer away from the second transistor, and on the side of the first gate insulating layer away from the substrate.

[0006] Optionally, in some embodiments, the second transistor includes a second gate insulating layer and a second interlayer insulating layer that sequentially cover the second active layer. The second source and the second drain of the second transistor are disposed on the side of the interlayer insulating layer away from the first transistor and on the side of the second interlayer insulating layer away from the substrate. The second gate is located on the side of the second active layer near the second source.

[0007] Optionally, in some embodiments, the display panel further includes a storage capacitor disposed on the periphery of the second transistor. The storage capacitor includes a first electrode and a second electrode, the first electrode and the second electrode forming a first capacitor, the second electrode being disposed on the same layer as the second active layer, the material of the second electrode being a conductive polycrystalline oxide semiconductor, and the first electrode being disposed on the same layer as the first gate.

[0008] Optionally, in some embodiments, the storage capacitor further includes a third plate, which is located on opposite sides of the second plate, and the third plate and the second plate form a second capacitor, which is connected in parallel with the first capacitor, wherein the third plate and the second drain are disposed on the same layer.

[0009] Optionally, in some embodiments, the storage capacitor further includes a fourth electrode plate disposed on the side of the third electrode plate away from the second electrode plate, the fourth electrode plate and the third electrode plate forming a third capacitor, the third capacitor being connected in parallel with the first capacitor and the second capacitor, and the fourth electrode plate being disposed on the same layer as the anode of the display panel.

[0010] Optionally, in some embodiments, the display panel further includes a storage capacitor disposed on the periphery of the second transistor. The storage capacitor includes a first electrode and a second electrode, the first electrode and the second electrode forming a first capacitor, the second electrode being disposed on the same layer as the second active layer, the material of the second electrode being a conductive polycrystalline oxide semiconductor, and the first electrode being disposed on the same layer as the second drain electrode.

[0011] Optionally, in some embodiments, the display panel further includes a planarization layer located between the second transistor and the anode, the planarization layer having a groove, and the fourth electrode plate located within the groove.

[0012] Optionally, in some embodiments, the display panel further includes a first barrier layer disposed between the first interlayer insulating layer and the second transistor.

[0013] Optionally, in some embodiments, the display panel further includes a buffer layer and a second barrier layer, the buffer layer being located between the substrate and the first active layer, and the second barrier layer being disposed between the buffer layer and the first active layer.

[0014] Optionally, in some embodiments, the second transistor includes a second gate, a second source, and a second drain. The second source and the second drain are disposed on the side of the second active layer away from the substrate, and the second gate is located on the side of the second active layer close to the second source. The display panel further includes a third barrier layer disposed between the second gate and the second active layer.

[0015] This application provides a display device comprising a display panel as described in any of the preceding claims.

[0016] The display panel and display device provided in this application embodiment have a hybrid driving circuit of polycrystalline oxide semiconductor and amorphous oxide semiconductor. Amorphous oxide semiconductor transistors with low leakage current and high uniformity are used as switching transistors, while high mobility and low cutoff leakage current are used as driving transistors, thereby reducing leakage current and improving display quality. The first transistor and the second transistor are disposed on different layers, and the first active layer and the second active layer are separated by a first interlayer insulating layer, reducing the probability of both being simultaneously invaded by water and oxygen, and improving the stability of the driving circuit. On the other hand, the grain size of polycrystalline oxide semiconductors is more uniform than that of LTPS, and it can replace LTPS in large-size display panels and display devices to overcome the technical bottleneck that existing LTPO technology can only be used in small and medium-sized displays. In the future, it can be applied to panels and display devices of G8.5 generation lines and above. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a display panel according to an embodiment of this application.

[0019] Figure 2 This is a schematic diagram of the structure of a display device according to an embodiment of this application.

[0020] Figures 3(a) to 3(j) This is a schematic diagram illustrating the steps of a method for manufacturing a display panel according to an embodiment of this application.

[0021] Figure 4This is a partial top view of the first transistor of a display panel according to an embodiment of this application.

[0022] Figures 5(a) to 5(f) for Figures 3(b) to 3(c) A detailed step-by-step diagram, and Figures 5(a) to 5(f) yes Figure 4 A sectional view along line AA. Detailed Implementation

[0023] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0024] In this application, unless otherwise expressly specified and limited, "above" or "below" a second feature can include the first and second features being directly connected, or it can include the first and second features not being directly connected but contacting each other through another feature between them. Furthermore, "above," "over," and "on top" of a second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" a second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features.

[0025] This application provides a display panel. The display panel can be an organic light-emitting diode (OLED) display panel, specifically, it can be an active matrix organic light-emitting diode (AMOLED) display panel or a passive matrix organic light-emitting diode (PMOLED) display panel.

[0026] The display panel includes a substrate, a first transistor disposed on the substrate, a first interlayer insulating layer covering the side of the first transistor away from the substrate, and a second transistor disposed on the side of the first interlayer insulating layer away from the first transistor. The first transistor includes a first active layer, and the second transistor includes a second active layer.

[0027] The following is for reference. Figure 1 The following is a detailed description of a display panel according to an embodiment of the present application, from bottom to top.

[0028] The display panel 100 includes a substrate 10, a pixel driving circuit 20 disposed on the substrate 10, and a light-emitting layer 30 connected to the pixel driving circuit 20. The pixel driving circuit 20 can be a pixel driving circuit 20 commonly used in the art, such as 2T1C, 3T1C, 5T1C, or 7T1C. In this embodiment, the pixel driving circuit 20 is a 2T1C circuit. The 2T1C pixel driving circuit 20 includes a first transistor T1, a second transistor T2, and a storage capacitor CST connected together. The first transistor T1 is a switching transistor, and the second transistor T2 is a driving transistor.

[0029] Specifically, the display panel 100 includes a substrate 10, a buffer layer BL disposed on the substrate 10, a first barrier layer 21, a first oxide semiconductor layer OS1, a first gate insulating layer GIL1, a first metal layer M1, a first interlayer insulating layer ILD1, a second barrier layer 22, a second oxide semiconductor layer OS2, a third barrier layer 23, a second metal layer M2, a second interlayer insulating layer ILD2, a third metal layer M3, a passivation layer PV, a planarization layer PLN, a bottom electrode layer PE, a pixel definition layer PDL, a light-emitting functional layer EL, and a top electrode layer PE'.

[0030] The substrate 10 is used to support the display element disposed on the substrate 10. The substrate 10 can be glass, plastic, or a flexible substrate 10, etc. Specifically, the flexible substrate 10 can be composed of a single flexible organic layer or two or more flexible organic layers. In one embodiment, the substrate 10 includes a first flexible organic layer, a barrier layer, and a second flexible organic layer stacked sequentially. The materials of the first and second flexible organic layers are selected from polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyaryl ester (PAR), polycarbonate (PC), polyetherimide (PEI), and polyethersulfone (PES). The barrier layer is selected from inorganic materials such as silicon dioxide and silicon nitride. In this embodiment, the substrate 10 is a glass substrate.

[0031] The buffer layer BL is used to enhance the adhesion between the film layer above the substrate 10 and the substrate 10. The material of the buffer layer BL is one of silicon oxide, nitric oxide, silicon oxynitride, or a stack thereof. In this embodiment, the buffer layer BL covers the entire surface of the substrate 10.

[0032] A first barrier layer 21 is disposed between the buffer layer BL and the first oxide semiconductor layer OS1. When hydrogen, water vapor, or oxygen enters the oxide semiconductor layer from a film layer adjacent to it, it can cause degradation of the TFT characteristics. The first barrier layer 21 is used to block external hydrogen, water vapor, or oxygen, preventing the first oxide semiconductor layer OS1 from being affected by hydrogen, water vapor, or oxygen. The material of the first barrier layer 21 is selected from one or a combination of alumina, hafnium oxide, and yttrium oxide.

[0033] The first oxide semiconductor layer OS1 includes a first active layer a-OS. The material of the first active layer a-OS is an amorphous oxide semiconductor. The first active layer a-OS includes a first channel CL1 and a first source portion S1 and a first drain portion D1 located on both sides of the first channel CL1. The first channel CL1 is connected to the first source portion S1 and the first drain portion D1, respectively. Figure 1 As shown, "located on both sides of the first channel CL1" refers to both sides in a direction parallel to the surface of the substrate 10. The first channel CL1 is an amorphous oxide semiconductor, and the first source portion S1 and the first drain portion D1 are conductive amorphous oxide semiconductors. Specifically, the amorphous oxide semiconductor material can be selected from one of indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), gallium indium oxide (IGO), indium gallium tin oxide (IGTO), and indium zinc tin oxide (IZTO), but is not limited to these. In this embodiment, the first barrier layer 21 is configured as a whole-layer structure covering the buffer layer BL. Optionally, the first barrier layer 21 can be disposed only below the first active layer a-OS.

[0034] A first gate insulating layer GIL1 covers the first oxide semiconductor layer OS1 and the first barrier layer 21. A first via TH1 and a second via TH2 are formed in the first gate insulating layer GIL1. The first via TH1 exposes the first source portion S1, and the second via TH2 exposes the first drain portion D1. The first gate insulating layer GIL1 includes a first gate insulating portion GI1, which is located above the first channel CL1 of the first active layer a-OS. The first gate insulating portion GI1 is island-shaped, that is, it is disposed independently of the other portions of the first gate insulating layer GIL1.

[0035] The first metal layer M1 includes a first gate GE1, a first source SE1, a first drain DE1, a light-shielding layer LS, and a first electrode CS1, which are spaced apart and insulated from each other. The first gate GE1, the first source SE1, and the first drain DE1 are the gate, source, and drain of the first transistor T1, respectively. The first gate GE1 is disposed on the island-shaped first gate insulating portion GI1. The first source SE1 extends into the first through-hole TH1 and connects to the first source portion S1, and the first drain DE1 extends into the second through-hole TH2 and connects to the first drain portion D1. The light-shielding layer LS shields the second transistor T2 from light, preventing the second transistor T2 from being affected by light and improving its stability. The first electrode CS1 serves as one electrode of the storage capacitor CST. The first gate GE1, the first source SE1, the first drain DE1, the light-shielding layer LS, and the first electrode CS1 are disposed in the same layer and made of the same material, and can be fabricated with a single photomask, thereby reducing the number of photomasks required to manufacture the display panel 100 of this application and reducing costs. It should be noted that "same-layer arrangement" in this application does not mean that all components are located on the same horizontal plane, but rather that, from the perspective of the film structure, the components "same-layer arrangement" belong to the same film layer. The material of the first metal layer M1 can be selected from copper (Cu), tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), titanium (Ti), nickel (Ni), and their alloys or stacks. The first metal layer M1 can be a single layer or multiple layers. When the first metal layer M1 is multiple layers, it can be a stack of copper (Cu), tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), titanium (Ti), nickel (Ni), and their alloys. In a specific embodiment, the first metal layer M1 is divided into three layers: the lower layer contains one or more alloys of Mo, Ti, and Ni; the middle layer is Cu or a Cu alloy; and the upper layer contains one or more alloys of Mo, Ti, and Ni. The thickness of the lower layer ranges from 50 angstroms to 500 angstroms, the thickness of the middle layer ranges from 2000 angstroms to 10000 angstroms, and the thickness of the upper layer ranges from 50 angstroms to 500 angstroms.

[0036] The first interlayer insulating layer ILD1 covers the first metal layer M1 and the first gate insulating layer GIL1, and extends into the first via TH1 and the second via TH2. The material of the first interlayer insulating layer ILD1 is one of silicon oxide, nitric oxide, silicon oxynitride, or a stack thereof.

[0037] The second barrier layer 22 covers the first interlayer insulating layer ILD1. Alternatively, the second barrier layer 22 is disposed between the first transistor T1 and the second transistor T2 to block hydrogen, water vapor, or oxygen, preventing the first transistor T1 and the second transistor T2 from being affected by hydrogen, water vapor, or oxygen. The material of the second barrier layer 22 is selected from one or a combination of alumina, hafnium oxide, and yttrium oxide. In this embodiment, the second barrier layer 22 is configured to completely cover the first interlayer insulating layer ILD1. Optionally, the second barrier layer 22 may also be disposed only above the first oxide semiconductor layer OS1 of the first transistor T1 and below the second oxide semiconductor layer OS2 of the second transistor T2.

[0038] The second oxide semiconductor layer OS2 includes a second active layer p-OS. The material of the second active layer p-OS is a polycrystalline oxide semiconductor. The second active layer p-OS includes a second channel CL2 and a second source portion S2 and a second drain portion D2 located on both sides of the second channel CL2. The second channel CL2 is connected to the second source portion S2 and the second drain portion D2, respectively. Figure 1 As shown, "located on both sides of the second channel CL2" refers to both sides in a direction parallel to the surface of the substrate 10. The second channel CL2 is an amorphous oxide semiconductor, and the second source portion S2 and the second drain portion D2 are conductive amorphous oxide semiconductors. Specifically, the amorphous oxide semiconductor material can be selected from one of indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), gallium indium oxide (IGO), indium gallium tin oxide (IGTO), and indium zinc tin oxide (IZTO), but is not limited to these. In this embodiment, the first barrier layer 21 is configured as a whole-layer structure covering the buffer layer BL. Optionally, the first barrier layer 21 can be disposed only below the first active layer a-OS. In addition, optionally, the orthogonal projection of the light-shielding layer LS on the plane where the first active layer a-OS is located at least covers the second channel CL2.

[0039] The second oxide semiconductor layer OS2 also includes a second electrode plate CS2 that is insulated from the second active layer p-OS by a gap. The second electrode plate CS2 serves as one electrode of the storage capacitor CST and is disposed opposite to the first electrode plate CS1 in the thickness direction of the display panel 100. The second electrode plate CS2 is a conductive polycrystalline oxide semiconductor, which can be conductive during the process of conductiveizing the second source portion S2 and the second source portion S2.

[0040] The third barrier layer 23 is disposed on the second active layer p-OS to block hydrogen, water vapor, or oxygen, preventing the second active layer p-OS from being affected by hydrogen, water vapor, or oxygen. The material of the third barrier layer 23 is selected from one or a combination of alumina, hafnium oxide, and yttrium oxide. In this embodiment, the third barrier layer 23 also serves as the gate insulating portion of the second transistor T2; therefore, the third barrier layer 23 is island-shaped. Optionally, the display panel 100 may also include a second gate insulating portion (not shown), on which the third barrier layer 23 is disposed. Alternatively, the third barrier layer 23 may be configured to cover the entire surface of the second active layer p-OS, or even cover the entire surface of the second barrier layer 22.

[0041] The second metal layer M2 includes a second gate GE2, which is disposed on the island-shaped third barrier layer 23 (i.e., the second gate insulating portion). The second gate GE2 is the gate of the second transistor T2. The material of the second metal layer M2 can be selected from copper (Cu), tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), titanium (Ti), nickel (Ni), and their alloys or stacks. The second metal layer M2 can be a single layer or multiple layers. When the second metal layer M2 is multiple layers, it can be a stack of copper (Cu), tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), titanium (Ti), nickel (Ni), and their alloys. In one specific embodiment, the second metal layer M2 is divided into three layers: the lower layer contains one or more alloys of Mo, Ti, and Ni; the middle layer is Cu or a Cu alloy; and the upper layer contains one or more alloys of Mo, Ti, and Ni. The thickness of the lower layer ranges from 50 angstroms to 500 angstroms, the thickness of the middle layer ranges from 2000 angstroms to 10000 angstroms, and the thickness of the upper layer ranges from 50 angstroms to 500 angstroms.

[0042] The second interlayer insulating layer ILD2 covers the second barrier layer 22, the second oxide semiconductor layer OS2, the third barrier layer 23, and the second metal layer M2. In this embodiment, the second interlayer insulating layer ILD2 covers the entire surface of the second barrier layer 22, the second oxide semiconductor layer OS2, the third barrier layer 23, and the second metal layer M2. The thickness of the second barrier layer 22 is 100 angstroms to 500 angstroms, and the thickness of the first interlayer insulating layer ILD1 is 2000 angstroms to 10000 angstroms. The second interlayer insulating layer ILD2 is one of silicon oxide, nitric oxide, and silicon oxynitride, or a stack thereof.

[0043] The third metal layer M3 includes a second source SE2, a second drain DE2, and a third electrode CS3, which are spaced apart and insulated from each other. The second source SE2 and the second drain DE2 are the source and drain of the second transistor T2, respectively. The second source SE2 extends into a third via TH3 formed in the second interlayer insulating layer ILD2 and is connected to the second source portion S2. The second drain DE2 extends into a TH4 formed in the second interlayer insulating layer ILD2 and is connected to the second drain portion D2. In addition, the second drain DE2 is also connected to the light-shielding layer LS through a deep hole DH that penetrates the second interlayer insulating layer ILD2, the second barrier layer 22, and the first interlayer insulating layer ILD1.

[0044] The third electrode plate CS3, serving as one electrode of the storage capacitor CST, is disposed opposite to the second electrode plate CS2 in the thickness direction of the display panel 100. The second source electrode SE2, the second drain electrode DE2, and the third electrode plate CS3 are disposed in the same layer and made of the same material, and can be fabricated using a single photomask, thereby reducing the number of photomasks required to manufacture the display panel 100 of this application and lowering costs. The material of the third metal layer M3 can be selected from copper (Cu), tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), titanium (Ti), nickel (Ni), and their alloys, or a stack thereof. The second metal layer M2 can be a single layer or multiple layers. When the third metal layer M3 is multiple layers, it can be a stack of copper (Cu), tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), titanium (Ti), nickel (Ni), and their alloys. In one specific embodiment, the third metal layer M3 consists of three layers: the lower layer contains one or more alloys of Mo, Ti, and Ni; the middle layer is Cu or a Cu alloy; and the upper layer contains one or more alloys of Mo, Ti, and Ni. The thickness of the lower layer ranges from 50 angstroms to 500 angstroms, the thickness of the middle layer ranges from 2,000 angstroms to 10,000 angstroms, and the thickness of the upper layer ranges from 50 angstroms to 500 angstroms.

[0045] Optionally, in another embodiment of this application, the storage capacitor of the display panel 100 is disposed on the periphery of the second transistor T2. The second electrode plate CS2 and the third electrode plate CS3 are disposed opposite to each other, serving as the two electrodes of the storage capacitor.

[0046] The passivation layer PV covers the second interlayer insulating layer ILD2 and the third metal layer M3. The material of the passivation layer PV is one of silicon oxide, nitric oxide, silicon oxynitride, or a stack thereof.

[0047] The planarization layer PLN covers the passivation layer PV. The material of the planarization layer PLN can be organic materials such as acrylic resin, epoxy resin, or perfluoroalkoxy resin (PFA).

[0048] The bottom electrode layer PE is disposed on the planarization layer PLN and includes the anode BE of the organic light-emitting device and the fourth electrode plate CS4. The anode BE and the fourth electrode plate CS4 are connected. A fifth through-hole TH5 is formed in the passivation layer PV and the planarization layer PLN (collectively referred to as the electrode insulating layer), and the anode BE of the organic light-emitting device extends into the fifth through-hole TH5 and connects to the second drain DE2. A groove G is also formed in the planarization layer PLN, and the fourth electrode plate CS4 is located in the groove G. Optionally, the display panel 100 may not include the planarization layer PLN, in which case the passivation layer PV is the electrode insulating layer. The fourth electrode plate CS4 serves as one electrode plate of the storage capacitor CST and is disposed opposite to the third electrode plate CS3 in the thickness direction of the display panel 100. The material of the bottom electrode layer PE can be a metal or a metal oxide layer, for example, selected from metal oxides such as aluminum, gold, silver, or indium tin oxide, or a stack of metals and metal oxides.

[0049] The pixel definition layer (PDL) is disposed on the bottom electrode layer (PE), and an opening is provided in the pixel definition layer (PDL) so that the anode (BE) is exposed from the opening of the pixel definition layer (PDL).

[0050] The light-emitting functional layer EL is disposed in the opening of the pixel definition layer PDL and connected to the anode BE.

[0051] The top electrode layer PE' covers the entire pixel definition layer PDL and the light-emitting functional layer EL, serving as the cathode of the light-emitting layer 30. The anode BE, the pixel definition layer PDL, the light-emitting functional layer EL, and the top electrode layer PE' together constitute the light-emitting layer 30 of the display panel 100.

[0052] Currently, various manufacturers are developing polycrystalline oxide semiconductor materials. Although different manufacturers use different material systems and element ratios, the polycrystalline oxide semiconductor materials currently on the market can achieve high mobility similar to LTPS and lower cutoff leakage current than LTPS. For example, the polycrystalline oxide semiconductor material developed by Idemitsu Kosan Co., Ltd. has high mobility and low cutoff leakage current.

[0053] The display panel 100 provided in this application embodiment has a hybrid driving circuit of polycrystalline oxide semiconductor and amorphous oxide semiconductor. It uses amorphous oxide semiconductor transistors with low leakage current and high uniformity as switching transistors, and high mobility and low cutoff leakage current as driving transistors, thereby reducing leakage current and improving display quality. The first transistor and the second transistor are disposed on different layers, and the first active layer and the second active layer are separated by a first interlayer insulating layer, reducing the probability of both being simultaneously invaded by water and oxygen, and improving the stability of the driving circuit. The first transistor and the second transistor are disposed on different layers, allowing for the selection of different materials for the two transistors, resulting in high process freedom, and ensuring that the two active layers do not affect each other when being conductive.

[0054] On the other hand, the current manufacturing process for polycrystalline oxide materials generally involves first preparing an amorphous oxide semiconductor thin film, followed by annealing to transform the amorphous oxide semiconductor into a polycrystalline state. The annealing temperature is lower than that of polycrystalline silicon, and it eliminates the need for excimer laser annealing. Furthermore, polycrystalline oxide semiconductors have more uniform grain sizes than LTPS, allowing them to replace LTPS in large-size display panels 100. This overcomes the current technical bottleneck that LTPO technology can only be used for small to medium-sized panels, and in the future, it can be applied to panels from generation G8.5 and above. Specifically, large-size display panels refer to display panels larger than 45 inches.

[0055] In some embodiments, the first gate GE1, the first source SE1, the first drain DE1, the light-shielding layer LS, and the first electrode CS1 are disposed in the same layer and are made of the same material, and can be made in one photomask, thereby reducing the number of photomasks required to manufacture the display panel 100 of this application and reducing costs.

[0056] The storage capacitor CST of the display panel 100 in some embodiments of this application includes a second electrode CS2 made of conductive polycrystalline oxide semiconductor. The second electrode CS2 is disposed on the same layer as the second active layer p-OS, which can be fabricated in one photomask process, thereby saving materials and processes.

[0057] The first electrode plate CS1 and the second electrode plate CS2 are arranged opposite each other to form the first capacitor, and the second electrode plate CS2 and the third electrode plate CS3 are arranged opposite each other to form the second capacitor. The first capacitor and the second capacitor are connected in parallel to increase the capacitance value of the storage capacitor CST.

[0058] In addition, the third plate CS3 and the fourth plate CS4 are arranged opposite each other to form a third capacitor. The first capacitor, the second capacitor and the third capacitor are connected in parallel to form a storage capacitor CST, which further increases the capacitance value of the storage capacitor.

[0059] In some embodiments, the first electrode CS1 is disposed on the same layer as the first gate GE1, the second electrode CS2 is disposed on the same layer as the polycrystalline oxide semiconductor layer p-OS, the third electrode CS3 is disposed on the same layer as the second drain DE2, and the fourth electrode CS4 is disposed on the same layer as the anode BE and connected to the anode BE. The storage capacitor can be formed using an existing photomask.

[0060] Meanwhile, as display devices pursue higher resolutions and refresh rates, pixel capacitor designs need to meet the driving requirements of high refresh rates while reducing capacitor area. The display panel 100 of this embodiment can also reduce the capacitor area and increase the aperture ratio while maintaining the same capacitance value. It should be noted that the four capacitor plates can be connected in parallel to the above three parallel plate capacitors through wiring design. Figure 1 The schematic diagram is only used to show the film structure of the display panel 100 and is not used to show the wiring connection.

[0061] In some implementations, the thickness of the planarization layer PLN is typically a few micrometers. It is known that the capacitance of a parallel plate capacitor is inversely proportional to the distance between the plates. To increase the capacitance of the storage capacitor CST, holes need to be drilled in the planarization layer PLN in the capacitor region so that the fourth substrate 10 can be directly attached to the passivation layer PV, thereby reducing the distance between the plates and increasing the capacitance of the storage capacitor CST.

[0062] In some embodiments, a first barrier layer 21 is provided between the first interlayer insulating layer ILD1 and the second transistor T2 to prevent the second transistor T2 from being invaded by water vapor, oxygen or hydrogen.

[0063] In some embodiments, a second barrier layer 22 is provided between the buffer layer BL and the first active layer OS-1 to prevent the first transistor T1 from being invaded by water vapor, oxygen or hydrogen.

[0064] In some implementations, since the second barrier layer 22 is thin (less than 500 angstroms), foreign objects may be introduced during the process, causing interlayer short circuits and affecting yield. The second interlayer insulating layer ILD2 is thicker, which can form a flat surface above the second barrier layer 22, preventing short circuits caused by foreign objects and ensuring process yield.

[0065] In some embodiments, a third barrier layer 23 is provided between the second gate GE2 and the second active layer OS-2 to prevent the second transistor T2 from being invaded by water vapor, oxygen or hydrogen.

[0066] Please refer to Figure 2 This application also provides a display device 1. The display device 1 can be a mobile phone, tablet computer, e-reader, electronic display screen, laptop computer, mobile phone, augmented reality (AR) or virtual reality (VR) device, media player, wearable device, digital camera, car navigation system, etc. The display device 1 includes the display panel 100 of this application.

[0067] Please refer to Figures 3(a) to 3(j) This application also provides a method for manufacturing a display panel, which includes the following steps:

[0068] 101: Referring to Figure 3(a), a substrate 10 is provided, on which a buffer layer BL and a first barrier layer 21 are sequentially formed. The buffer layer BL is one or a combination of silicon nitride and silicon oxide. The thickness of the buffer layer BL ranges from 2000 angstroms to 10000 angstroms, and the material of the first barrier layer 21 is aluminum oxide, with a thickness of 100 angstroms to 500 angstroms.

[0069] 102: A first semiconductor material layer 30 is formed on the first barrier layer 21. The material of the first semiconductor material layer 30 is an amorphous oxide semiconductor, and the thickness is 100 angstroms to 1000 angstroms.

[0070] 103: Referring to Figure 3(b), a first gate insulating layer GIL1 is formed on the first semiconductor material layer 30. The material of the first gate insulating layer GIL1 is silicon oxide, and the thickness is 1000 angstroms to 3000 angstroms. The first gate insulating layer GIL1 is patterned by photolithography, and a first gate insulating portion GI1 is formed above the first semiconductor material layer 30. A first via TH1 and a second via TH2 are formed in the first gate insulating layer GIL1. The amorphous oxide semiconductor exposed in the first via TH1 and the second via TH2 is made conductive by helium plasma (He Plasma) treatment.

[0071] 104: Referring to Figure 3(c), a first metal layer M1 is formed on the first gate insulating layer GIL1. The first metal layer M1 includes a first gate GE1, a first source SE1, a first drain DE1, a light-shielding layer LS, and a first electrode CS1, which are spaced apart and insulated from each other. The first gate GE1 is disposed on the first gate insulating portion GI1. The first source SE1 extends into the first via TH1 and connects to the first source portion S1, and the first drain DE1 extends into the second via TH2 and connects to the first drain portion D1. Furthermore, after forming the gate self-alignment structure, the first semiconductor material layer 30 in the first via TH1 and the second via TH2 is subjected to secondary conductor treatment. The first metal layer M1 is divided into three layers: the lower layer contains one or more alloys of Mo, Ti, and Ni; the middle layer is Cu or a Cu alloy; and the upper layer contains one or more alloys of Mo, Ti, and Ni. The thickness of the lower layer ranges from 50 angstroms to 500 angstroms, the thickness of the middle layer ranges from 2,000 angstroms to 10,000 angstroms, and the thickness of the upper layer ranges from 50 angstroms to 500 angstroms.

[0072] 105: Referring to Figure 3(d), a first interlayer insulating layer ILD1 and a second barrier layer 22 are formed on the first metal layer M1. The first interlayer insulating layer ILD1 is silicon oxide with a thickness ranging from 2000 angstroms to 10000 angstroms, and the second barrier layer 22 is made of aluminum oxide with a thickness ranging from 100 angstroms to 500 angstroms.

[0073] 106: A second oxide semiconductor layer OS2 is formed on the second barrier layer 22. The second oxide semiconductor layer OS2 includes a second active layer p-OS of the second transistor T2 and a second electrode plate CS2 disposed insulated from the second active layer p-OS. The thickness of the second oxide semiconductor layer OS2 is 100 angstroms to 1000 angstroms.

[0074] 107: Referring to Figure 3(e), a third barrier layer 23 and a second metal layer M2 are formed on the second oxide semiconductor layer OS2. The third barrier layer 23 and the second metal layer M2 are patterned to form a top-gate self-aligned structure including a second gate GE2. The material of the third barrier layer 23 is aluminum oxide, and its thickness is 500 angstroms to 1000 angstroms. In one specific embodiment, the second metal layer M2 is divided into three layers: the lower layer contains one or more alloys of Mo, Ti, and Ni; the middle layer is Cu or a Cu alloy; and the upper layer contains one or more alloys of Mo, Ti, and Ni. The thickness of the lower layer ranges from 50 angstroms to 500 angstroms, the thickness of the middle layer ranges from 2000 angstroms to 10000 angstroms, and the thickness of the upper layer ranges from 50 angstroms to 500 angstroms. The second metal layer M2 also includes a third electrode CS3.

[0075] 108: Referring to Figure 3(f), a second interlayer insulating layer ILD2 is formed on the third barrier layer 23 and the second metal layer M2. The material of the second interlayer insulating layer ILD2 is silicon oxide, and the thickness ranges from 2000 angstroms to 10000 angstroms. A third via TH3, a fourth via TH4, and a deep via DH are patterned and etched. The third via TH3 and the fourth via TH4 penetrate the second interlayer insulating layer ILD2, and the deep via DH penetrates the second interlayer insulating layer ILD2, the second barrier layer 22, and the first interlayer insulating layer ILD1.

[0076] 109: Please refer to Figure 3(g), where a third metal layer M3 is located on the second interlayer insulating layer ILD2. The third metal layer M3 includes a second source SE2, a second drain DE2, and a third electrode CS3, which are spaced apart and insulated from each other. The second source SE2 and the second drain DE2 are the source and drain of the second transistor T2, respectively. The second source SE2 extends into a third via TH3 formed in the second interlayer insulating layer ILD2 and is connected to the second source portion S2. The second drain DE2 extends into a TH4 formed in the second interlayer insulating layer ILD2 and is connected to the second drain portion D2. In addition, the second drain DE2 is also connected to the light-shielding layer LS through a deep hole DH penetrating the second interlayer insulating layer ILD2, the second barrier layer 22, and the first interlayer insulating layer ILD1.

[0077] In one specific embodiment, the third metal layer M3 is divided into three layers: the lower layer contains one or more alloys of Mo, Ti, and Ni; the middle layer is Cu or a Cu alloy; and the upper layer contains one or more alloys of Mo, Ti, and Ni. The thickness of the lower layer ranges from 50 angstroms to 500 angstroms, the thickness of the middle layer ranges from 2000 angstroms to 10000 angstroms, and the thickness of the upper layer ranges from 50 angstroms to 500 angstroms.

[0078] 110: Referring to Figure 3(h), a passivation layer PV and a planarization layer PLN are formed on the third metal layer M3. The material of the passivation layer PV is silicon oxide, and the material of the planarization layer PLN is an organic material. A fifth via TH5 penetrating the passivation layer PV and the planarization layer PLN and a groove G penetrating the planarization layer PLN are patterned using a half-tone mask. The thickness of the passivation layer PV ranges from 1000 angstroms to 5000 angstroms.

[0079] 111: Please refer to Figure 3(i) to form and pattern the bottom electrode layer PE on the planarization layer PLN. The bottom electrode layer PE includes the anode BE of the organic light-emitting device and the fourth electrode plate CS4. The anode BE is made of a stack of ITO / Ag / ITO.

[0080] 112: Please refer to Figure 3(j). A pixel definition layer PDL, an emitting functional layer EL, and a top electrode layer PE' are formed sequentially on the bottom electrode layer PE.

[0081] It should be noted that the manufacturing method of the display panel in this application also includes steps such as forming a light-emitting layer and a cathode, which will not be described in detail here.

[0082] For further information, please refer to [link / reference]. Figure 4 and Figures 5(a) to 5(e) , Figures 3(b) to 3(c) The specific steps are as follows:

[0083] 201: Please refer to Figure 5(a). A first photoresist PR1 layer is formed on the first gate insulating layer GIL1. An opening OP is formed at both ends of the first active layer a-OS.

[0084] It should be noted that, Figures 5(a) to 5(e) Only the formation process of the drain terminal of the TFT is shown in the figure; the formation process of the source terminal is the same and is omitted here.

[0085] 202: Please refer to Figure 5(b). Under the protection of the first photoresist PR1 layer, the first gate insulating layer GIL1 is etched away to expose the two ends of the first active layer a-OS.

[0086] 203: Referring to Figure 5(c), the two ends of the exposed first active layer a-OS are first conductiveized, and the first photoresist PR1 layer is removed. As shown in Figure 5(c), a first conductive portion C1 is formed in the first active layer a-OS.

[0087] 204: Referring to Figure 5(d), a metal layer is formed on the first gate insulating layer GIL1. A second photoresist PR2 is formed on the metal layer by exposure and development. Under the protection of the second photoresist PR2, the metal layer is etched to form the first gate GE1, the first source SE1, and the first drain DE1. For subsequent connection, the first source SE1 and the first drain DE1 extend into the first via TH1 and the second via TH2. While etching the metal layer, the portion of the first conductor C1 not covered by the second photoresist PR2 is removed. Furthermore, the first source SE1 and the first drain DE1 respectively cover the first conductor C1 located in the first via TH1 and the second via TH2 that was not etched away.

[0088] 205: Referring to Figure 5(e), under the protection of the second photoresist PR2, the first gate insulating layer GIL1 is etched away, and the first active layer a-OS is conductiveized a second time. The first active layer a-OS, which is not covered by the first gate GE1, is conductiveized to form the first source region S1 and the first drain region D1.

[0089] 206: Please refer to Figure 5(f) to remove the second photoresist PR2.

[0090] The display panel provided in this application embodiment has a hybrid driving circuit of polycrystalline oxide semiconductor and amorphous oxide semiconductor. Amorphous oxide semiconductor transistors with low leakage current and high uniformity are used as switching transistors, while high mobility and low cutoff leakage current are used as driving transistors, thereby reducing leakage current and improving display quality. On the other hand, the grain size of polycrystalline oxide semiconductors is more uniform than that of LTPS, and it can replace LTPS in large-size display panels, overcoming the technical bottleneck that existing LTPO technology can only be used in small and medium-sized panels. In the future, it can be applied to panels of generation G8.5 and above.

[0091] The foregoing has provided a detailed description of the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, include: substrate; A first transistor is disposed on the substrate. The first transistor includes a first active layer, and the material of the first active layer is an amorphous oxide semiconductor. A first interlayer insulating layer covers the side of the first transistor away from the substrate; The second transistor is disposed on the side of the first interlayer insulating layer away from the first transistor. The second transistor includes a second active layer, and the material of the second active layer is a polycrystalline oxide semiconductor. A first barrier layer is disposed between the first interlayer insulating layer and the second transistor; as well as A storage capacitor is disposed on the periphery of the second transistor. The storage capacitor includes a first plate and a second plate. The first plate and the second plate form a first capacitor. The second plate is disposed on the same layer as the second active layer. The material of the second plate is a conductive polycrystalline oxide semiconductor. The display panel further includes a pixel driving circuit. The first transistor is a switching transistor of the pixel driving circuit, and the second transistor is a driving transistor of the pixel driving circuit. The first transistor also includes a first gate insulating layer covering the first active layer. The first gate, first source, and first drain of the first transistor are all located on the side of the first interlayer insulating layer away from the second transistor and on the side of the first gate insulating layer away from the substrate. The second transistor includes a second gate insulating layer and a second interlayer insulating layer that sequentially cover the second active layer. The second source and second drain of the second transistor are disposed on the side of the second interlayer insulating layer away from the first transistor and on the side of the second interlayer insulating layer away from the substrate. The second gate is located on the side of the second active layer near the second source.

2. The display panel as described in claim 1, characterized in that, The storage capacitor further includes a third plate, which is located on opposite sides of the second plate, and forms a second capacitor with the first plate. The second capacitor is connected in parallel with the first capacitor, and the third plate is disposed on the same layer as the second drain.

3. The display panel as described in claim 2, characterized in that, The storage capacitor further includes a fourth electrode plate, which is disposed on the side of the third electrode plate away from the second electrode plate. The fourth electrode plate and the third electrode plate form a third capacitor. The third capacitor is connected in parallel with the first capacitor and the second capacitor. The fourth electrode plate is disposed on the same layer as the anode of the display panel.

4. The display panel as described in claim 3, characterized in that, The display panel further includes a planarization layer located between the second transistor and the anode, and a groove is formed in the planarization layer, with the fourth electrode plate located within the groove.

5. The display panel as described in claim 1, characterized in that, The display panel further includes a storage capacitor disposed on the periphery of the second transistor. The storage capacitor includes a first electrode and a second electrode, the first electrode and the second electrode forming a first capacitor, the second electrode being disposed on the same layer as the second active layer, the material of the second electrode being a conductive polycrystalline oxide semiconductor, and the first electrode being disposed on the same layer as the second drain electrode.

6. The display panel as described in claim 1, characterized in that, The display panel further includes a buffer layer and a second barrier layer. The buffer layer is located between the substrate and the first active layer, and the second barrier layer is disposed between the buffer layer and the first active layer.

7. The display panel as described in claim 1, characterized in that, The second transistor includes a second gate, a second source, and a second drain. The second source and the second drain are disposed on the side of the second active layer away from the substrate. The second gate is located on the side of the second active layer close to the second source. The display panel also includes a third barrier layer disposed between the second gate and the second active layer.

8. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 7.

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