Photovoltaic device

Abstract

The application provides a photovoltaic device, comprising: a layer plate, a light-transmitting conductive layer, an HRT buffer layer, a window layer, an absorption layer and a back contact layer which are arranged in a stack, wherein the HRT buffer layer comprises: n layer sub-HRT buffer layers, n is greater than or equal to 2, the nth layer sub-HRT buffer layer is located between the (n-1)th layer sub-HRT buffer layer and the window layer, and the resistance of a later layer sub-HRT buffer layer is higher than that of an earlier layer sub-HRT buffer layer. The technical scheme of the application can effectively solve the problem of low efficiency of the photovoltaic device in the prior art.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of solar cells, and in particular, to a photovoltaic device. BACKGROUND

[0002] The world record efficiency of small laboratory CdTe / CdS(e) solar cells is maintained at 22.1%, with short circuit current (Jsc), open circuit voltage (Voc) and fill factor (FF) in the range of 30-31 mA / cm 2 , 880-900 mV and 78-80%, respectively. The quantity Jsc is close to its practical limit, considering the optical losses in CdTe cells (reflection, absorption in CdS, etc.), and further improvements are very difficult.

[0003] CdS(e) / CdTe based solar cell structure is the most successful thin film technology to date. The short circuit current (Jsc) is largely influenced by the thickness of the window layer CdS(e). However, if the window layer CdS(e) is too thin, it will lead to the phenomenon of discontinuity of CdS(e), so that the absorber layer (CdTe layer) will be in direct contact with the TCO layer at the discontinuous position, resulting in cell leakage, and the Voc and FF will decrease, thereby affecting the cell efficiency. SUMMARY

[0004] The main purpose of the present application is to provide a photovoltaic device to solve the problem of low efficiency of the photovoltaic device in the prior art.

[0005] In order to achieve the above-mentioned purpose, the present application provides a photovoltaic device, comprising: a layer plate, a light-transmitting conductive layer, an HRT buffer layer, a window layer, an absorber layer and a back contact layer which are stacked, wherein the HRT buffer layer comprises: n layers of sub-HRT buffer layers, n≥2, the nth layer of sub-HRT buffer layer is located between the (n-1)th layer of sub-HRT buffer layer and the window layer, and the resistance of the latter layer of sub-HRT buffer layer is higher than that of the former layer of sub-HRT buffer layer.

[0006] In one embodiment, the material of each sub-HRT buffer layer independently comprises one or more of oxide, nitride, carbide, diamond lattice carbon.

[0007] In one embodiment, the material of each sub-HRT buffer layer independently comprises one or more of Al2O3, TiO2, SiO2, ZrO, ZnO, MgO, CdO, TeO2, WO2, M0O2, Ta2O5, Ga2O3, SiC, SiN, AlN, C.

[0008] In one embodiment, the thickness of the HRT buffer layer is between 10 and 1000 nm.

[0009] In one embodiment, the photovoltaic device further comprises: an interface buffer layer between the window layer and the absorber layer, the material of the interface buffer layer having a lattice length between the lattice length of the material of the window layer and the lattice length of the material of the absorber layer.

[0010] In one embodiment, the material of the interface buffer layer independently comprises one or more of an oxide, a nitride, a carbide, diamond lattice carbon.

[0011] In one embodiment, the material of the interface buffer layer independently comprises one or more of AI2O3, TiO2, SiO2, ZrO, ZnO, MgO, CdO, TeO2, WO2, M0O2, Ta2O5, Ga2O3, SiC, SiN, AIN, C.

[0012] In one embodiment, the thickness of the interface buffer layer is between 1 and 1000 nm.

[0013] In one embodiment, the photovoltaic device further comprises: a back contact buffer layer, the back contact buffer layer being a high resistivity transparent layer, the back contact buffer layer being between the absorber layer and the back contact layer.

[0014] In one embodiment, the back contact buffer layer comprises m layers of sub-back contact buffer layers, m > 2, the mth layer of sub-back contact buffer layer being between the m-1th layer of sub-back contact buffer layer and the back contact layer, the electrical resistance of the latter layer of sub-back contact buffer layer being higher than the electrical resistance of the former layer of sub-back contact buffer layer.

[0015] In one embodiment, in the case where the back contact buffer layer is a single layer, the material of the back contact buffer layer independently comprises one or more of an oxide, a nitride, a carbide, diamond lattice carbon; in the case where the back contact buffer layer comprises multiple layers of sub-back contact buffer layers, the material of each sub-back contact buffer layer independently comprises one or more of an oxide, a nitride, a carbide, diamond lattice carbon.

[0016] In one embodiment, in the case where the back contact buffer layer is a single layer, the material of the back contact buffer layer independently comprises one or more of AI2O3, TiO2, SiO2, ZrO, ZnO, MgO, CdO, TeO2, WO2, M0O2, Ta2O5, Ga2O3, SiC, SiN, AIN, C; in the case where the back contact buffer layer comprises multiple layers of sub-back contact buffer layers, the material of each sub-back contact buffer layer independently comprises one or more of AI2O3, TiO2, SiO2, ZrO, ZnO, MgO, CdO, TeO2, WO2, M0O2, Ta2O5, Ga2O3, SiC, SiN, AIN, C.

[0017] In one embodiment, the thickness of the back contact buffer layer is between 1 to 1000 nm.

[0018] By applying the technical solution of the present application, the HRT buffer layer is arranged between the light-transmitting conductive layer and the window layer, so that even if the window layer has discontinuity, the HRT buffer layer can exist between the light-transmitting conductive layer and the window layer, thereby preventing current leakage, avoiding the Voc and FF from being reduced, and further ensuring that the battery efficiency will not be reduced. More importantly, by applying the technical solution of the present application, the HRT buffer layer actually includes multiple layers of sub-HRT buffer layers, and the resistance of the latter layer of sub-HRT buffer layers is higher than that of the former layer of sub-HRT buffer layers. On the one hand, since the resistance of the latter layer of sub-HRT buffer layers is higher than that of the former layer of sub-HRT buffer layers, the effect of preventing current leakage is better. On the other hand, since electrons need to tunnel through the HRT buffer layer, if the HRT buffer layer is thicker, it is more difficult for the electrons to tunnel. In order to reduce the difficulty of electron tunneling, in the present application, the resistance of the latter layer of sub-HRT buffer layers is higher than that of the former layer of sub-HRT buffer layers. In this way, even if the thickness of the latter layer of sub-HRT buffer layers is set to be thinner, it can still meet the requirement of preventing current leakage. At the same time, since the thickness of the latter layer of sub-HRT buffer layers is thinner, the overall thickness of the HRT buffer layer is reduced, thereby reducing the difficulty of electron tunneling and improving the battery efficiency.

[0019] In addition to the above-described objects, features and advantages, the present application has other objects, features and advantages. The present application will be further described below with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0020] The drawings constituting a part of the specification of the present application serve to provide further understanding of the present application, and the schematic embodiments of the present application and the description thereof serve to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0021] Figure 1 A structural schematic diagram of an embodiment of a photovoltaic device according to the present application is shown.

[0022] Among them, the above-mentioned drawings include the following reference signs:

[0023] 10, layer plate; 20, light-transmitting conductive layer; 30, HRT buffer layer; 31, sub-HRT buffer layer; 40, window layer; 50, interface buffer layer; 60, absorption layer; 70, back contact buffer layer; 80, back contact layer. DETAILED DESCRIPTION

[0024] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0025] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of embodiments of the present application, rather than all embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort should fall within the protection scope of the present application.

[0026] It should be noted that the terms "first", "second" and the like in the description and in the claims of the present application and the above-described drawings are intended to distinguish similar objects and not to describe a particular order or sequence. It should be understood that the terms so used are interchangeable under appropriate circumstances so that the embodiments of the application described herein are applicable to embodiments of the application in which the terms are transposed. Furthermore, the terms "comprise", "have" and any variations thereof are intended to cover a non-exclusive inclusion, for example, a process, method, article, or apparatus that comprises a list of steps or units not necessarily limited to those specifically listed, but can include other not expressly listed steps or units, or additional steps or units inherent to such process, method, article, or apparatus.

[0027] It should be noted that the terms used herein are only intended to describe specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprise" and / or "include", when used in this specification, specify the presence of stated features, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0028] As shown in FIG. 1, in the present embodiment, the photovoltaic device comprises a layer plate 10, a light-transmitting conductive layer 20, an HRT buffer layer 30, a window layer 40, an absorption layer 60, and a back contact layer 80, which are stacked, wherein the HRT buffer layer 30 comprises two layers of sub-HRT buffer layers 31, and the second layer of sub-HRT buffer layers 31 is located between the first layer of sub-HRT buffer layers 31 and the window layer 40, and the resistance of the second layer of HRT buffer layers 30 is higher than that of the first layer of sub-HRT buffer layers 31.

[0029] The technical scheme is applied to the embodiment, the HRT buffer layer 30 is arranged between the light-transmitting conductive layer 20 and the window layer 40, so that even if the window layer 40 has discontinuity, the HRT buffer layer 30 can exist between the light-transmitting conductive layer 20 and the window layer 40, thereby preventing current leakage, avoiding Voc and FF from being reduced, and ensuring that the battery efficiency is not reduced. More importantly, in the technical scheme of the embodiment, the HRT buffer layer 30 actually includes two layers of sub-HRT buffer layers 31, and the resistance of the second layer of sub-HRT buffer layers 31 is higher than that of the first layer of sub-HRT buffer layers 31. On the one hand, because the resistance of the second layer of sub-HRT buffer layers 31 is higher than that of the first layer of sub-HRT buffer layers 31, the effect of preventing current leakage is better. On the other hand, because electrons need to tunnel through the HRT buffer layer 30, the thicker the HRT buffer layer 30 is, the more difficult it is for the electrons to tunnel. In order to reduce the difficulty of electron tunneling, in the embodiment, the resistance of the second layer of sub-HRT buffer layers 31 is higher than that of the first layer of sub-HRT buffer layers 31. In this way, the thickness of the second layer of sub-HRT buffer layers 31 can be set to be thin, while meeting the requirement of preventing current leakage. At the same time, because the thickness of the second layer of sub-HRT buffer layers 31 is thin, the thickness of the overall HRT buffer layer 30 is reduced, thereby reducing the difficulty of electron tunneling and improving the battery efficiency.

[0030] Of course, in other embodiments not shown in the figure, the sub-HRT buffer layer 31 can be three or more layers, as long as the resistance of the subsequent layer of sub-HRT buffer layers 31 is greater than that of the previous layer of sub-HRT buffer layers 31.

[0031] As shown in Figure 1 In the embodiment, the material of each sub-HRT buffer layer 31 independently includes one or more of oxides, nitrides, carbides, and diamond lattice carbon. That is, the material of the sub-HRT buffer layer 31 can be any oxide, nitride, carbide, diamond lattice carbon, or a mixture thereof. Preferably, the material of each sub-HRT buffer layer 31 independently includes one or more of Al2O3, TiO2, SiO2, ZrO, ZnO, MgO, CdO, TeO2, WO2, MoO2, Ta2O5, Ga2O3, SiC, SiN, AlN, and C. It should be noted that the material of the sub-HRT buffer layer 31 includes but is not limited to the above-mentioned materials.

[0032] As shown in Figure 1 In the embodiment, the thickness of the HRT buffer layer 30 is between 10 and 1000bnm. Table 1 shows the relationship between the thickness of the HRT buffer layer 30 and the battery efficiency.

[0033] Table 1 Relationship between thickness of HRT buffer layer 30 and battery efficiency

[0034]

[0035] The 2nd to 4th groups in Table 1 are within the scope of the present embodiment, and the 1st and 5th groups are comparative examples. As can be seen from the above table, the battery efficiency is higher when the thickness of the HRT buffer layer 30 is within the predetermined range.

[0036] Since the lattice length of the material of the window layer 40 is different from that of the material of the absorption layer 60, defects can exist between the interface of the two layers. To solve the above problem, as shown in Figure 1 the photovoltaic device of the present embodiment further comprises an interface buffer layer 50, which is located between the window layer 40 and the absorption layer 60, and the lattice length of the material of the interface buffer layer 50 is between the lattice length of the material of the window layer 40 and the lattice length of the material of the absorption layer 60. The above structure can effectively reduce lattice defects, thereby improving the junction interface, inhibiting the intermediate energy gap impurity state, and further improving Voc and FF.

[0037] In the present embodiment, the material of the interface buffer layer 50 independently comprises one or more of oxides, nitrides, carbides, diamond lattice carbon. That is, the material of the interface buffer layer 50 can be any oxide, nitride, carbide, diamond lattice carbon or a mixture thereof. Preferably, in the present embodiment, the material of the interface buffer layer 50 independently comprises one or more of Al2O3, TiO2, SiO2, ZrO, ZnO, MgO, CdO, TeO2, WO2, MoO2, Ta2O5, Ga2O3, SiC, SiN, AlN, C. It should be noted that the material of the interface buffer layer 50 includes but is not limited to the above materials.

[0038] In the present embodiment, the thickness of the interface buffer layer 50 is between 1 and 1000 nm. Table 2 shows the relationship between the thickness of the interface buffer layer 50 and the battery efficiency.

[0039] Table 2 Relationship between thickness of interface buffer layer 50 and battery efficiency

[0040]

[0041] The 2nd to 4th groups in Table 1 are within the scope of the present embodiment, and the 1st and 5th groups are comparative examples. As can be seen from the above table, the battery efficiency is higher when the thickness of the interface buffer layer 50 is within the predetermined range.

[0042] As Figure 1As shown, in this embodiment, the photovoltaic device further comprises a back contact buffer layer 70, the back contact buffer layer 70 is a high resistivity transparent layer, the back contact buffer layer 70 is located between the absorber layer 60 and the back contact layer 80. Table 3 shows the relationship between the presence of the back contact buffer layer and Voc and FF. It should be noted that high resistivity means higher than 1000 ohm.cm.

[0043] Table 3 Relationship between the presence of the back contact buffer layer 70 and Voc and FF

[0044]

[0045] As can be seen from the above table, the presence of the back contact buffer layer can increase the back contact resistance, thereby increasing Voc and FF.

[0046] In this embodiment, the material of the back contact buffer layer 70 independently comprises one or more of oxides, nitrides, carbides, diamond lattice carbon; the material of the back contact buffer layer 70 can be any oxide, nitride, carbide, diamond lattice carbon or mixture thereof. Preferably, the material of the back contact buffer layer 70 independently comprises one or more of Al2O3, TiO2, SiO2, ZrO, ZnO, MgO, CdO, TeO2, WO2, MoO2, Ta2O5, Ga2O3, SiC, SiN, AlN, C. It should be noted that the material of the back contact buffer layer 70 includes but is not limited to the above-mentioned materials.

[0047] In this embodiment, the thickness of the back contact buffer layer 70 is between 1 to 1000 nm. Table 4 shows the relationship between the thickness of the back contact buffer layer 70 and the battery efficiency.

[0048] Table 4 Relationship between the thickness of the back contact buffer layer 70 and the battery efficiency

[0049]

[0050] The 2nd to 4th groups in Table 4 are within the scope of this embodiment, and the 1st and 5th groups are comparative examples. As can be seen from the above table, if the thickness of the back contact buffer layer 70 is within the predetermined range, the battery efficiency is higher. It should be noted that if the thickness of the back contact buffer layer 70 is too thick, the voltage will be wasted, and the open circuit voltage Voc will decrease.

[0051] It should be noted that the HRT buffer layer 30, the interface buffer layer 50 and the back contact buffer layer 70 can be deposited by many different techniques, including but not limited to APCVD, ALD, PVD, CBD, printing, spin coating, etc. After depositing each buffer layer, some post-processing may be required, such as thermal annealing or etching in some environments.

[0052] In this embodiment, the substrate 10 is typically soda lime glass, low iron glass, quartz or borosilicate glass. The transparent conductive layer 20, i.e. the TCO layer, functions as the front contact. Common materials for the TCO layer include fluorine-doped tin oxide (FTO) and indium tin oxide (ITO). The window layer 40 CdS(e) is an N-type semiconductor. It absorbs some of the photons. Thinner CdS(e) layers can produce higher current. The absorber layer 60 is the light absorber CdTe, which is a P-type semiconductor. The CdTe layer is about 0.5 to 10 microns thick, and it absorbs the photons that pass through the CdS(e) layer and converts them into electrical carriers. The back contact layer 80 is typically one or more layers of metal, such as Mo, Al and Cr, etc., or graphite paste.

[0053] The photovoltaic device of embodiment two differs from the photovoltaic device of embodiment one in the number of sub-back contact buffer layers. In embodiment two, the back contact buffer layer 70 includes m layers of sub-back contact buffer layers (not shown in the figure), m > 2, the mth layer of sub-back contact buffer layer is located between the (m-1)th layer of sub-back contact buffer layer and the back contact layer 80, and the electrical resistance of the latter layer of sub-back contact buffer layer is higher than that of the former layer of sub-back contact buffer layer. The above structure can on the one hand increase the back contact resistance, thereby increasing Voc and FF. On the other hand, it can reduce the thickness of the back contact buffer layer 70, thereby reducing the waste of voltage and further increasing Voc.

[0054] In embodiment two, the material of each sub-back contact buffer layer independently includes one or more of oxide, nitride, carbide, diamond lattice carbon. The material of the sub-back contact buffer layer can be any oxide, nitride, carbide, diamond lattice carbon or mixture thereof. Preferably, in embodiment two, the material of each sub-back contact buffer layer independently includes one or more of Al2O3, TiO2, SiO2, ZrO, ZnO, MgO, CdO, TeO2, WO2, MoO2, Ta2O5, Ga2O3, SiC, SiN, AlN, C. It should be noted that the material of each sub-back contact buffer layer includes but is not limited to the above materials.

[0055] The foregoing is considered as illustrative only of the principles of the application. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the application to the exact construction and operation described. Accordingly, all such variations are intended to be included within the scope of the present application as defined in the claims. The application is also not limited to the details of the foregoing embodiment.

[0056] For purposes of the description hereinafter, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall relate to the application as it is oriented in use. Therein, the term "horizontal" shall relate to a direction that is from left to right in the drawings, the term "vertical" shall relate to a direction that is from bottom to top in the drawings, and the term "diagonal" shall relate to a direction that is from lower left to upper right in the drawings. Where a term is provided in the singular tense, the inventors also contemplate aspects of the present application in the plural tense unless otherwise specified herein.

[0057] In the description of the present application, it is to be understood that the specific locations of the terms "front", "back", "up", "down", "left", "right", "lateral", "vertical", "horizontal", and "top", "bottom" and the like are made only with reference to the position of the drawings as shown and that such terms are used only to facilitate the description of the application and are not intended to limit the scope of the application. The terms "inner", "outer" refer to the inner and outer contours of the components themselves.

[0058] The above description is implemented by the preferred embodiments of the present application. The present application can be variously changed and modified by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of the present application.

Claims

1. A photovoltaic device, characterized in that, include: The stacked layers include a plate (10), a light-transmitting conductive layer (20), an HRT buffer layer (30), a window layer (40), an absorption layer (60), and a back contact layer (80). The HRT buffer layer (30) includes n sub-HRT buffer layers (31), where n ≥ 2. The nth sub-HRT buffer layer (31) is located between the (n-1)th sub-HRT buffer layer (31) and the window layer (40). The resistance of the next sub-HRT buffer layer (31) is higher than that of the previous sub-HRT buffer layer (31). An interface buffer layer (50) is located between the window layer (40) and the absorption layer (60), and the lattice length of the material of the interface buffer layer (50) is between the lattice length of the material of the window layer (40) and the lattice length of the material of the absorption layer (60). A back contact buffer layer (70) is a high resistivity transparent layer. The back contact buffer layer (70) is located between the absorption layer (60) and the back contact layer (80). The back contact buffer layer (70) includes m sub-back contact buffer layers, where m ≥ 2. The m-th sub-back contact buffer layer is located between the (m-1)-th sub-back contact buffer layer and the back contact layer (80). The resistance of the later sub-back contact buffer layer is higher than that of the previous sub-back contact buffer layer.

2. The photovoltaic device according to claim 1, characterized in that, The material of each of the sub-HRT buffer layers (31) independently includes one or more of oxides, nitrides, carbides, and diamond lattice carbon.

3. The photovoltaic device according to claim 2, characterized in that, The material of each of the sub-HRT buffer layers (31) independently includes one or more of Al2O3, TiO2, SiO2, ZrO, ZnO, MgO, CdO, TeO2, WO2, MoO2, Ta2O5, Ga2O3, SiC, SiN, AlN, and C.

4. The photovoltaic device according to claim 1, characterized in that, The thickness of the HRT buffer layer (30) is between 10 and 1000 nm.

5. The photovoltaic device according to claim 1, characterized in that, The material of the interface buffer layer (50) independently includes one or more of oxides, nitrides, carbides, and diamond lattice carbon.

6. The photovoltaic device according to claim 1, characterized in that, The material of the interface buffer layer (50) independently includes one or more of Al2O3, TiO2, SiO2, ZrO, ZnO, MgO, CdO, TeO2, WO2, MoO2, Ta2O5, Ga2O3, SiC, SiN, AlN, and C.

7. The photovoltaic device according to claim 1, characterized in that, The thickness of the interface buffer layer (50) is between 1 and 1000 nm.

8. The photovoltaic device according to claim 1, characterized in that, When the back contact buffer layer (70) is a single layer, the material of the back contact buffer layer (70) independently includes one or more of oxides, nitrides, carbides, and diamond lattice carbon; when the back contact buffer layer (70) includes multiple sub-back contact buffer layers, the material of each sub-back contact buffer layer independently includes one or more of oxides, nitrides, carbides, and diamond lattice carbon.

9. The photovoltaic device according to claim 1, characterized in that, When the back contact buffer layer (70) is a single layer, the material of the back contact buffer layer (70) independently includes one or more of Al2O3, TiO2, SiO2, ZrO, ZnO, MgO, CdO, TeO2, WO2, MoO2, Ta2O5, Ga2O3, SiC, SiN, AlN, and C; when the back contact buffer layer (70) includes multiple sub-back contact buffer layers, the material of each sub-back contact buffer layer independently includes one or more of Al2O3, TiO2, SiO2, ZrO, ZnO, MgO, CdO, TeO2, WO2, MoO2, Ta2O5, Ga2O3, SiC, SiN, AlN, and C.

10. The photovoltaic device according to claim 1, characterized in that, The thickness of the back contact buffer layer (70) is between 1 and 1000 nm.

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