Common-Mode Voltage Suppression Modulation Method Based on Three-Phase T-Type Three-Level Dual-Output Inverter

Abstract

The present invention relates to the technical field of power electronic conversion devices, and is a method for suppressing common mode voltage modulation based on a three-phase T-type three-level dual-output inverter. The method is characterized by comprising two DC side capacitors at the input end, 18 power switches, and a circuit at the T S / 4 places and 3T S / 4, and alternately perform the operation mode 1 and the operation mode 2. By equating the high-amplitude common-mode voltage small vector to a virtual voltage vector, the basic vectors constituting the virtual vector in each small sector are switched smoothly, avoiding the direct switching between state P and state N between adjacent basic vectors. When the upper and lower groups of outputs are in the effective working mode respectively, the common-mode voltage u of the inverter stage 1 is converted into the value of the inverter stage 1. CM1 Inhibition in ‑U d / 6~U d / 2, common mode voltage u of inverter stage 2 CM2 Inhibition in ‑U d / 2~U d / 6, and within a certain modulation range, there are only four switching actions in one switching cycle to reduce switching losses.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic conversion devices, in particular to a common mode voltage suppression modulation method based on a three-phase T-type three-level dual-output inverter. Background Art

[0002] An inverter, a converter that directly converts DC power into AC power, can power AC loads, but it can only convert DC power into a set of three-phase AC outputs. Dual AC output systems are becoming increasingly important in wind power generation systems, electric vehicles, and rail traction. Some researchers have proposed a three-phase, T-type, three-level, dual-output inverter. This design not only offers better suitability for high-voltage, high-power applications, but also reduces voltage stress on the switches compared to two-level inverters, resulting in a more sinusoidal output waveform, reducing device size and cost. However, the common-mode current generated by the inverter's common-mode voltage, when flowing through the load, induces high-amplitude shaft voltage on the motor shaft and generates bearing currents, which can damage the motor's bearings in a short period of time and shorten its service life. Furthermore, the high-frequency, continuous operation of the switching devices generates significant switching losses, reducing inverter efficiency and further exacerbating the negative impact of the common-mode voltage. Currently, research on three-level, dual-output inverters is limited, and there are no reports or practical applications of modulation methods to optimize the performance of three-phase, T-type, three-level, dual-output inverters. Summary of the Invention

[0003] The purpose of the present invention is to propose a scientific, reasonable, highly applicable and effective common-mode voltage suppression modulation method based on a three-phase T-type three-level dual-output inverter. When the upper and lower output groups of the three-phase T-type three-level dual-output inverter are respectively in an effective working mode, the common-mode voltage can be suppressed, and within a certain modulation range, only four switching operations are performed in one switching cycle, thereby reducing switching losses.

[0004] The technical solution adopted to achieve the purpose of the present invention is a common mode voltage suppression modulation method based on a three-phase T-type three-level dual-output inverter, comprising: a three-phase T-type three-level dual-output inverter, the three-phase T-type three-level dual-output inverter comprising a DC side capacitor C1 and a capacitor C2 at the input end, 18 power switches and 18 diodes, the three-phase T-type three-level dual-output inverter having A-phase, B-phase and C-phase bridge arms, each of the A-phase, B-phase and C-phase bridge arms having 6 power switches S x1 ~S x6 and 6 diodes D x1 ~D x6Composition, wherein x∈{A, B, C}; the capacitance values of the DC side capacitor C1 and the capacitor C2 of the three-phase T-type three-level dual-output inverter are equal, the positive electrode of the capacitor C1 is connected to the positive terminal P of the DC bus, the negative electrode of the capacitor C1 is connected to the positive electrode of the capacitor C2, and the point where the negative electrode of the capacitor C1 and the positive electrode of the capacitor C2 are connected is defined as the DC neutral point O, whose potential is 0, the negative electrode of the capacitor C2 is connected to the negative terminal N of the DC bus, and the DC side input voltage between the positive terminal P and the negative terminal N is U d , the voltage between the positive terminal P and the neutral point O is U d / 2, the voltage between the neutral point O and the negative terminal is U d / 2; define the two sets of outputs of the inverter as inverter stage 1 and inverter stage 2, the output terminal of inverter stage 1 is defined as x1, and the output phase voltage of inverter stage 1 is defined as u x1O , the output terminal of inverter stage 2 is defined as x2, and the output phase voltage of inverter stage 2 is defined as u x2O , where x∈{A, B, C}; the inverter output terminals x1 and x2 are connected to two groups of three-phase loads respectively, and x1 is connected to the three-phase load Z x1 Connected, x2 and three-phase load Z x2 Connected, three-phase load Z x1 The neutral point is defined as n1, and the three-phase load Z x2 The neutral point is defined as n2, where x∈{A, B, C}; wherein the method further comprises a common mode voltage suppression modulation method, wherein the modulation method comprises:

[0005] The three-phase T-type three-level dual-output inverter has two working modes. Working mode 1 is the effective working state of inverter stage 1, and working mode 2 is the effective working state of inverter stage 2. When in working mode 1, the power switch S of each phase is kept x2 and S x6 When in the working mode 2, keep the power switch S of each phase x1 and S x5 conduction;

[0006] The working mode 1 includes three switch states: switch state 1_1, switch state 1_2 and switch state 1_3;

[0007] ① The switch state 1_1: power switch S x1 、S x2 and S x6 If the current flows from the inverter to the load, the current flows through the power switch S x1 and three-phase load Z x1 , the potential of the output terminal x1 is equal to the potential of point P, at this time the output phase voltage u x1O For U d / 2; if the current flows from the load to the inverter, the current flows through the three-phase load Z x1 and diode D x1 , the potential of the output terminal x1 is equal to the potential of point P;

[0008] ② The switch state 1_2: power switch S x2 、S x3 、S x4 and S x6 If the current flows from the inverter to the load, the current flows through the power switch S x3 , diode D x4 、D x2 and three-phase load Z x1 , the potential of the output terminal x1 is equal to the potential of point O, at this time the output phase voltage u x1O is 0; if the current flows from the load to the inverter, the current flows through the three-phase load Z x1 , power switch S x2 、S x4 and diode D x3 , the potential of the output terminal x1 is equal to the potential of point O;

[0009] ③ The switch state 1_3: power switch S x2 、S x5 and S x6 If the current flows from the inverter to the load, the current flows through the diode D x6 、D x5 、D x2 and three-phase load Z x1 , the potential of the output terminal x1 is equal to the potential of point N, at this time the output phase voltage u x1O -U d / 2; if the current flows from the load to the inverter, the current flows through the three-phase load Z x1 , power switch S x2 、S x5 and S x6 , the potential of the output terminal x1 is equal to the potential of point N;

[0010] The working mode 2 includes three switch states: switch state 2_1, switch state 2_2 and switch state 2_3;

[0011] i. Switching state 2_1 of the working mode 2: power switch S x1 、S x2 and S x5 If the current flows from the inverter to the load, the current flows through the power switch S x1 、S x2 、S x5 and three-phase load Z x2, the potential of the output terminal x2 is equal to the potential of point P, at this time the output phase voltage u x2O For U d / 2; if the current flows from the load to the inverter, the current flows through the three-phase load Z x2 , diode D x5 、D x2 and D x1 , the potential of the output terminal x2 is equal to the potential of point P;

[0012] ii. Switching state 2_2 of the operating mode 2: power switch S x1 、S x3 、S x4 and S x5 If the current flows from the inverter to the load, the current flows through the power switch S x3 , diode D x4 , power switch S x5 and three-phase load Z x2 , the output terminal x2 potential is equal to the potential of point O, at this time the inverter stage 2 output phase voltage u x2O is 0; if the current flows from the load to the inverter, the current flows through the three-phase load Z x2 , diode D x5 , power switch S x4 and diode D x3 , the potential of the output terminal x2 is equal to the potential of point O;

[0013] iii. Switching state 2_3 of the operating mode 2: power switch S x1 、S x5 and S x6 If the current flows from the inverter to the load, the current flows through the diode D x6 and three-phase load Z x2 , the potential of the output terminal x2 is equal to the potential of point N, at this time the output phase voltage u x2O -U d / 2; if the current flows from the load to the inverter, the current flows through the three-phase load Z x2 and power switch S x6 , the potential of the output terminal x2 is equal to the potential of point N;

[0014] According to the power switch S x1 ~S x6 The on and off states are defined, and the output levels of the two inverter stages corresponding to each switching state of the working mode 1 and the working mode 2 are redefined; in one switching cycle T S Evenly distribute the working time within the circuit, and modulate the inverter level 1 and inverter level 2 in different time periods. S / 4 places and 3T S / 4, the operation of working mode 1 and working mode 2 is alternated; S / 4 and 3T S / 4~T S During the switching cycle, in the working mode 1, when the output level of the inverter stage 1 is P, the output phase voltage u x1O For U d / 2; when the output level of inverter stage 1 is 0, the output phase voltage u x1O When the output level of inverter stage 1 is N, the output phase voltage u x1O -U d / 2; at this time, the output level of inverter stage 2 remains at N', and the output phase voltage u x2O -U d / 2; in T S / 4~3T S In the / 4 switching cycle, in the working mode 2, when the output level of the inverter stage 2 is P', the output phase voltage u x2O For U d / 2; when the output level of inverter stage 2 is O', the output phase voltage u x2O When the output level of inverter stage 2 is N', the output phase voltage u x2O -U d / 2; at this time, the output level of inverter stage 1 remains at P, and the output phase voltage u x1O For U d / 2;

[0015] The three-phase output phase voltages of the inverter stage 1 and the inverter stage 2 are respectively combined into a space voltage vector. The space voltage vectors of the inverter stage 1 and the inverter stage 2 are the same. For the space voltage vector of the inverter stage 1, the voltage vector amplitude is 2U d The six large vectors of / 3 have the corresponding states of the three-phase AC output terminals as PNN, PPN, NPN, NPP, NNP, and PNP respectively; the voltage vector amplitude is The six neutral vectors of the three-phase AC output terminals are PON, OPN, NPO, NOP, ONP, and PNO respectively; the voltage vector amplitude is U d / 3, the corresponding states of the three-phase AC output terminals are POO, PPO, OPO, OPP, OOP, POP; the voltage vector amplitude is U d / 3, and their corresponding states at the three-phase AC output terminals are ONN, OON, NON, NOO, NNO, and ONO respectively; the three zero vectors with a voltage vector amplitude of 0, and their corresponding states at the three-phase AC output terminals are PPP, OOO, and NNN respectively; the zero vector is located at the center of all vectors, the P-type small vector and the N-type small vector are redundant vectors that appear in pairs, with the same direction as the large vector and an amplitude half of the large vector, and the middle vector is located on the midline of the triangle formed by the large vectors; the spatial voltage vector is divided into six large sectors A~F, and each large sector is divided into four small sectors X1~X4, X∈{A~F};

[0016] Define common mode voltage u CM is the voltage value of the load neutral point relative to the reference ground, and the reference ground is taken as the midpoint O of the DC side capacitor, then the common mode voltage u of the inverter stage 1 is CM1 Expressed as:

[0017]

[0018] The common mode voltage u of the inverter stage 2 CM2 Expressed as:

[0019]

[0020] Substituting each basic voltage vector into the common mode voltage expression, the common mode voltage magnitude corresponding to all space voltage vectors can be derived;

[0021] For the large sector A, the small vector ONN is equivalent to half of the vector synthesized by the small vector OON and the medium vector PNO; the small vector PPO is equivalent to half of the vector synthesized by the small vector POO and the medium vector OPN; the common mode voltage is ±U d The small vector of / 3 is equivalent to a virtual voltage vector linearly combined with the small vector with a smaller common mode voltage amplitude and the medium vector. Then the virtual voltage vector and the basic voltage vector constructed in the large sector A are:

[0022]

[0023] Among them, V S1_1 、V S2_1 is the basic voltage vector, V S1_2 、V S2_2 The virtual voltage vector constructed has an output average current of zero and does not have the ability to control the midpoint potential. To ensure smooth switching of the output voltage vector sequence, the basic voltage vector V S1_1 and virtual voltage vector V S1_2 ; In the small sector A4, the basic voltage vector V is used simultaneously S2_1 and virtual voltage vector V S2_2 ;

[0024] The three-phase output reference voltage of inverter stage 1 is:

[0025]

[0026] Among them, U m1 is the output phase voltage amplitude of inverter stage 1, ω1 is the angular frequency of the output voltage of inverter stage 1, is the initial phase angle of the output voltage of inverter stage 1;

[0027] The three-phase output reference voltage of inverter stage 2 is:

[0028]

[0029] Among them, U m2 is the output phase voltage amplitude of inverter stage 2, ω2 is the angular frequency of the output voltage of inverter stage 2, is the initial phase angle of the output voltage of inverter stage 2;

[0030] The two reference voltage vector formulas can be obtained as follows:

[0031]

[0032] Assume that the output reference voltage vector U of inverter stage 1 and inverter stage 2 is ref1 and U ref2 Located in sectors A1 and A1' respectively, the space voltage vector of the synthetic reference voltage vector is obtained according to the nearest three vector principle, and the action time of each voltage vector is calculated using the volt-second balance principle; it can be seen from the two reference voltage vector formulas that a switching cycle T S The inner inverter stage 1 and the inverter stage 2 work alternately, so the sum of the duty cycles of each inverter stage is 1 / 2; thus:

[0033]

[0034]

[0035] Among them, d1, d2, and d3 are the duty cycles of the effective vector of inverter stage 1 respectively; d1', d2', and d3' are the duty cycles of the effective vector of inverter stage 2 respectively; when the operation is in mode 1 or the operation mode 2, the output voltage vector sequence meets the following principles: a virtual voltage vector is used to replace the common mode voltage with a magnitude of ±U dThe basic voltage vector of / 3 ensures that only one phase changes when adjacent switch states in the output sequence switch, and there is no direct switching between state P and state N. When the reference voltage vector moves from one sector to the next, it follows the principle of minimum switching, and therefore an N-type small vector is selected as the starting vector. A symmetrical pulse sequence is used to reduce harmonics. When the reference voltage vector is located in small sector A1 (A1') or A2 (A2'), the vector involved in the synthesis involves only the basic voltage vector. The output terminal B2 is clamped at the zero level in operating mode 2. Only four switching operations occur in one switching cycle, resulting in low switching losses.

[0036] The present invention discloses a method for suppressing common-mode voltage modulation based on a three-phase T-type three-level dual-output inverter. By converting a small high-amplitude common-mode voltage vector into a virtual voltage vector, the basic vectors constituting the virtual vector in each small sector are smoothly switched, thereby avoiding direct switching between state P and state N between adjacent basic vectors. When the upper and lower output groups are in effective working modes, the common-mode voltage u of the inverter stage 1 is converted into the effective working mode by combining time-sharing modulation. CM1 Suppressed in -U d / 6~U d / 2, common mode voltage u of inverter stage 2 CM2 Suppressed in -U d / 2~U d / 6 or less, and within a certain modulation range, there are only four switching actions in one switching cycle, which reduces switching losses and increases the service life of the switch. It has the advantages of scientific rationality, strong applicability and good effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is the topology diagram of a three-phase T-type three-level dual-output inverter;

[0038] Figure 2 This is the working principle diagram of switch state 1_1 in mode 1;

[0039] Figure 3 This is the working principle diagram of switch state 1_2 in mode 1;

[0040] Figure 4 This is the working principle diagram of switch state 1_3 in mode 1;

[0041] Figure 5 This is the working principle diagram of switch state 2_1 in mode 2;

[0042] Figure 6 This is the working principle diagram of switch state 2_2 in mode 2;

[0043] Figure 7 This is the working principle diagram of switch state 2_3 in mode 2;

[0044] Figure 8 is the space voltage vector diagram of inverter stage 1;

[0045] Figure 9 is the space voltage vector diagram of inverter stage 2;

[0046] Figure 10 It is a virtual vector composite image equivalent to the small vector ONN;

[0047] Figure 11 It is a virtual vector composite graph equivalent to the small vector PPO;

[0048] Figure 12 is the voltage vector sequence diagram of sectors A1 and A1';

[0049] Figure 13 is the voltage vector sequence diagram of sectors A3 and A3';

[0050] Figure 14 Schematic diagram of the current waveform output by inverter stage 1;

[0051] Figure 15 Schematic diagram of the current waveform output by inverter stage 2;

[0052] Figure 16 is the output line voltage u of inverter stage 1 A1B1 Schematic diagram;

[0053] Figure 17 is the output line voltage u of inverter stage 2 A2B2 Schematic diagram;

[0054] Figure 18 is the common mode voltage u of inverter stage 1 CM1 Schematic diagram;

[0055] Figure 19 is the common mode voltage u of inverter stage 2 CM2 Schematic diagram. DETAILED DESCRIPTION

[0056] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0057] like Figure 1 As shown, a modulation method for suppressing the common mode voltage of a three-phase T-type three-level dual-output inverter of the present invention includes: a three-phase T-type three-level dual-output inverter, wherein the three-phase T-type three-level dual-output inverter includes a DC side capacitor C1 and a capacitor C2 at the input end, 18 power switches and 18 diodes, and the three-phase T-type three-level dual-output inverter has A-phase, B-phase and C-phase bridge arms, and each phase bridge arm of the A-phase, B-phase and C-phase bridge arms is composed of 6 power switches S x1 ~S x6 and 6 diodes D x1 ~Dx6 Composition, wherein x∈{A, B, C}; the capacitance values of the DC side capacitor C1 and the capacitor C2 of the three-phase T-type three-level dual-output inverter are equal, the positive electrode of the capacitor C1 is connected to the positive terminal P of the DC bus, the negative electrode of the capacitor C1 is connected to the positive electrode of the capacitor C2, and the point where the negative electrode of the capacitor C1 and the positive electrode of the capacitor C2 are connected is defined as the DC neutral point O, whose potential is 0, the negative electrode of the capacitor C2 is connected to the negative terminal N of the DC bus, and the DC side input voltage between the positive terminal P and the negative terminal N is U d , the voltage between the positive terminal P and the neutral point O is U d / 2, the voltage between the neutral point O and the negative terminal is U d / 2; define the two sets of outputs of the inverter as inverter stage 1 and inverter stage 2, the output terminal of inverter stage 1 is defined as x1, and the output phase voltage of inverter stage 1 is defined as u x1O , the output terminal of inverter stage 2 is defined as x2, and the output phase voltage of inverter stage 2 is defined as u x2O , where x∈{A, B, C}; the inverter output terminals x1 and x2 are connected to two groups of three-phase loads respectively, and x1 is connected to the three-phase load Z x1 Connected, x2 and three-phase load Z x2 Connected, three-phase load Z x1 The neutral point is defined as n1, and the three-phase load Z x2 The neutral point is defined as n2, where x∈{A, B, C}; and a common mode voltage suppression modulation method is also included, wherein the modulation method includes:

[0058] The three-phase T-type three-level dual-output inverter has two working modes. Working mode 1 is the effective working state of inverter stage 1, and working mode 2 is the effective working state of inverter stage 2. When in working mode 1, the power switch S of each phase is kept x2 and S x6 When in the working mode 2, keep the power switch S of each phase x1 and S x5 conduction.

[0059] The working mode 1 includes three switch states: switch state 1_1, switch state 1_2 and switch state 1_3, respectively. Figure 2 、 Figure 3 and Figure 4 As shown;

[0060] ① The switch state 1_1: power switch S x1 、S x2 and S x6 If the current flows from the inverter to the load, the current flows through the power switch S x1 and three-phase load Z x1 ,like Figure 2 As shown by the long dashed line, the potential of the output terminal x1 is equal to the potential of point P. At this time, the output phase voltage u x1O For U d / 2; if the current flows from the load to the inverter, the current flows through the three-phase load Z x1 and diode D x1 , the potential of the output terminal x1 is equal to the potential of point P;

[0061] ② The switch state 1_2: power switch S x2 、S x3 、S x4 and S x6 If the current flows from the inverter to the load, the current flows through the power switch S x3 , diode D x4 、D x2 and three-phase load Z x1 ,like Figure 3 As shown by the long dashed line, the potential of the output terminal x1 is equal to the potential of point O. At this time, the output phase voltage u x1O is 0; if the current flows from the load to the inverter, the current flows through the three-phase load Z x1 , power switch S x2 、S x4 and diode D x3 , the potential of the output terminal x1 is equal to the potential of point O;

[0062] ③ The switch state 1_3: power switch S x2 、S x5 and S x6 If the current flows from the inverter to the load, the current flows through the diode D x6 、D x5 、D x2 and three-phase load Z x1 ,like Figure 4 As shown by the long dashed line, the potential of the output terminal x1 is equal to the potential of point N. At this time, the output phase voltage u x1O -U d / 2; if the current flows from the load to the inverter, the current flows through the three-phase load Z x1 , power switch S x2 、S x5 and S x6 , the potential of the output terminal x1 is equal to the potential of point N.

[0063] The working mode 2 of the three-phase T-type three-level dual-output inverter includes three switching states: switching state 2_1, switching state 2_2 and switching state 2_3, respectively. Figure 5 、 Figure 6 and Figure 7 As shown;

[0064] i. Switching state 2_1 of the working mode 2: power switch S x1 、S x2 and S x5 If the current flows from the inverter to the load, the current flows through the power switch S x1 、S x2 、S x5 and three-phase load Z x2 ,like Figure 5 As shown by the long dashed line, the potential of the output terminal x2 is equal to the potential of point P. At this time, the output phase voltage u x2O For U d / 2; if the current flows from the load to the inverter, the current flows through the three-phase load Z x2 , diode D x5 、D x2 and D x1 , the potential of the output terminal x2 is equal to the potential of point P;

[0065] ii. Switching state 2_2 of the operating mode 2: power switch S x1 、S x3 、S x4 and S x5 If the current flows from the inverter to the load, the current flows through the power switch S x3 , diode D x4 , power switch S x5 and three-phase load Z x2 ,like Figure 6 As shown by the long dashed line, the potential of the output terminal x2 is equal to the potential of point O. At this time, the output phase voltage u x2O is 0; if the current flows from the load to the inverter, the current flows through the three-phase load Z x2 , diode D x5 , power switch S x4 and diode D x3 , the potential of the output terminal x2 is equal to the potential of point O;

[0066] iii. Switching state 2_3 of the operating mode 2: power switch S x1 、S x5 and S x6 If the current flows from the inverter to the load, the current flows through the diode D x6 and three-phase load Z x2 ,like Figure 7 As shown by the long dashed line, the potential of the output terminal x2 is equal to the potential of point N. At this time, the output phase voltage u x2O -U d / 2; if the current flows from the load to the inverter, the current flows through the three-phase load Z x2 and power switch S x6, the potential of the output terminal x2 is equal to the potential of point N.

[0067] Table 1 Relationship between switching state and output level of three-phase T-type three-level dual-output inverter

[0068]

[0069] Table 1 summarizes the power switch S according to the above working principle. x1 ~S x6 The on and off states of the power switch S x1 ~S x6 Each switching state corresponds to the two inverter output levels. In a switching cycle T S Evenly distribute the working time within the circuit, and modulate the inverter level 1 and inverter level 2 in different time periods. S / 4 places and 3T S / 4, the operation of working mode 1 and working mode 2 is alternated. S / 4 and 3T S / 4~T S During the switching cycle, when the output level of the inverter stage 1 is P, the output phase voltage u x1O For U d / 2; when the output level of inverter stage 1 is 0, the output phase voltage u x1O When the output level of inverter stage 1 is N, the output phase voltage u x1O -U d / 2; at this time, the output level of inverter stage 2 remains at N', and the output phase voltage u x2O -U d / 2. In T S / 4~3T S / 4 switching cycle, in the working mode 2, when the output level of the inverter stage 2 is P', the output phase voltage u x2O For U d / 2; when the output level of inverter stage 2 is O', the output phase voltage u x2O When the output level of inverter stage 2 is N', the output phase voltage u x2O -U d / 2; at this time, the output level of inverter stage 1 remains at P, and the output phase voltage u x1O For U d / 2.

[0070] Figure 8 、 Figure 9They are space voltage vector diagrams of inverter stage 1 and inverter stage 2 respectively. The three-phase output phase voltages of inverter stage 1 and inverter stage 2 are respectively combined into space voltage vectors. The space voltage vectors of inverter stage 1 and inverter stage 2 are the same. Taking inverter stage 1 as an example for detailed description, the space voltage vector diagram of inverter stage 1 is as follows: Figure 8 As shown, it includes a voltage vector amplitude of 2U d The six large vectors of / 3 have the corresponding states of the three-phase AC output terminals as PNN, PPN, NPN, NPP, NNP, and PNP respectively; the voltage vector amplitude is The six neutral vectors of the three-phase AC output terminals are PON, OPN, NPO, NOP, ONP, and PNO respectively; the voltage vector amplitude is U d / 3, the corresponding states of the three-phase AC output terminals are POO, PPO, OPO, OPP, OOP, POP; the voltage vector amplitude is U d The six N-type small vectors with a voltage vector amplitude of 0 / 3 correspond to the three-phase AC output states of ONN, OON, NON, NOO, NNO, and ONO, respectively. The three zero vectors with a voltage vector amplitude of 0 correspond to the three-phase AC output states of PPP, OOO, and NNN, respectively. The zero vector is located at the center of all vectors. The P-type small vectors and the N-type small vectors are redundant vectors and appear in pairs, aligning with the direction of the large vector and having an amplitude half that of the large vector. The center vector is located on the midline of the triangle formed by the large vectors. The spatial voltage vector is divided into six large sectors A to F, each of which is further divided into four small sectors X1 to X4, where X∈{A to F}.

[0071] Define common mode voltage u CM is the voltage value of the load neutral point relative to the reference ground. The reference ground is taken as the midpoint O of the DC side capacitor. Then the common mode voltage u of the inverter stage 1 is CM1 Expressed as:

[0072]

[0073] Common mode voltage u of inverter stage 2 CM2 It can be expressed as:

[0074]

[0075] By substituting each basic voltage vector into the common-mode voltage expression, the common-mode voltage corresponding to all space voltage vectors can be derived. The results of the derivation and calculation are shown in Table 2.

[0076] Table 2 Common mode voltage magnitude corresponding to each space voltage vector

[0077]

[0078] Take large sector A as an example, Figure 10 As shown, the small vector ONN is equivalent to half of the vector synthesized by the small vector OON and the middle vector PNO; Figure 11 As shown, the small vector PPO is equivalent to half of the vector synthesized by the small vector POO and the medium vector OPN; the common mode voltage is ±U d The small vector of / 3 is equivalent to a virtual voltage vector that is a linear combination of a small vector with a smaller common-mode voltage amplitude and a medium vector. The virtual voltage vector and the basic voltage vector constructed in the large sector A are as follows:

[0079]

[0080] In formula (3), V S1_1 、V S2_1 is the basic voltage vector, V S1_2 、V S2_2 The virtual voltage vector constructed has an output average current of zero and does not have the ability to control the midpoint potential. To ensure smooth switching of the output voltage vector sequence, the basic voltage vector V S1_1 and virtual voltage vector V S1_2 ; In the small sector A4, the basic voltage vector V is used simultaneously S2_1 and virtual voltage vector V S2_2 .

[0081] The three-phase output reference voltage of inverter stage 1 is:

[0082]

[0083] Among them, U m1 is the output phase voltage amplitude of inverter stage 1, ω1 is the angular frequency of the output voltage of inverter stage 1, is the initial phase angle of the output voltage of inverter stage 1.

[0084] The three-phase output reference voltage of inverter stage 2 is:

[0085]

[0086] Among them, U m2 is the output phase voltage amplitude of inverter stage 2, ω2 is the angular frequency of the output voltage of inverter stage 2, is the initial phase angle of the output voltage of inverter stage 2.

[0087] The two reference voltage vector formulas can be obtained as follows:

[0088]

[0089] Assume that the output reference voltage vector U of inverter stage 1 and inverter stage 2 is ref1 and U ref2Located in sectors A1 and A1' respectively, the space voltage vector of the synthetic reference voltage vector is obtained according to the nearest three vector principle, and the action time of each voltage vector is calculated using the volt-second balance principle. From formula (6), it can be seen that a switching cycle T S The inner inverter stage 1 and the inverter stage 2 work alternately, so the sum of the duty cycles of each inverter stage is 1 / 2. From this, we can get:

[0090]

[0091]

[0092] In formula (7) and formula (8), d1, d2, and d3 are the duty cycles of the effective vector of inverter stage 1; d1', d2', and d3' are the duty cycles of the effective vector of inverter stage 2. When the operation is in mode 1 or mode 2, the output voltage vector sequence satisfies the following principle: a virtual voltage vector is used to replace the common mode voltage with a magnitude of ±U d The basic voltage vector of / 3 ensures that only one phase changes when adjacent switch states of the output sequence are switched, and there is no direct switching between state P and state N. When the reference voltage vector moves from one sector to the next, it follows the principle of minimum switching, so an N-type small vector is selected as the starting vector. A symmetrical pulse sequence is used to reduce harmonics.

[0093] Figure 12 and Figure 13 According to the above rules for generating voltage vector sequence, the following are listed respectively when U ref1 and U ref2 The voltage vector sequence and the action time of each vector in sectors A1, A1' and sectors A3, A3'.

[0094] Table 3 Voltage vector sequence of each small sector in sector A

[0095]

[0096] Taking large sector A as an example, the vector sequences for its small sectors are summarized in Table 3. The voltage vector sequences for other large sectors are derived similarly. Table 3 shows that when the reference voltage vector is located in small sectors A1 (A1') or A2 (A2'), the vectors involved in the synthesis only involve the basic voltage vector. Output terminal B2 is clamped to zero when the inverter operates in Mode 2, resulting in only four switching operations per switching cycle, reducing switching losses.

[0097] To verify the feasibility of the proposed three-phase T-type three-level dual-output inverter and the effectiveness of the common-mode voltage modulation suppression method, simulations were performed using MATLAB / Simulink. The simulation parameters were as follows: a switching frequency of 10 kHz; a DC power supply voltage of 200 V; an 80 V amplitude and 50 Hz frequency for the three-phase output voltage of inverter stage 1; an 80 V amplitude and 60 Hz frequency for the three-phase output voltage of inverter stage 2; a 6 Ω load resistance and 25 mH inductance for the three-phase load of inverter stage 1; and a 6 Ω load resistance and 25 mH inductance for the three-phase load of inverter stage 2.

[0098] The simulation results are as follows Figures 14-19 As shown, Figure 14 The three-phase current waveform diagram of the inverter stage 1 output; Figure 15 This is the three-phase current waveform output by inverter stage 2; Figure 16 is the output line voltage u of inverter stage 1 A1B1 ; Figure 17 is the output line voltage u of inverter stage 2 A2B2 ; Figure 18 is the common mode voltage u of inverter stage 1 CM1 ; Figure 19 is the common mode voltage u of inverter stage 2 CM2 The above simulation results show that the present invention is based on a three-phase T-type three-level dual-output inverter to suppress the common-mode voltage modulation method, so that when the upper and lower output groups are in the effective working mode, the common-mode voltage u of the inverter stage 1 is CM1 Suppressed in -U d / 6~U d / 2, common mode voltage u of inverter stage 2 CM2 Suppressed in -U d / 2~U d / 6, and within a certain modulation range, there are only four switching actions in one switching cycle, which reduces switching losses and proves its effectiveness.

[0099] Although the present invention has been described above in conjunction with the accompanying drawings, the present invention is not limited to the above-mentioned specific embodiments. The above-mentioned specific embodiments are illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make other forms without departing from the purpose of the invention. These are all within the protection of the present invention.

Claims

1. A method for suppressing common-mode voltage modulation based on a three-phase T-type three-level dual-output inverter, comprising: A three-phase T-type three-level dual-output inverter includes a DC side capacitor C1 and a capacitor C2 at the input end, 18 power switches and 18 diodes. The three-phase T-type three-level dual-output inverter has A-phase, B-phase and C-phase bridge arms. Each phase of the A-phase, B-phase and C-phase bridge arms is composed of 6 power switches S x1 ~S x6 and 6 diodes D x1 ~D x6 Composition, wherein x∈{A, B, C}; the capacitance values of the DC side capacitor C1 and the capacitor C2 of the three-phase T-type three-level dual-output inverter are equal, the positive electrode of the capacitor C1 is connected to the positive terminal P of the DC bus, the negative electrode of the capacitor C1 is connected to the positive electrode of the capacitor C2, and the point where the negative electrode of the capacitor C1 and the positive electrode of the capacitor C2 are connected is defined as the DC neutral point O, whose potential is 0, the negative electrode of the capacitor C2 is connected to the negative terminal N of the DC bus, and the DC side input voltage between the positive terminal P and the negative terminal N is U d , the voltage between the positive terminal P and the neutral point O is U d / 2, the voltage between the neutral point O and the negative terminal is U d / 2; define the two sets of outputs of the inverter as inverter stage 1 and inverter stage 2, the output terminal of inverter stage 1 is defined as x1, and the output phase voltage of inverter stage 1 is defined as u x1O , the output terminal of inverter stage 2 is defined as x2, and the output phase voltage of inverter stage 2 is defined as u x2O , where x∈{A, B, C}; the inverter output terminals x1 and x2 are connected to two groups of three-phase loads respectively, and x1 is connected to the three-phase load Z x1 Connected, x2 and three-phase load Z x2 Connected, three-phase load Z x1 The neutral point is defined as n1, and the three-phase load Z x2 The neutral point is defined as n2, where x∈{A, B, C}; wherein the method further comprises a common mode voltage suppression modulation method, wherein the modulation method comprises: The three-phase T-type three-level dual-output inverter has two working modes. Working mode 1 is the effective working state of inverter stage 1, and working mode 2 is the effective working state of inverter stage 2. When in working mode 1, the power switch S of each phase is kept x2 and S x6 When in the working mode 2, keep the power switch S of each phase x1 and S x5 conduction; The working mode 1 includes three switch states: switch state 1_1, switch state 1_2 and switch state 1_3; ① The switch state 1_1: power switch S x1 、S x2 and S x6 If the current flows from the inverter to the load, the current flows through the power switch S x1 and three-phase load Z x1 , the potential of the output terminal x1 is equal to the potential of point P, at this time the output phase voltage u x1O For U d / 2; if the current flows from the load to the inverter, the current flows through the three-phase load Z x1 and diode D x1 , the potential of the output terminal x1 is equal to the potential of point P; ② The switch state 1_2: power switch S x2 、S x3 、S x4 and S x6 If the current flows from the inverter to the load, the current flows through the power switch S x3 , diode D x4 、D x2 and three-phase load Z x1 , the potential of the output terminal x1 is equal to the potential of point O, at this time the output phase voltage u x1O is 0; if the current flows from the load to the inverter, the current flows through the three-phase load Z x1 , power switch S x2 、S x4 and diode D x3 , the potential of the output terminal x1 is equal to the potential of point O; ③ The switch state 1_3: power switch S x2 、S x5 and S x6 If the current flows from the inverter to the load, the current flows through the diode D x6 、D x5 、D x2 and three-phase load Z x1 , the potential of the output terminal x1 is equal to the potential of point N, at this time the output phase voltage u x1O -U d / 2; if the current flows from the load to the inverter, the current flows through the three-phase load Z x1 , power switch S x2 、S x5 and S x6 , the potential of the output terminal x1 is equal to the potential of point N; The working mode 2 includes three switch states: switch state 2_1, switch state 2_2 and switch state 2_3; i. Switching state 2_1 of the working mode 2: power switch S x1 、S x2 and S x5 If the current flows from the inverter to the load, the current flows through the power switch S x1 、S x2 、S x5 and three-phase load Z x2 , the potential of the output terminal x2 is equal to the potential of point P, at this time the output phase voltage u x2O For U d / 2; if the current flows from the load to the inverter, the current flows through the three-phase load Z x2 , diode D x5 、D x2 and D x1 , the potential of the output terminal x2 is equal to the potential of point P; ii. Switching state 2_2 of the operating mode 2: power switch S x1 、S x3 、S x4 and S x5 If the current flows from the inverter to the load, the current flows through the power switch S x3 , diode D x4 , power switch S x5 and three-phase load Z x2 , the output terminal x2 potential is equal to the potential of point O, at this time the inverter stage 2 output phase voltage u x2O is 0; if the current flows from the load to the inverter, the current flows through the three-phase load Z x2 , diode D x5 , power switch S x4 and diode D x3 , the potential of the output terminal x2 is equal to the potential of point O; iii. Switching state 2_3 of the operating mode 2: power switch S x1 、S x5 and S x6 If the current flows from the inverter to the load, the current flows through the diode D x6 and three-phase load Z x2 , the potential of the output terminal x2 is equal to the potential of point N, at this time the output phase voltage u x2O -U d / 2; if the current flows from the load to the inverter, the current flows through the three-phase load Z x2 and power switch S x6 , the potential of the output terminal x2 is equal to the potential of point N; According to the power switch S x1 ~S x6 The on and off states are defined, and the output levels of the two inverter stages corresponding to each switching state of the working mode 1 and the working mode 2 are redefined; in one switching cycle T S Evenly distribute the working time within the time interval, and modulate the inverter level 1 and inverter level 2 in different time periods. S / 4 places and 3T S / 4, the operation of working mode 1 and working mode 2 is alternated; S / 4 and 3T S / 4~T S During the switching cycle, in the working mode 1, when the output level of the inverter stage 1 is P, the output phase voltage u x1O For U d / 2; when the output level of inverter stage 1 is 0, the output phase voltage u x1O When the output level of inverter stage 1 is N, the output phase voltage u x1O -U d / 2; at this time, the output level of inverter stage 2 remains at N', and the output phase voltage u x2O -U d / 2; in T S / 4~3T S In the / 4 switching cycle, in the working mode 2, when the output level of the inverter stage 2 is P', the output phase voltage u x2O For U d / 2; when the output level of inverter stage 2 is O', the output phase voltage u x2O When the output level of inverter stage 2 is N', the output phase voltage u x2O -U d / 2; at this time, the output level of inverter stage 1 remains at P, and the output phase voltage u x1O For U d / 2; The three-phase output phase voltages of the inverter stage 1 and the inverter stage 2 are respectively combined into a space voltage vector. The space voltage vectors of the inverter stage 1 and the inverter stage 2 are the same. For the space voltage vector of the inverter stage 1, the voltage vector amplitude is 2U d The six large vectors of / 3 have the corresponding states of the three-phase AC output terminals as PNN, PPN, NPN, NPP, NNP, and PNP respectively; the voltage vector amplitude is The six neutral vectors of the three-phase AC output terminals are PON, OPN, NPO, NOP, ONP, and PNO respectively; the voltage vector amplitude is U d / 3, the corresponding states of the three-phase AC output terminals are POO, PPO, OPO, OPP, OOP, POP; the voltage vector amplitude is U d / 3, and their corresponding states at the three-phase AC output terminals are ONN, OON, NON, NOO, NNO, and ONO respectively; the three zero vectors with a voltage vector amplitude of 0, and their corresponding states at the three-phase AC output terminals are PPP, OOO, and NNN respectively; the zero vector is located at the center of all vectors, the P-type small vector and the N-type small vector are redundant vectors that appear in pairs, with the same direction as the large vector and an amplitude half of the large vector, and the middle vector is located on the midline of the triangle formed by the large vectors; the spatial voltage vector is divided into six large sectors A~F, and each large sector is divided into four small sectors X1~X4, X∈{A~F}; Define common mode voltage u CM is the voltage value of the load neutral point relative to the reference ground, and the reference ground is taken as the midpoint O of the DC side capacitor, then the common mode voltage u of the inverter stage 1 is CM1 Expressed as: The common mode voltage u of the inverter stage 2 CM2 Expressed as: Substituting each basic voltage vector into the common-mode voltage expression, the common-mode voltage magnitude corresponding to all space voltage vectors can be derived; For the large sector A, the small vector ONN is equivalent to half of the vector synthesized by the small vector OON and the medium vector PNO; the small vector PPO is equivalent to half of the vector synthesized by the small vector POO and the medium vector OPN; the common mode voltage is ±U d The small vector of / 3 is equivalent to a virtual voltage vector linearly combined with the small vector with a smaller common mode voltage amplitude and the medium vector. Then the virtual voltage vector and the basic voltage vector constructed in the large sector A are: Among them, V S1_1 、V S2_1 is the basic voltage vector, V S1_2 、V S2_2 The virtual voltage vector constructed has an output average current of zero and does not have the ability to control the midpoint potential. To ensure smooth switching of the output voltage vector sequence, the basic voltage vector V S1_1 and virtual voltage vector V S1_2 ; In the small sector A4, the basic voltage vector V is used simultaneously S2_1 and virtual voltage vector V S2_2 ; The three-phase output reference voltage of inverter stage 1 is: Among them, U m1 is the output phase voltage amplitude of inverter stage 1, ω1 is the angular frequency of the output voltage of inverter stage 1, is the initial phase angle of the output voltage of inverter stage 1; The three-phase output reference voltage of inverter stage 2 is: Among them, U m2 is the output phase voltage amplitude of inverter stage 2, ω2 is the angular frequency of the output voltage of inverter stage 2, is the initial phase angle of the output voltage of inverter stage 2; The two reference voltage vector formulas can be obtained as follows: Assume that the output reference voltage vector U of inverter stage 1 and inverter stage 2 is ref1 and U ref2 Located in sectors A1 and A1' respectively, the space voltage vector of the synthetic reference voltage vector is obtained according to the nearest three vector principle, and the action time of each voltage vector is calculated using the volt-second balance principle; it can be seen from the two reference voltage vector formulas that a switching cycle T S The inner inverter stage 1 and the inverter stage 2 work alternately, so the sum of the duty cycles of each inverter stage is 1 / 2; thus: Among them, d1, d2, and d3 are the duty cycles of the effective vector of inverter stage 1 respectively; d1', d2', and d3' are the duty cycles of the effective vector of inverter stage 2 respectively; when the working mode 1 or the working mode 2 is used, the output voltage vector sequence meets the following principles: a virtual voltage vector is used to replace the common mode voltage with a magnitude of ±U d The basic voltage vector of / 3 ensures that only one phase changes when adjacent switch states in the output sequence switch, and there is no direct switching between state P and state N. When the reference voltage vector moves from one sector to the next, it follows the principle of minimum switching, and therefore an N-type small vector is selected as the starting vector. A symmetrical pulse sequence is used to reduce harmonics. When the reference voltage vector is located in small sector A1 (A1') or A2 (A2'), the vector involved in the synthesis involves only the basic voltage vector. The output terminal B2 is clamped at the zero level in operating mode 2. Only four switching operations occur in one switching cycle, resulting in low switching losses.

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