An RSSI cascaded operational amplifier circuit for RF transceiver chips
By designing an RSSI cascade op amp circuit for RF transceiver chips, the problem of difficulty in reducing power consumption and limited dynamic range and working linear range when detecting no input signals is solved, and the effect of large gain and stable working linear range is achieved.
Patent Information
- Application Number
- CN202211480716.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-24
- Publication Date
- 2025-03-04
- Estimated Expiration
- 2042-11-24
AI Technical Summary
The RSSI circuit in existing RF transceiver chips is difficult to effectively reduce power consumption when detecting no input signal, and the dynamic range and operating linear range of the continuous detection logarithmic amplifier are limited.
An RSSI cascaded op amp circuit for radio frequency transceiver chips is designed, including an RC filter module, a cascaded op amp module, a comparator and a rectifier. The circuit amplifies the input signal through a single-stage op amp module connected in series in N stages, and implements signal processing and indication through a comparator and rectifier.
This circuit has a large gain, expands the working linear range, and realizes a stable gain to the cascading op amp module through calibration of the digital part, and is almost unaffected by PVT.
Smart Images
Figure CN115865007B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to an RSSI cascade operational amplifier circuit for a radio frequency transceiver chip. Background Art
[0002] With the development of wireless communication, the design of circuits has higher and higher requirements for low power consumption and low cost. Therefore, the design of GPS receiver systems is also developing in the direction of low cost, high integration and low power consumption. Therefore, the design of RSSI (Received Signal Strength Indication) has received more and more attention, because they are not only an important part of the signal size control circuit, but also play a certain role in system power management.
[0003] When the RSSI circuit detects that there is no input signal in the system, it can control some modules in the system to enter the shutdown or sleep state, thereby reducing the power consumption of the system and extending the life of the system. Since the continuous detection logarithmic amplifier can represent a large dynamic range of the input signal with a small output voltage range, it is widely used in RSSI circuits. The logarithmic amplitude characteristic of the continuous detection logarithmic amplifier is obtained by the continuous addition method of the input voltage signal. This method can obtain a logarithmic characteristic curve approximated by a series of broken line segmented linearity.
[0004] The continuous detection logarithmic amplifier is composed of a cascade of multiple limiting amplifiers. The full-wave rectifier converts the output voltage of each limiting amplifier into a current. The DC voltage signal obtained by linearly superimposing the output current through a low-pass filter is used to indicate the input signal strength. Summary of the invention
[0005] The object of the present invention is to provide a RSSI cascade operational amplifier circuit for a radio frequency transceiver chip to solve the problems in the background technology.
[0006] In order to solve the above technical problems, the present invention provides an RSSI cascade operational amplifier circuit for a radio frequency transceiver chip, comprising four parts: an RC filter module, a cascade operational amplifier module, a comparator and a rectifier;
[0007] The dual input ends of the RC filter module are externally connected to the external signals Vin1 and Vin2, and the dual output ends are connected to the dual input ends of the cascade amplifier module, for taking the previous stage signal and processing it into a valid signal and transmitting it to the cascade amplifier module;
[0008] The cascade operational amplifier module is used to amplify the input signal and the working linear range of the circuit, and includes N stages of single-stage operational amplifier modules connected in series, and the dual output ends of each stage of the single-stage operational amplifier module are connected to the input end of the rectifier;
[0009] The dual output terminals of the single-stage operational amplifier module of the last stage are connected to the dual input terminals of the comparator, and the dual output terminals of the comparator are connected to the external digital signals Vout1 and Vout2.
[0010] In one embodiment, the RC filter module includes a coupling capacitor and a controllable resistor in each branch, and the two coupling capacitors are directly connected to the external signals Vin1 and Vin2 respectively; one end of the controllable resistor is connected in parallel with the dual input ends of the cascade operational amplifier module, and the other end of the controllable resistor is provided with a stable DC signal to the cascade operational amplifier module by an external circuit.
[0011] In one embodiment, the single-stage operational amplifier module includes a bias circuit, and the bias circuit includes NMOS tubes MN9 to MN16 and PMOS tubes MP19 to MP20;
[0012] The drain terminal of the NMOS tube MN9 is connected to the current I1, the gate terminal is connected to the V6 port, and the source terminal is simultaneously connected to the drain terminal and the gate terminal of the NMOS tube MN10 and the gate terminal of the NMOS tube MN11; the source terminal of the NMOS tube MN10 is connected to the drain terminal of the NMOS tube MN11; the source terminal of the NMOS tube MN11 is grounded, and the gate terminal is connected to the gate terminal of the NMOS tube MN13;
[0013] The drain end of the NMOS tube MN12 is connected to the current I2, the gate end is connected to the V7 port, and the source end is connected to the drain end of the NMOS tube MN13 and the gate end of the NMOS tube MN14 at the same time; the gate end of the NMOS tube MN13 is connected to the gate end of the NMOS tube MN15, and the source end is connected to the drain end of the NMOS tube MN14; the source end of the NMOS tube MN14 is grounded, and the gate end is connected to the gate end of the NMOS tube MN16;
[0014] The source end of the NMOS tube MN16 is grounded, the gate end is connected to the V3 port, and the drain end is connected to the source end of the NMOS tube MN15; the gate end of the NMOS tube MN15 is connected to the V2 port, and the drain end is simultaneously connected to the drain end and gate end of the PMOS tube MP20 and the gate end of the PMOS tube MP19;
[0015] The source end of the PMOS tube MP20 is connected to the drain end of the PMOS tube MP19 . The source end of the PMOS tube MP19 is connected to the power supply VDD, and the gate end is connected to the V1 port.
[0016] In one embodiment, the single-stage operational amplifier module includes a core operational amplifier circuit, and the core operational amplifier circuit includes NMOS tubes MN1 to MN8 and PMOS tubes MP1 to MP18;
[0017] The gate end of the NMOS tube MN1 is connected to the V3 port, the source end is grounded, and the drain end is connected to the source end of the NMOS tube MN2; the gate end of the NMOS tube MN2 is connected to the V2 port, and the drain end is connected to the source end of the NMOS tube MN3 and the source end of the NMOS tube MN4;
[0018] The source end of the PMOS tube MP1 and the source end of the PMOS tube MP4 are both connected to the power supply VDD, the drain end of the PMOS tube MP1 is connected to the source end of the PMOS tube MP2, and the drain end of the PMOS tube MP2 is connected to the source end of the PMOS tube MP3; the gate end of the PMOS tube MP1 and the gate end of the PMOS tube MP2 are connected to the drain end of the PMOS tube MP3;
[0019] The drain end of the PMOS tube MP4 is connected to the source end of the PMOS tube MP5, and the drain end of the PMOS tube MP5 is connected to the source end of the PMOS tube MP6; the gate end of the PMOS tube MP4 and the gate end of the PMOS tube MP5 are connected to the drain end of the PMOS tube MP6;
[0020] The source end of the PMOS tube MP7 is connected to the power supply VDD, the drain end is connected to the source end of the PMOS tube MP8, and the drain end of the PMOS tube MP8 is connected to the source end of the PMOS tube MP9; the gate end of the PMOS tube MP7 and the gate end of the PMOS tube MP8 are both connected to the drain end of the PMOS tube MP3, and the drain end of the PMOS tube MP9 is connected to the output end VOUT1;
[0021] The source end of the PMOS tube MP13 is connected to the power supply VDD, the gate end is connected to the V4 port, and the drain end is connected to the source end of the PMOS tube MP14. The gate end of the PMOS tube MP14 is connected to the source end of the PMOS tube MP15; the gate end of the PMOS tube MP15 is connected to the V4 port, and the drain end is connected to the gate end of the PMOS tube MP7; the drain end of the PMOS tube MP14 is connected to the source end of the PMOS tube MP8;
[0022] The source end of the PMOS tube MP10 is connected to the power supply VDD, the drain end is connected to the source end of the PMOS tube MP11, and the drain end of the PMOS tube MP11 is connected to the source end of the PMOS tube MP12; the gate end of the PMOS tube MP10 and the gate end of the PMOS tube MP11 are both connected to the drain end of the PMOS tube MP6, and the drain end of the PMOS tube MP12 is connected to the output end VOUT2;
[0023] The source end of the PMOS tube MP16 is connected to the power supply VDD, the gate end is connected to the V5 port, and the drain end is connected to the source end of the PMOS tube MP17. The gate end of the PMOS tube MP17 is connected to the source end of the PMOS tube MP18; the gate end of the PMOS tube MP18 is connected to the V5 port, and the drain end is connected to the gate end of the PMOS tube MP10; the drain end of the PMOS tube MP17 is connected to the source end of the PMOS tube MP11.
[0024] In one embodiment, the drain end of the NMOS tube MN3 is connected to the drain end of the PMOS tube MP3; the drain end of the NMOS tube MN4 is connected to the drain end of the PMOS tube MP6; the drain end of the NMOS tube MN5 is connected to the drain end of the PMOS tube MP9, the source end is connected to the drain end of the NMOS tube MN6, and the source end of the NMOS tube MN6 is grounded; the drain end of the NMOS tube MN7 is connected to the drain end of the PMOS tube MP12, the source end is connected to the drain end of the NMOS tube MN8, and the source end of the NMOS tube MN8 is grounded;
[0025] The NMOS transistors MN3, MN4, MN5, MN6, MN7 and MN8 are respectively connected by four identical N-type transistors to form a series feedback circuit.
[0026] In one embodiment, the current mirror formed by the branches of the PMOS tubes MP1, MP2, MP3 and the branches of the PMOS tubes MP4, MP5, MP6 is completely symmetrical with the current mirror formed by the branches of the PMOS tubes MP7, MP8, MP9 and the branches of the PMOS tubes MP10, MP11, MP12.
[0027] The RSSI cascade operational amplifier circuit for a radio frequency transceiver chip provided by the present invention has the following beneficial effects:
[0028] (1) It has a larger gain, which brings a larger working linear range;
[0029] (2) There is no self-calibration module in the cascaded op amp module. The calibration method is to pass the output of the N-stage op amp to the digital part through the comparator, and the digital part divides it into 8 bits to control the calibration of the first six stages of op amps;
[0030] (3) Using a special op amp structure makes the gain almost unaffected by PVT (including process, supply voltage, and temperature), making the total gain of the cascaded op amp module more stable. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 The present invention provides a schematic diagram of the structure of an RSSI cascade operational amplifier circuit for a radio frequency transceiver chip.
[0032] Figure 2 It is the schematic diagram of the core op amp circuit structure in a single-stage op amp module.
[0033] Figure 3 It is a structural diagram of the bias circuit in a single-stage operational amplifier module. DETAILED DESCRIPTION
[0034] The following is a further detailed description of an RSSI cascade operational amplifier circuit for a radio frequency transceiver chip proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0035] The present invention provides an RSSI cascade amplifier circuit for a radio frequency transceiver chip, comprising four parts: an RC filter module, a cascade amplifier module, a comparator and a rectifier; the cascade amplifier module comprises N-stage single-stage amplifier modules. The dual input ends of the RC filter module are externally connected to external signals Vin1 and Vin2, and the dual output ends are connected to the dual input ends of the cascade amplifier module, for taking the previous stage signal and processing it into a valid signal and transmitting it to the cascade amplifier module; the cascade amplifier module is used to amplify the input signal and the working linear range of the amplification circuit, and comprises N-stage single-stage amplifier modules connected in series, and the dual output ends of each stage of the single-stage amplifier module are connected to the input end of the rectifier; the dual output ends of the single-stage amplifier module of the last stage are connected to the dual input ends of the comparator, and the dual output ends of the comparator are connected to the external digital signals Vout1 and Vout2.
[0036] The single-stage operational amplifier module includes a core operational amplifier circuit and a bias circuit. The core operational amplifier circuit includes NMOS tubes MN1 to MN8 and PMOS tubes MP1 to MP18. The NMOS tubes MN3, MN4, MN5, MN6, MN7 and MN8 are respectively connected by four identical N-type transistors to form a series feedback circuit, which can increase the output impedance and reduce the input capacitance. Therefore, the three transistors close to the ground in each of the four series-connected transistors work in the linear region and are used as resistors Rs to realize series feedback. The loop gain is 1+g m *R s , g m is the transconductance of a single transistor; loop gain affects the transconductance g m , if R s Large, single series feedback circuit transconductance g mR will be reduced to It has nothing to do with the current, so the op amp gain will not be large. The branches of PMOS tubes MP1, MP2, and MP3 form a current mirror with the branches of PMOS tubes MP4, MP5, and MP6, and the branches of PMOS tubes MP7, MP8, and MP9 form a current mirror with the branches of PMOS tubes MP10, MP11, and MP12. The current ratio of the two current mirrors is β, and they are completely symmetrical.
[0037] In the single-stage operational amplifier module, the operational amplifier gain is related to the impedance ratio of the equivalent diodes at the input end and the output end and the current ratio of the input end and the output end. AV is the circuit gain, R out is the output resistance; therefore, the gain has nothing to do with PVT (i.e., the main factor affecting the performance of integrated circuits). The total gain of the cascaded op amp can be increased by increasing the number of single-stage op amp modules, but as the number of cascades increases, the bandwidth will decrease; but at the same time, R out increases, the output voltage will also increase and be greater than V DD As the power supply voltage, it will reduce the output swing, and as the input voltage of the next stage op amp, it will affect the DC point of the input pair of the next stage op amp.
[0038] In this embodiment, N takes a value of 11, that is, the cascaded operational amplifier module includes 11 single-stage operational amplifier modules; the DC point difference between the two output branches in the single-stage operational amplifier module can be adjusted by controlling the V4 and V5 input voltages to control the PMOS tubes MP13, MP15 and MP16, MP18, respectively, to keep the DC points of the two output ends of each stage of the operational amplifier the same.
[0039] There is no self-calibration module in the cascaded operational amplifier module. The calibration method is to transmit the output of the 11-stage operational amplifier to the digital part (not shown in the figure) through the comparator, and then the digital part uses 8 bits to control the calibration of the first six stages of operational amplifiers, that is, V4 and V5 in the single-stage operational amplifier module; the first-stage single-stage operational amplifier module is controlled by 3 bits of digital bits, and the second to sixth-stage single-stage operational amplifier modules are each controlled by 1 bit of digital bits.
[0040] The bias circuit generates a bias current that is not related to the power supply voltage VDD. The bias circuit includes NMOS tubes MN9-MN16 and PMOS tubes MP19-MP20; the source end of NMOS tube MN9 is connected to the gate end of NMOS tube MN11 and the gate end of NMOS tube MN10; the gate end of NMOS tube MN13 is connected to the gate end of NMOS tube MN15 and the NMOS tube MN2 in the single-stage operational amplifier module connected to the V2 port; the gate end of NMOS tube MM14 is connected to the source end of NMOS tube MN12, the gate end of NMOS tube MM16, and the gate end of NMOS tube MN1 in the single-stage operational amplifier module connected to the V3 port; the drain end of NMOS tube MN15 is connected to the gate end of PMOS tube MP20, the gate end of PMOS tube MP19, the gate end of PMOS tube MP3 in the single-stage operational amplifier module, the gate end of PMOS tube MP6, the gate end of PMOS tube MP9, and the gate end of PMOS tube MP12.
[0041] The NMOS transistors MN13, MN14, MN15 and MN16 in the bias circuit form a current mirror, which is suitable for working under low voltage. The source-drain voltage Vds of the NMOS transistors MN14 and MN16 is 14 With Vds 16Equal, approximately equal to 0.2V, for the threshold voltage Vth = 0.7V, the gate-source voltage Vgs is approximately equal to 0.9V, so the bias voltage V2 must be equal to about 1.1V, so that the minimum output voltage allowed is reduced from 1.1V to Vds 16 +Vds 15 =0.4V, and this structure has large output impedance and voltage swing.
[0042] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A RSSI cascade amplifier circuit for a radio frequency transceiver chip, characterized in that: It includes four parts: RC filter module, cascade amplifier module, comparator and rectifier; The dual input ends of the RC filter module are externally connected to the external signals Vin1 and Vin2, and the dual output ends are connected to the dual input ends of the cascade amplifier module, for taking the previous stage signal and processing it into a valid signal and transmitting it to the cascade amplifier module; The cascade operational amplifier module is used to amplify the input signal and the working linear range of the amplification circuit, and includes N stages of single-stage operational amplifier modules connected in series, and the dual output ends of each stage of the single-stage operational amplifier module are connected to the input end of the rectifier, and the output end of the rectifier outputs a voltage signal Vout3; The dual output terminals of the single-stage operational amplifier module of the last stage are connected to the dual input terminals of the comparator, and the dual output terminals of the comparator are connected to external digital signals Vout1 and Vout2. The digital signals Vout1 and Vout2 are used to calibrate subsequent links. The single-stage operational amplifier module includes a bias circuit, which includes NMOS tubes MN9~MN16 and PMOS tubes MP19~MP20; the single-stage operational amplifier module includes a core operational amplifier circuit, which includes NMOS tubes MN1~MN8 and PMOS tubes MP1~MP18; wherein the NMOS tubes MN3~MN8 are respectively composed of four NMOS tubes whose sources and drains are connected, and the gate ends of the four NMOS tubes in the NMOS tubes MN3, MN4, MN5, MN6, MN7, and MN8 are respectively interconnected; the gate ends of the four NMOS tubes in the NMOS tube MN3 are all connected to the VP port, and the gate ends of the four NMOS tubes in the NMOS tube MN4 are all connected to the VN port; The drain terminal of the NMOS tube MN9 is connected to the current I1, the gate terminal is connected to the V6 port, and the source terminal is simultaneously connected to the drain terminal and the gate terminal of the NMOS tube MN10 and the gate terminal of the NMOS tube MN11; the source terminal of the NMOS tube MN10 is connected to the drain terminal of the NMOS tube MN11; the source terminal of the NMOS tube MN11 is grounded, and the gate terminal is connected to the gate terminal of the NMOS tube MN13; The drain end of the NMOS tube MN12 is connected to the current I2, the gate end is connected to the V7 port, and the source end is connected to the drain end of the NMOS tube MN13 and the gate end of the NMOS tube MN14 at the same time; the gate end of the NMOS tube MN13 is connected to the gate end of the NMOS tube MN15, and the source end is connected to the drain end of the NMOS tube MN14; the source end of the NMOS tube MN14 is grounded, and the gate end is connected to the gate end of the NMOS tube MN16; wherein the current I1 and the current I2 are the currents flowing out of the bias circuit branch of the analog module in the entire chip; The source end of the NMOS tube MN16 is grounded, the gate end is connected to the gate end of the NMOS tube MN1, and the drain end is connected to the source end of the NMOS tube MN15; the gate end of the NMOS tube MN15 is connected to the gate end of the NMOS tube MN2, and the drain end is simultaneously connected to the drain end and the gate end of the PMOS tube MP20 and the gate end of the PMOS tube MP19; The source end of the PMOS tube MP20 is connected to the drain end of the PMOS tube MP19, the source end of the PMOS tube MP19 is connected to the power supply VDD, and the gate end is connected to the gate end of the PMOS tube MP3; The gate end of the NMOS tube MN1 is connected to the gate end of the NMOS tube MN16, the source end is grounded, and the drain end is connected to the source end of the NMOS tube MN2; the gate end of the NMOS tube MN2 is connected to the gate end of the NMOS tube MN15, and the drain end is connected to the source end of the terminal NMOS tube in the NMOS tube MN3 and the source end of the terminal NMOS tube in the NMOS tube MN4; the drain end of the head end NMOS tube in the NMOS tube MN3 is connected to the drain end of the PMOS tube MP3; the drain end of the head end NMOS tube in the NMOS tube MN4 is connected to the drain end of the PMOS tube MP6; the NMOS tube M The drain of the head end NMOS tube in N5 is connected to the drain of the PMOS tube MP9, the source of the terminal NMOS tube in NMOS tube MN5 is connected to the drain of the head end NMOS tube in NMOS tube MN6, and the source of the terminal NMOS tube in NMOS tube MN6 is grounded; the drain of the head end NMOS tube in NMOS tube MN7 is connected to the drain of the PMOS tube MP12, the source of the terminal NMOS tube in NMOS tube MN7 is connected to the drain of the head end NMOS tube in NMOS tube MN8, and the source of the terminal NMOS tube in NMOS tube MN8 is grounded; The gate end of the PMOS tube MP3, the gate end of the PMOS tube MP6, the gate end of the PMOS tube MP9 and the gate end of the PMOS tube MP12 are connected to the gate end of the PMOS tube MP19; the source end of the PMOS tube MP1 and the source end of the PMOS tube MP4 are connected to the power supply VDD, the drain end of the PMOS tube MP1 is connected to the source end of the PMOS tube MP2, and the drain end of the PMOS tube MP2 is connected to the source end of the PMOS tube MP3; the gate end of the PMOS tube MP1 and the gate end of the PMOS tube MP2 are connected to the drain end of the PMOS tube MP3; The drain end of the PMOS tube MP4 is connected to the source end of the PMOS tube MP5, and the drain end of the PMOS tube MP5 is connected to the source end of the PMOS tube MP6; the gate end of the PMOS tube MP4 and the gate end of the PMOS tube MP5 are connected to the drain end of the PMOS tube MP6; The source end of the PMOS tube MP7 is connected to the power supply VDD, the drain end is connected to the source end of the PMOS tube MP8, and the drain end of the PMOS tube MP8 is connected to the source end of the PMOS tube MP9; the gate end of the PMOS tube MP7 and the gate end of the PMOS tube MP8 are both connected to the drain end of the PMOS tube MP3, and the drain end of the PMOS tube MP9 is connected to the output end VOUT1; The source end of the PMOS tube MP13 is connected to the power supply VDD, the gate end is connected to the V4 port, and the drain end is connected to the source end of the PMOS tube MP14. The gate end of the PMOS tube MP14 is connected to the source end of the PMOS tube MP15; the gate end of the PMOS tube MP15 is connected to the V4 port, and the drain end is connected to the gate end of the PMOS tube MP7; the drain end of the PMOS tube MP14 is connected to the source end of the PMOS tube MP8; The source end of the PMOS tube MP10 is connected to the power supply VDD, the drain end is connected to the source end of the PMOS tube MP11, and the drain end of the PMOS tube MP11 is connected to the source end of the PMOS tube MP12; the gate end of the PMOS tube MP10 and the gate end of the PMOS tube MP11 are both connected to the drain end of the PMOS tube MP6, and the drain end of the PMOS tube MP12 is connected to the output end VOUT2; The source end of the PMOS tube MP16 is connected to the power supply VDD, the gate end is connected to the V5 port, and the drain end is connected to the source end of the PMOS tube MP17. The gate end of the PMOS tube MP17 is connected to the source end of the PMOS tube MP18; the gate end of the PMOS tube MP18 is connected to the V5 port, and the drain end is connected to the gate end of the PMOS tube MP10; the drain end of the PMOS tube MP17 is connected to the source end of the PMOS tube MP11.
2. The RSSI cascade operational amplifier circuit for a radio frequency transceiver chip as claimed in claim 1, characterized in that: The RC filter module includes a coupling capacitor and a controllable resistor in each branch, and the two coupling capacitors are directly connected to the external signals Vin1 and Vin2 respectively; one end of the controllable resistor is connected in parallel with the dual input ends of the cascade operational amplifier module, and the other end of the controllable resistor is provided with a stable DC signal to the cascade operational amplifier module by an external circuit.
3. The RSSI cascade operational amplifier circuit for a radio frequency transceiver chip as claimed in claim 1, characterized in that: The current mirror formed by the branches of the PMOS tubes MP1, MP2, MP3 and the branches of the PMOS tubes MP4, MP5, MP6 is completely symmetrical with the current mirror formed by the branches of the PMOS tubes MP7, MP8, MP9 and the branches of the PMOS tubes MP10, MP11, MP12.
Citation Information
Patent Citations
Received signal strength indicator circuit and method for correcting deviation thereof
CN103297075A