A broadband variable gain single-ended to differential low noise amplifier

Abstract

The present invention belongs to the field of radio frequency microwave integrated circuit technology, and is specifically an active single-ended to differential low noise amplifier with broadband variable gain. The low noise amplifier is composed of a common-phase branch, an anti-phase branch, and a feedback network. The common-phase branch and the anti-phase branch amplify the input signal, and the common-phase branch outputs a differential low noise amplifier. OUT+ and the inverting branch output terminal V OUT‑ A differential signal output is achieved. The amplifier of the present invention has a wide operating frequency range, can achieve single-ended to differential conversion without the need for a passive balun, and has variable gain. Because a passive balun is not required to achieve the single-ended to differential conversion function, the cost of the receiver system can be reduced and the receiver noise performance can be improved. The variable gain function of the present invention allows the receiver's RF front-end module to achieve a larger dynamic range and can be widely used in broadband RF receivers or receivers that support multiple wireless communication protocols.

Description

Technical Field

[0001] The present invention belongs to the technical field of radio frequency microwave integrated circuits, and in particular relates to a broadband variable gain single-ended to differential low noise amplifier. Background Art

[0002] A differential structure can effectively suppress common-mode interference generated on-chip by various factors. In RF receivers, since antennas are single-ended, a module circuit is required to convert single-ended signals to differential signals to facilitate differential processing in subsequent circuits. One approach to achieving this conversion is to use a passive balun external to the chip. This approach requires an additional off-chip balun, increasing system cost and degrading receiver noise performance. Alternatively, the passive balun can be integrated internally on the chip and connected to the input of a differential low-noise amplifier. However, on-chip passive baluns have higher losses than off-chip ones, further degrading receiver noise performance. While this approach reduces the need for off-chip baluns, it also increases the receiver chip area (increasing cost). Another implementation using an on-chip passive balun is to use the passive balun as a load for a single-ended low-noise amplifier (LNA), thereby achieving a single-ended-to-differential conversion function at the output of the LNA. This can somewhat reduce the degradation of receiver noise performance due to the balun's insertion loss, but at the expense of the single-ended LNA having poor power supply rejection ratio and common-mode rejection ratio. Furthermore, regardless of the application of an on-chip passive balun, the more advanced the process, the higher the cost. This is because process improvements do not reduce the size of the required transformer, but rather increase the cost per unit area. Using an on-chip active single-ended-to-differential LNA can address all of these issues. It provides low-noise amplification while also performing the single-ended-to-differential conversion function, effectively reducing receiver system cost without compromising noise performance. Summary of the Invention

[0003] The object of the present invention is to provide an active single-ended to differential low noise amplifier with a wide operating frequency range and a variable gain function.

[0004] The broadband variable gain single-ended to differential low noise amplifier provided by the present invention has a structure as shown in the attached figure. Figure 1 As shown. The structure consists of a non-inverting branch, an anti-inverting branch and a feedback network. Among them:

[0005] The inverting branch consists of transistor M N1a 、M N1b 、M N2a 、M N2b 、M P1 , DC blocking capacitor C B1 、C B2 、C B3 、C B4 、CB5 , load resistance R LO1 The circuit is connected. N1a With M N1b Parallel, M N2a With M N2b Parallel; M N1a With M N1b The source is grounded, M N2a 、M N2b As a common source common gate tube stacked on M N1a and M N1b The drain terminal, M N2a 、M N2b The drain terminal and M P1 The drain end is connected to M P1 The source end is connected to the power supply; R LO1 One end is connected to the power supply and the other end is connected to the M P1 Drain connected; M N1a 、M N1b 、M P1 The gates of the B1 、C B2 、C B3 and RF input port V IN Connected, M N2a 、M N2b The gates of the B4 、C B5 With transistor M N3a 、M N3b The drain end is connected to the inverting output port V OUT- Located in M P1 The inverting branch amplifies the input signal and inverts the input signal (gain is -1).

[0006] The non-inverting branch consists of transistor M N3a 、M N3b 、M N4a 、M N4b 、M P2 , DC blocking capacitor C B6 、C B7 、C B8 、C B9 、C B10 , load resistance R LO2 The circuit is connected. N3a With M N3b Parallel, M N4a With M N4b Parallel; M N3a With M N3b The source is grounded, M N4a 、M N4b As a common source common gate tube stacked on MN3a and M N3b The drain terminal, M N4a 、M N4b The drain terminal and M P2 The drain end is connected to M P2 The source end is connected to the power supply; R LO2 One end is connected to the power supply and the other end is connected to the M P2 Drain connected; M N3a 、M N3b 、M N4a 、M N4b 、M P2 The gates of the B6 、C B7 、C B8 、C B9 、C B10 With M N1a 、M N1b The drain end is connected to the non-inverting output port V OUT+ Located in M P2 The non-inverting branch amplifies the voltage provided by the inverting branch, ensuring that the output signal is in phase with the input RF signal. The inverting and non-inverting branches form the single-ended to differential conversion function.

[0007] The feedback network, consisting of the feedback resistor R f , feedback capacitor C f , DC blocking capacitor C B11 、C B12 , and transistor M N5 、M N6 The circuit is connected. N5 The source is grounded and the gate is connected to the DC blocking capacitor C. B11 With V OUT+ Port connected; M N6 The drain terminal is connected to the power supply, and the gate is connected to the DC blocking capacitor C B12 With V OUT- Port connected; M N5 The drain terminal and M N6 The source end is connected; the feedback resistor R f With the feedback capacitor C f Connect in series and across the RF input terminal and M N5 The single-ended to differential low-noise broadband input matching performance is provided by the open-loop amplifier (non-inverting branch + inverting branch) and the feedback network. The switch in the feedback network is disconnected in high gain mode, and R f Connect to the feedback network; the switch in the feedback network is closed in low gain mode, R f By switching in this way, better input matching performance can be achieved in both high gain and low gain modes.

[0008] The variable gain described in the present invention is achieved by turning on and off the parallel current multiplexing structure. The current multiplexing structure consists of transistors M N1a 、M N2a 、M N3a 、M N4a 、M P1 、M P2 Circuit connection composition. Among them, M N1a 、M N2a 、M P1 Belongs to the anti-phase branch, M N1a 、M N2a Respectively with M N1b 、M N2b Parallel, M P1 Source end connected to power supply, M P1 Drain terminal and M N2a Drain connected; M N3a 、M N4a 、M P2 Belongs to the same phase branch, M N3a 、M N4a Respectively with M N3b 、M N4b Parallel, M P2 Source end connected to power supply, M P2 Drain terminal and M N2a The drain terminals are connected. In high-gain mode, the current multiplexing structure is powered on, providing additional gain and reducing the overall noise figure of the low-noise amplifier. This enables switching from low-gain mode to high-gain mode. Conversely, the parallel current multiplexing structure of the in-phase and inverting branches is disabled to switch from high-gain mode to low-gain mode.

[0009] In the present invention, the inverting branch amplifies the input signal in reverse phase. OUT- Output terminal; at the same time, transistor M N1a 、M N1b The drain end of the M realizes the inversion of the input signal (gain is -1) and provides input for the non-inverting branch. N1a 、M N1b The signal at the drain end is further amplified in reverse phase to achieve in-phase amplification. OUT+ Finally, at the inverting amplifier output terminal V OUT- and the non-inverting amplifier output V OUT+ Differential signal output is achieved, that is, the single-ended to differential function is realized through active circuits.

[0010] In order to reduce the amplitude error and phase error of the differential signal, the corresponding device sizes of the in-phase branch and the anti-phase branch need to be equal, specifically: M N1a With M N3a 、M N1b With M N3b 、MN2a With M N4a 、M N2b With M N4b 、M P1 With M P2 、R LO1 With R LO2 The device parameter values ​​are equal.

[0011] The broadband, variable-gain, single-ended-to-differential low-noise amplifier of the present invention features a wide operating frequency range, can achieve single-ended-to-differential conversion without a passive balun, and has variable gain. Because this single-ended-to-differential conversion function eliminates the need for a passive balun, it can reduce receiver system costs while improving receiver noise performance. The broadband, single-ended-to-differential low-noise amplifier of the present invention, with its variable gain, enables the receiver's RF front-end module to achieve a greater dynamic range.

[0012] In the embodiment, the differential signal amplitude error and phase error achieved in the range of 0.7GHz to 2.5GHz are respectively in the range of 0.15dB to 0.44dB / -0.7° to 3.0°. In the low-gain mode, the active single-ended splitter function is realized, and the switching from the low-gain mode to the high-gain mode is achieved by connecting the in-phase branch and the anti-phase branch in parallel with the current multiplexing structure; in the high-gain mode, the noise figure achieved can be lower than 2dB. The broadband input matching is provided by the open-loop low-noise amplifier and the feedback network, and the feedback resistor R f The access and short circuit of the MOSFET make the input matching performance better in both high gain and low gain modes.

[0013] The broadband variable-gain single-ended-to-differential low-noise amplifier of the present invention can be widely used in broadband radio frequency receivers or receivers supporting multiple wireless communication protocols. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a specific circuit diagram of the broadband variable gain single-ended to differential low noise amplifier of the present invention.

[0015] Figure 2 These are the amplitude error and phase error of the differential output signal implemented in the specific embodiment of the present invention.

[0016] Figure 3 ] represents the variable gain value and the noise figure at high gain achieved in the specific embodiment of the present invention.

[0017] Figure 4 This is the input matching S11 in two gain modes implemented in the specific example of the present invention.

[0018] Figure 5It is the linearity achieved in the specific embodiment of the present invention. DETAILED DESCRIPTION

[0019] The structure and working principle of the broadband variable gain single-ended to differential low noise amplifier are further described below with reference to the accompanying drawings and embodiments.

[0020] As attached Figure 1 As shown in Figure 1, the structure mainly consists of an inverting branch, a non-inverting branch, and a feedback network. The inverting branch is a transistor M N1a 、M N1b 、M N2a 、M N2b 、M P1 , DC blocking capacitor C B1 、C B2 、C B3 、C B4 、C B5 and the load resistor R LO1 The circuit is connected. N1a With M N1b Parallel, M N2a With M N2b Parallel; M N1a With M N1b The source is grounded, M N2a 、M N2b As a common source common gate tube stacked on M N1a and M N1b The drain terminal, M N2a 、M N2b The drain terminal and M P1 The drain end is connected to M P1 The source end is connected to the power supply; R LO1 One end is connected to the power supply and the other end is connected to the M P1 Drain connected; M N1a 、M N1b 、M P1 The gates of the B1 、C B2 、C B3 Connected to the RF input port, M N2a 、M N2b The gates of the B4 、C B5 With transistor M N3a 、M N3b The drain end is connected to the inverting output port V OUT- Located in M P1 Drain terminal. The inverting branch realizes the RF input signal V IN Inverting amplifier. Input port to transistor M N1a 、M N1b The drain gain is -1. The non-inverting branch is connected to the transistor MN3a 、M N3b 、M N4a 、M N4b 、M P2 , DC blocking capacitor C B6 、C B7 、C B8 、C B9 、C B10 , load resistance R LO2 The circuit is connected. N3a With M N3b Parallel, M N4a With M N4b Parallel; M N3a With M N3b The source is grounded, M N4a 、M N4b As a common source common gate tube stacked on M N3a and M N3b The drain terminal, M N4a 、M N4b The drain terminal and M P2 The drain end is connected to M P2 The source end is connected to the power supply; R LO2 One end is connected to the power supply and the other end is connected to the M P2 Drain connected; M N3a 、M N3b 、M N4a 、M N4b 、M P2 The gates of the B6 、C B7 、C B8 、C B9 、C B10 With M N1a 、M N1b The drain end is connected to the non-inverting output port V OUT+ Located in M P2 Drain terminal. The in-phase branch connects transistor M N1a 、M N1b The drain signal is then inverted and amplified to achieve the same phase between the output and the input port. N2a 、M N2b and M N4a 、M N4b The drain terminals of the OUT- and V OUT+ Output, that is, the single-ended to differential function is realized through the active circuit.

[0021] In order to achieve equal amplitude and opposite phase of differential signal output, the size of the components of the in-phase branch and the anti-phase branch needs to be symmetrical when designing the circuit. Specifically, M N1a With M N3a、M N1b With M N3b 、M N2a With M N4a 、M N2b With M N4b 、M P1 With M P2 、R LO1 With R LO2 The device parameter values ​​are equal. Figure 2 As shown, in the range of 0.7GHz to 2.5GHz, the differential signal amplitude error and phase error achieved by the broadband single-ended to differential low noise amplifier are in the range of 0.15dB to 0.44dB / -0.7° to 3.0°, respectively, reflecting the excellent performance of the invented broadband single-ended to differential low noise amplifier in output differential signal balance.

[0022] The variable gain mode is achieved by turning on and off the parallel current multiplexing structure. The transistors included in the current multiplexing structure are M N1a 、M N2a 、M N3a 、M N4a 、M P1 、M P2 In high gain mode, the current multiplexing structure is powered on, providing additional gain and reducing the noise figure of the overall low noise amplifier. In high gain mode, the gain of the single-ended to differential low noise amplifier is A VH for:

[0023] A VH =V OUT+ -V OUT- ≈2(g mn1a +g mn1b +g mp1 )(R LO1 ||r op1 ),

[0024] Among them, g mn1a ,g mn1b ,g mp1 Transistor M N1a 、M N1b 、M P1 The transconductance value; r op1 M P1 The on-resistance of the tube. Figure 3 As shown in the figure, in the range of 0.7GHz to 2.5GHz, in high gain mode, the gain value is 24dB. In low gain mode, the current multiplexing structure is closed, and the gain of the single-ended to differential low noise amplifier is A VL for:

[0025] A VL =VOUT+ -V OUT- ≈2g mn1b R LO1 ,

[0026] As attached Figure 3 As shown, in the range of 0.7GHz to 2.5GHz, in the low gain mode, the gain value at low frequency is about 10dB.

[0027] The broadband input matching of the single-ended to differential low noise amplifier is provided by the open-loop amplifier (non-inverting branch + inverting branch) and the feedback network. The feedback network consists of the feedback resistor R f , feedback capacitor C f , DC blocking capacitor C B11 、C B12 , and transistor M N5 、M N6 The circuit is connected. N5 The source is grounded and the gate is connected to the DC blocking capacitor C. B11 With V OUT+ Port connected; M N6 The drain terminal is connected to the power supply, and the gate is connected to the DC blocking capacitor C B12 With V OUT- Port connected; M N5 The drain terminal and M N6 The source end is connected; the feedback resistor R f With the feedback capacitor C f Connect in series and across the RF input terminal and M N5 Drain terminal. In high gain mode, the switch in the feedback network is disconnected, Rf is connected to the feedback network, and the input impedance of the broadband, single-ended to differential low noise amplifier is R IN for:

[0028]

[0029] Among them, g mn6 is transistor M N6 In low gain mode, the switch in the feedback network is closed, and the input impedance of the single-ended to differential low noise amplifier is R IN for:

[0030]

[0031] As attached Figure 4 As shown, in the range of 0.7GHz to 2.5GHz, the input matching S11 is lower than -10dB in both high gain mode and low gain mode.

[0032] Noise figure is one of the most important indicators of a single-ended to differential low noise amplifier. Figure 3As shown in the figure, under the power consumption of 19mW, the noise figure of the broadband variable gain single-ended to differential low noise amplifier of the invention is about 2dB. Figure 5 As shown, the input third-order intercept point of the invented broadband variable gain single-ended to differential low noise amplifier is -1.4dBm to 1.3dBm in the range of 0.3GHz to 3GHz; the second-order intercept point is 12.4dBm to 15.5dBm in the range of 0.3GHz to 3GHz.

Claims

1. A broadband variable gain single-ended to differential low noise amplifier circuit, characterized in that: It consists of an anti-phase branch, a non-phase branch, and a feedback network; among which: The inverting branch consists of five transistors M N1a 、M N1b 、M N2a 、M N2b 、M P1 , five DC blocking capacitors C B1 、C B2 、C B3 、C B4 、C B5 , load resistance R LO1 Circuit connection structure; wherein, transistor M N1a With transistor M N1b Parallel, transistor M N2a With transistor M N2b Parallel connection; transistor M N1a With transistor M N1b The source terminal is grounded, and the transistor M N2a , transistor M N2b As a cascode transistor stacked on transistor M N1a and transistor M N1b The drain terminal of transistor M N2a , transistor M N2b The drain terminal of transistor M P1 The drain terminal of transistor M is connected to P1 The source end is connected to the power supply; the load resistor R LO1 One end is connected to the power supply, and the other end is connected to the transistor M P1 The drain terminal is connected to the transistor M N1a , transistor M N1b , transistor M P1 The gates of the B1 、C B2 、C B3 and RF input port V IN connected, transistor M N2a , transistor M N2b The gates of the B4 、C B5 With transistor M N3a , transistor M N3b The drain end is connected to the inverting output port V OUT- Located in transistor M P1 Drain terminal; the inverting branch realizes the inverting amplification of the input signal on the one hand; on the other hand, it realizes the inversion of the input signal with a gain of -1; The non-inverting branch consists of five transistors M N3a 、M N3b 、M N4a 、M N4b 、M P2 , five DC blocking capacitors C B6 、C B7 、C B8 、C B9 、C B10 , load resistance R LO2 Circuit connection structure; wherein, transistor M N3a With transistor M N3b Parallel, transistor M N4a With transistor M N4b Parallel connection; transistor M N3a With transistor M N3b The source terminal is grounded, and the transistor M N4a , transistor M N4b As a cascode transistor stacked on transistor M N3a and transistor M N3b The drain terminal of transistor M N4a , transistor M N4b The drain terminal of transistor M P2 The drain terminal of transistor M is connected to P2 The source end is connected to the power supply; R LO2 One end is connected to the power supply, and the other end is connected to the transistor M P2 The drain terminal is connected to the transistor M N3a 、M N3b 、M N4a 、M N4b 、M P2 The gates of the B6 、C B7 、C B8 、C B9 、C B10 With transistor M N1a , transistor M N1b The drain end is connected to the non-inverting output port V OUT+ Located in transistor M P2 Drain terminal; the in-phase branch amplifies the voltage provided by the inverting branch in reverse phase, so that the output signal is in phase with the input RF signal; the inverting branch and the in-phase branch constitute the single-ended to differential function; The feedback network, consisting of the feedback resistor R f , feedback capacitor C f , two DC blocking capacitors C B11 、C B12 , and two transistors M N5 、M N6 Circuit connection structure; wherein, transistor M N5 The source is grounded and the gate is connected to the DC blocking capacitor C. B11 With V OUT+ Port connected; transistor M N6 The drain terminal is connected to the power supply, and the gate is connected to the DC blocking capacitor C B12 With V OUT- Port connected; transistor M N5 The drain terminal of transistor M N6 The source end is connected; the feedback resistor R f With the feedback capacitor C f connected in series and across the RF input terminal and transistor M N5 Drain end; the single-ended to differential low-noise broadband input matching performance is achieved by the open-loop amplifier and feedback network consisting of the in-phase branch and the anti-phase branch.

2. The broadband variable gain single-ended to differential low noise amplifier circuit according to claim 1, characterized in that: The switches in the feedback network are disconnected in high gain mode, R f Connect to the feedback network; the switch in the feedback network is closed in low gain mode, R f Short circuit; switching in this way enables good input matching performance in high gain and low gain modes.

3. The broadband variable gain single-ended to differential low noise amplifier circuit according to claim 1, characterized in that: The variable gain is achieved by turning on and off the parallel current multiplexing structure; the current multiplexing structure is composed of transistors M N1a 、M N2a 、M N3a 、M N4a 、M P1 、M P2 Circuit connection structure; wherein, transistor M N1a 、M N2a 、M P1 Belongs to the inverting branch, transistor M N1a 、M N2a Respectively with transistor M N1b 、M N2b Parallel, transistor M P1 The source terminal is connected to the power supply, transistor M P1 The drain terminal and transistor M N2a The drain terminal is connected to the transistor M N3a 、M N4a 、M P2 Belongs to the in-phase branch, transistor M N3a 、M N4a Respectively with transistor M N3b 、M N4b Parallel, transistor M P2 The source terminal is connected to the power supply, transistor M P2 The drain terminal and transistor M N2a The drain terminals are connected; in high-gain mode, the current multiplexing structure is powered on to provide additional gain, reduce the noise figure of the overall low-noise amplifier, and realize switching from low-gain mode to high-gain mode; conversely, the parallel current multiplexing structure of the in-phase branch and the inverting branch is turned off to realize switching from high-gain mode to low-gain mode.

4. The broadband variable gain single-ended to differential low noise amplifier circuit according to claim 1, wherein: The inverting branch amplifies the input signal in an inverted manner. OUT- Output terminal; at the same time, transistor M N1a , transistor M N1b The drain end of the input signal is inverted, the gain is -1, and it provides input for the in-phase branch; The non-inverting branch connects the inverting branch to the transistor M N1a , transistor M N1b The signal at the drain end is further amplified in reverse phase to achieve in-phase amplification. OUT+ Output at the inverting amplifier output terminal V OUT- and the non-inverting amplifier output V OUT+ Realize differential signal output, that is, realize the single-ended to differential function through active circuit.

5. The broadband variable gain single-ended to differential low noise amplifier circuit according to claim 1, wherein: The corresponding device sizes of the in-phase branch and the inverting branch are equal, specifically: transistor M N1a With transistor M N3a , transistor M N1b With transistor M N3b , transistor M N2a With transistor M N4a , transistor M N2b With transistor M N4b , transistor M P1 With transistor M P2 , load resistance R LO1 With the load resistor R LO2 The device parameter values ​​are equal.

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