A PCIe switching circuit pass-through mode control method

Abstract

The present invention discloses a method for controlling a pass-through mode of a PCIe switching circuit, and belongs to the field of integrated circuit design. The present invention sets an input-end switching control register and an output-end switching control register for each port inside the PCIe switching circuit, and controls the switching modes of the input port and the output port in sections, so that the user can perform differentiated switching control on the transaction packets entering or outputting from different ports of the PCIe switching circuit, thereby improving the flexibility of the application of the PCIe switching circuit and thus improving the overall switching performance of the system. The present invention enables the switching transactions entering from the same input port to adopt different switching modes for different output ports by setting the output-end switching control registers of different output ports differently; in addition, the switching transactions inputted from different ports and outputted from the same port can adopt different switching modes by setting the input-end switching control registers of different input ports differently.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit design, and in particular to a PCIe exchange circuit pass-through mode control method. Background Art

[0002] As the third generation high-performance IO bus, PCIe bus is widely used in computer systems. In a PCIe system, PCIe switching circuit is used to interconnect multiple electronic components or modules. PCIe switching circuit generally has two or more PCIe ports, and the link width and rate of each port can be the same or different.

[0003] The PCIe protocol defines three logical layers: the physical layer, the data link layer, and the transaction layer. The transaction layer packets are exchanged between different ports of the switching circuit as the highest logical layer data. The transaction packets exchanged by the PCIe switching circuit include two types of transaction packets with data words and transaction packets without data words. The transaction packets with data words are further divided into memory write request transaction packets and message request transaction packets. The length of the data word ranges from 4 bytes to 4096 bytes.

[0004] Common switching methods include direct switching and store-and-forward. Direct switching does not require the entire data packet to be received before the data entering the input port is output from the output port, which has the advantage of low switching delay, but has the disadvantage of excessive link bandwidth occupation due to data retransmission after an error occurs in the tail data; store-and-forward switching is to receive and store the entire data packet before outputting it from the output port, which has a large switching delay, especially for large data packets and cascaded multi-stage switching circuits. It will produce unacceptable delays, but has the advantage of not occupying the output link bandwidth due to retransmission after an error occurs in the tail data.

[0005] All ports and input and output directions of existing PCIe switching circuits that support both pass-through and store-and-forward switching modes can only work in one of the pass-through or store-and-forward modes. In actual applications, they cannot meet users' differentiated control requirements for different ports, affecting the flexibility of the application and further affecting the switching performance of the entire system. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a method for controlling a pass-through mode of a PCIe switching circuit.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A method for controlling a pass-through mode of a PCIe switching circuit, wherein an input-end switching control register and an output-end switching control register are set for each port in the PCIe switching circuit;

[0009] The values ​​of the input-end switching control register and the output-end switching control register of the port respectively represent a data length;

[0010] The switching mode of the data word transaction packet on the switching line formed by the input port and the output port is controlled by segmentation; the input port input end switching control register controls the direct mode of the data word transaction packet on the switching line, and the output port output end switching control register controls the direct mode of the data word transaction packet on the switching line.

[0011] On a switching link within a PCIe switching circuit, for a transaction packet with data words of a given length, when both the input port input switching control register and the output port output switching control register enable the pass-through mode, the switching line is a pass-through switch; and when either the input port input switching control register or the output port output switching control register does not enable the pass-through mode, the storage and forwarding mode is used for switching.

[0012] Furthermore, after a power-on reset, the input-end switching control register and the output-end switching control register of each port can be configured and modified by a configuration EEPROM connected to the outside of the circuit.

[0013] Furthermore, during the operation of the PCIe switch circuit, the input switch control register and the output switch control register of each port can be modified by a memory write transaction sent by a root complex device connected to the upstream port of the PCIe switch circuit.

[0014] Further, the specific operations are:

[0015] According to the requirements of different ports of the PCIe switching circuit, the addresses and modified values ​​of the input switching control register and / or the output switching control register of non-default values ​​are burned into the EEPROM device outside the switching circuit;

[0016] After power-on reset, the input switching control register and / or the output switching control register of the port using the non-default value is configured and changed by a configuration EEPROM connected externally to the circuit;

[0017] After the system is enumerated, if the port in the PCIe switching circuit fails to establish a link of a preset rate or width, the root complex device is used to modify the input switching control register and / or the output switching control register of the corresponding port of the PCIe switching circuit in a memory write transaction;

[0018] During the operation of the PCIe switching circuit, the PCIe transaction packets between different ports are exchanged according to the control of the input-end switching control register and the output-end switching control register of each port.

[0019] Furthermore, the specific operation of controlling the exchange of PCIe transaction packets between different ports is as follows:

[0020] (1) For exchange transaction packets without data words, the store-and-forward mode is used for exchange. The transaction packets received by the input port are exchanged to the output port after it is determined that there is no error. The transaction packets with errors at the input port are not exchanged to the output port.

[0021] (2) For a transaction packet with a data word, when the data length of the transaction packet received by the input port is greater than the data length indicated by the input switching control register of the port, the port adopts the pass-through mode as an input port; when the data length of the received transaction packet is less than or equal to the data length indicated by the input switching control register of the port, the port adopts the store-and-forward mode as an input port;

[0022] (3) For a transaction packet with a data word, when the data length of the transaction packet received by the output port is greater than the data length indicated by the output switching control register of the port, the port adopts the pass-through mode as an output port; when the data length of the transaction packet received by the port is less than or equal to the data length indicated by the output switching control register of the port, the port adopts the store-and-forward mode as an output port.

[0023] Furthermore, during the operation of the PCIe switching circuit, the root complex device is used to change the input switching control register and the output switching control register of each port through a memory write transaction, thereby changing the switching mode of PCIe transaction packets of different lengths.

[0024] Further, for a switching transaction packet with a given length and a data word and in which an error occurs, when the input port input switching control register does not enable the through mode, the switching of the transaction packet is terminated at the input end.

[0025] Furthermore, when the output port output exchange control register does not enable the through mode, if the transaction packet with data word error has been exchanged to the output end, the exchange will be terminated at the output end.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The PCIe switching circuit pass-through mode control method of the present invention sets an input switching control register and an output switching control register for each port inside the PCIe switching circuit, and controls the switching mode of the input port and the output port in sections, so that the user can perform differentiated switching control on the transaction packets entering or outputting from different ports of the PCIe switching circuit, thereby improving the flexibility of the application of the PCIe switching circuit and thus improving the overall switching performance of the system. The present invention enables the switching transaction entering from the same input port to adopt different switching modes for different output ports by setting the output switching control registers of different output ports differently; and enables the switching transaction entering from different ports and outputting from the same port to adopt different switching modes by setting the input switching control registers of different input ports differently; in addition, on the switching line formed by the same input and output ports, transaction packets with data words of different lengths can adopt different switching modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 The figure is a simplified schematic diagram of a PCIe switching circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] The present invention is further described in detail below in conjunction with the accompanying drawings:

[0032] See also Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a PCIe switching circuit according to an embodiment of the present invention. Figure 1 As shown, the PCIe switching circuit of this embodiment has four ports, all of which are ports with a rate of 5.0 Gbps and a link width of 4. The four ports have the same internal principle. For clarity and readability, only a brief schematic diagram of the internal structure of port 0 is drawn in the figure; each of the four ports of the circuit of this embodiment is provided with an input switching control register INCCREG and an output switching control register EGRCCREG; the maximum data load supported by this embodiment is 256 DW, so the input switching control register INCCREG and the output switching control register EGRCCREG are both set to registers with a bit width of 9 bits, and their values ​​represent the data length in double words (DW), and the data length range that can be represented is 0DW~511DW;

[0033] After the circuit is powered on, under the control of the internal reset module of the circuit, the INCCREG registers of all ports are reset to the default value of all 0, indicating that all input ports enable the direct switching mode, and the EGRCCREG registers of all ports are reset to the default value of all 0, indicating that all output ports enable the direct switching mode;

[0034] After power-on reset, the input switching control register and the output switching control register of each port can be configured and modified by the configuration EEPROM connected to the outside of the circuit, and the configuration value of the EEPROM is loaded into the INCCREG register and / or the EGRCCREG register through the EEPROM loading and register access module inside the circuit;

[0035] During the operation of the PCIe switching circuit, the input switching control register and the output switching control register of each port can be modified by the memory write transaction sent by the root complex device connected to the upstream port of the PCIe switching circuit. The memory write transaction sent by the root complex is sent by the upstream port 0 to the EEPROM loading and register access module, and then the EEPROM loading and register access module updates the corresponding INCCREG register and / or EGRCCREG register; for clarity and readability, the connection between the EEPROM loading and register access module and the registers in each port in the figure is only indicated by text;

[0036] The values ​​of the input switch control register and the output switch control register of the same port configured by the external configuration EEPROM or the root complex device can be different;

[0037] The values ​​of the input switching control register or the output switching control register of different ports configured by the external configuration EEPROM or the root complex device can be different;

[0038] In this embodiment, the input switching control register of each port interacts with the input switching module of the port, and the input switching module controls whether the switching transaction packet with data words entering from the port enables the direct mode by the input switching control register; when the direct mode is enabled, if there are no other transactions cached in the input switching module, the input switching module starts to exchange the transaction packet to the output port through the interconnection bus without waiting for the entire transaction packet to be received; when the direct mode is enabled, if there are other transactions cached in the input switching module, the input switching module receives and caches the current transaction packet; when the direct mode is not enabled, the input switching module receives and stores the complete transaction packet and then exchanges the cached transaction packet to the output port through the interconnection bus;

[0039] In this embodiment, the outgoing switching control register of each port interacts with the outgoing switching module of the port, and the outgoing switching module selects the routing mode of the switching transaction packet with data words entering from the port under the control of the outgoing switching control register; when the direct mode is enabled, if there are no other transactions cached in the outgoing switching module, the outgoing switching module starts to send the transaction packet to the sending interface of the port without waiting to receive the entire transaction packet from the interconnection bus; when the direct mode is not enabled, the outgoing switching module starts to send the transaction packet to the sending interface of the port only after receiving the complete transaction packet from the interconnection bus;

[0040] For a switching line in a circuit, for a transaction packet with data words of a given length, the entire switching line is a direct switching only when both the input port input switching control register and the output port output switching control register enable the direct switching mode; when any one of the input port input switching control register or the output port output switching control register does not enable the direct switching mode, the transaction packet with data words of the given length is switched in the store-and-forward mode;

[0041] Further, for a transaction packet with a data word error of a certain length, when the input port input end switching control register does not enable the direct mode, the transaction packet terminates the switching at the input end switching module of the input port; when the output port output end switching control register does not enable the direct mode, if the transaction packet with the data word error has been switched to the output end, the switching will be terminated at the output end switching module of the output port;

[0042] The PCIe switching system architecture of the embodiment of the present invention; in this embodiment, two Figure 1The four-port PCIe switching circuit shown is cascaded to realize the interconnection between the CPU (central processing unit with root complex function) unit and five PCIe endpoint devices; in this embodiment, data needs to be exchanged between many PCIe endpoint devices and the CPU. In the entire system, link 0, that is, the link between port 0 of PCIe switching circuit 0 and the CPU has the highest communication load in the system, and it is necessary to reduce the bandwidth of link 0 occupied by the data transmitted from many endpoint devices to the CPU when it may be erroneously retransmitted;

[0043] The PCIe switching circuit endpoint 1 of this embodiment is a device that mainly transmits data back to the CPU. The transaction packet length of the large amount of data transmitted back is less than 64DW and is not sensitive to the delay time. The occasional emergency transaction packet with a length of 128DW needs to be transmitted back to the CPU with a shorter delay time. In order to reduce the occupation of the link bandwidth of the link 0 flowing to the CPU when the transaction packet with a length of 64DW transmitted back to the CPU by endpoint 1 is retransmitted due to an error, and at the same time ensure that the occasional emergency transaction packet with a length of 128DW is transmitted back to the CPU with the minimum delay time, the default value 0 is used for the output switching control register of port 0 of the PCIe switching circuit 1, and the input switching control register of port 1 of the PCIe switching circuit 1 is set to 127 through the EEPROM;

[0044] In this way, when a transaction packet with a data length less than or equal to 127DW enters port 1 of PCIe switching circuit 1 from endpoint 1, the transaction packet will be exchanged to port 0 in store-and-forward mode after being completely received by port 1, and port 0 will exchange the transaction packet to CPU in direct mode; for transaction packets with a data length less than or equal to 127DW, this control method of only using direct mode exchange at the outbound port makes it possible for the transaction packet with a length less than or equal to 127DW transmitted back from endpoint 1 to the CPU to terminate exchange at input port port 1 when an error occurs, and retransmission only occurs on link 1, and will not occupy the bandwidth of link 0 for retransmission; and when no error occurs in the transaction packet, it can be quickly exchanged to CPU in direct mode at outbound port 0, thereby taking into account both the system exchange delay and the bandwidth of high-load link 0 occupied by the retransmission of the error transaction packet, thereby improving the performance of the system;

[0045] When an occasional emergency transaction packet larger than 128DW enters port 1 of PCIe switching circuit 1 from endpoint 1, port 1 switches it to port 0 in direct mode, and port 0 also switches the transaction packet to the CPU in direct mode at the output end. The direct mode is used in the entire switching line from port 1 to port 0, ensuring that the emergency transaction packet reaches the CPU with the minimum delay time.

[0046] In this embodiment, the data of the CPU and endpoint 2, endpoint 3, and endpoint 4 need to pass through port 2 of the switching circuit 1. In order to reduce the large delay caused by the two-stage switching, the input switching control register and the output switching control register of port 2 of the PCIe switching circuit 1 use the default value 0; under this configuration, the CPU and the transactions exchanged via the PCIe switching circuit 2 are exchanged in the direct mode in the PCIe switching circuit 1 in both directions of entering the PCIe switching circuit 1 and entering the PCIe switching circuit 2, which effectively reduces the exchange delay of the transaction packets via the two-stage switching circuits;

[0047] The operation process of the PCIe switching circuit 1 switching method of the PCIe switching system of the embodiment of the present invention is described as follows:

[0048] Step S310, burning the address and modification value 127 of the input switching control register of port 1 into the external EEPROM device;

[0049] Step S320, after power-on reset, the value of the input switching control register of port 1 is changed to 127 by the configuration EEPROM connected externally to the circuit;

[0050] Step S330, after the system is enumerated, the CPU checks the link status registers of each port of the PCIe switching circuit. If a port fails to establish the expected 5.0 Gbps rate or link width of 4, the CPU adjusts the input switching control register of the corresponding port to the maximum value of 511 by means of a memory write transaction, so that all transaction packets with data words entering from the port with a lower bandwidth adopt the store-and-forward mode at the input port, so as to avoid the exchange data of the low-bandwidth input port occupying the interconnection bus and other resources in the PCIe switching circuit for a long time;

[0051] Step S340: During operation, the PCIe switching circuit exchanges PCIe transaction packets between different ports according to the control of the input-end switching control register and the output-end switching control register of each port, as follows:

[0052] 1) For exchange transaction packets without data words, the store-and-forward mode is used for exchange. The transaction packets received by the inlet port are exchanged to the output port after it is determined that there is no error. The transaction packets with errors at the inlet port are not exchanged to the output port.

[0053] 2) For transaction packets with data words, when the data length of the transaction packet received by a port as an input port from the opposite device of the PCIe link is greater than the data length indicated by the input-end switching control register of the port, the port as an input port adopts the pass-through mode and starts to exchange transactions to the output end without completing the reception of the entire transaction packet; when the data length of the transaction packet received from the opposite device of the PCIe link is less than or equal to the data length indicated by the input-end switching control register of the port, the port as an input port adopts the store-and-forward mode and starts to exchange transactions to the output port after completing the reception of the entire transaction packet;

[0054] 3) For transaction packets with data words, when the data length of the transaction packet received by a port as an output port from an input port in the PCIe switching circuit is greater than the data length indicated by the output switching control register EGRCCREG of the port, the port as an output port adopts the pass-through mode and starts to transmit the transaction to the opposite device without completing the reception of the entire transaction packet from the input port; when the data length of the transaction packet received by the port is less than or equal to the data length indicated by the output switching control register EGRCCREG of the port, the port as an output port adopts the store-and-forward mode and starts to transmit the transaction to the opposite device after completing the reception of the entire transaction packet from the input port;

[0055] The operation process of the switching method of the PCIe switching circuit 2 of the PCIe switching system of the embodiment of the present invention will not be described in detail.

[0056] The switching method of the present invention has great flexibility. For a switching line that requires a smaller switching delay but has a larger average transaction packet length, the corresponding input port control register of the PCIe switching circuit can be set to 0, and the corresponding output port output controller can be set to 0, so that the transaction packets with data words on this switching line in the switching switch all adopt the direct-through mode, thereby giving full play to the advantage of the short switching delay of the direct-through mode and reducing the switching delay; for a switching line that is only sensitive to the switching delay of individual occasional extra-long transaction packets, the input port control register or the output port output controller can be set, so that the extra-long transaction packets adopt direct-through switching to reduce the switching delay, and the transaction packets of normal length adopt the storage and forwarding mode to reduce the average switching delay of the switching line, avoid the error retransmission at the tail of the transaction packet occupying the link bandwidth of the output port, and improve the performance of the entire switching system.

[0057] The above contents are only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A method for controlling a pass-through mode of a PCIe switching circuit, characterized in that: An input-end switching control register and an output-end switching control register are set for each port inside the PCIe switching circuit; the values ​​of the input-end switching control register and the output-end switching control register of the port both represent a data length; The switching mode of the data word transaction packet on the switching line formed by the input port and the output port is controlled by segmentation; the input port input end switching control register controls the direct mode of the data word transaction packet on the switching line, and the output port output end switching control register controls the direct mode of the data word transaction packet on the switching line. On a switching line in a PCIe switching circuit, for a transaction packet with a data word, when both the input port input-end switching control register and the output port output-end switching control register enable the direct-through mode, the switching line adopts the direct-through switching mode for switching; and when either the input port input-end switching control register or the output port output-end switching control register does not enable the direct-through mode, the storage-and-forwarding mode for switching is adopted; During operation of the PCIe switch circuit, the input switch control register and the output switch control register of each port can be modified by a memory write transaction sent by a root complex device connected to an upstream port of the PCIe switch circuit; According to the requirements of different ports of the PCIe switching circuit, the addresses and modified values ​​of the input switching control register and / or the output switching control register of non-default values ​​are burned into the EEPROM device outside the switching circuit; After power-on reset, the input switching control register and / or the output switching control register of the port using the non-default value is configured and changed by a configuration EEPROM connected externally to the circuit; After the system is enumerated, if the port in the PCIe switching circuit fails to establish a link of a preset rate or width, the root complex device is used to modify the input switching control register and / or the output switching control register of the corresponding port of the PCIe switching circuit in a memory write transaction; During the operation of the PCIe switching circuit, the PCIe transaction packets between different ports are exchanged according to the control of the input switching control register and the output switching control register of each port; The specific operations for controlling the exchange of PCIe transaction packets between different ports are: (1) For exchange transaction packets without data words, the store-and-forward mode is used for exchange. The transaction packets received by the input port are exchanged to the output port after it is determined that there is no error. The transaction packets with errors at the input port are not exchanged to the output port. (2) For a transaction packet with a data word, when the data length of the transaction packet received by the input port is greater than the data length indicated by the input switching control register of the port, the port adopts the pass-through mode as an input port; when the data length of the received transaction packet is less than or equal to the data length indicated by the input switching control register of the port, the port adopts the store-and-forward mode as an input port; (3) For a transaction packet with a data word, when the data length of the transaction packet received by the output port is greater than the data length indicated by the output switching control register of the port, the port adopts the pass-through mode as an output port; when the data length of the transaction packet received by the port is less than or equal to the data length indicated by the output switching control register of the port, the port adopts the store-and-forward mode as an output port; After power-on reset, the input switching control register and output switching control register of each port can be configured and changed by the configuration EEPROM connected outside the circuit; During the operation of the PCIe switching circuit, the root complex device is used to change the input switching control register and the output switching control register of each port through a memory write transaction, thereby changing the switching mode of PCIe transaction packets of different lengths.

2. The PCIe switching circuit pass-through mode control method according to claim 1, characterized in that: For a switching transaction packet with a given length and a data word and an error, when the input port input switching control register does not enable the pass-through mode, the transaction packet terminates the switching at the input end.

3. The PCIe switching circuit pass-through mode control method according to claim 2, characterized in that: When the output port output exchange control register does not enable the through mode, if the transaction packet with data word error has been exchanged to the output end, the exchange will be terminated at the output end.

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