A clock data recovery method for long-distance industrial optical fiber communication

Abstract

The present invention relates to a clock data recovery method for long-distance industrial optical fiber communication. By adopting 6 times the clock for oversampling, the serial data jump edge is judged and aggregated under the same clock, and the sampling clock is dynamically selected. According to the level jitter tolerance, the validity of the sampled data under different conditions is confirmed. After data processing, the data sampled by multiple clocks is restored to serial data under the local clock, and finally the serial data is converted into parallel data. In the process of clock data recovery, the present invention can avoid the influence of level "jitter" caused by crystal oscillator error, inter-symbol interference, baseline drift and the like, and the accuracy of clock data recovery is high; at the same time, the present invention is more suitable for the site of long-distance industrial optical fiber communication, and the communication has strong anti-interference ability and extremely low bit error rate. The experimental results show that the application effect is good.

Description

Technical Field

[0001] The invention belongs to the technical field of industrial communication, and in particular to a clock data recovery method for long-distance industrial optical fiber communication. Background Art

[0002] The on-site application environment of industrial equipment is usually very harsh, and electrical communication signals are easily interfered with. Fiber-optic communication is widely used in industrial equipment due to its high real-time performance, high accuracy, and strong anti-interference ability. The performance of fiber-optic communication directly affects whether the entire control system can work properly. In fiber-optic communication, the transmitter encodes the data into a self-synchronous data stream, and combines the data and clock into a single signal for transmission; the receiver needs to accurately separate the data and clock from the single signal.

[0003] Usually, electronic components have parameter differences. Taking a 40MHz active crystal oscillator as an example, its error is ±20ppm (ppm, one part per million), which means that its actual crystal oscillator frequency is between 39.9992MHz and 40.0008MHz. The sampling frequency deviation at the communication receiving end will affect the sampled data, resulting in an increase in the signal-to-noise ratio of the transmission system and deterioration in performance.

[0004] In the optical fiber transmission system, the signal receiving end needs to recover the initial valid clock from the data signal containing noise and transmission distortion in order to correctly obtain the data signal. This technology is called clock data recovery technology. For the clock data recovery at the receiving end, the most important non-ideal factor is caused by the non-ideal characteristics of the channel and line code. The non-ideal characteristics mainly include the inherent noise of the transmitter, inter-symbol interference, baseline drift, etc. In long-distance industrial optical fiber transmission, the problems caused by such non-ideal factors are particularly obvious, which makes it difficult to correctly decode the optical fiber signal.

[0005] Affected by factors such as crystal oscillator error, inter-symbol interference, and baseline drift, it is technically difficult for the receiving end of optical fiber communication to correctly separate data and clock from a single signal. Summary of the invention

[0006] The purpose of the present invention is to overcome the shortcomings of the prior art and to propose a clock data recovery method for long-distance industrial optical fiber communication, which can avoid the influence of jitter on clock data recovery, has high accuracy, low cost, and good effect in industrial field application.

[0007] The present invention solves the technical problem by adopting the following technical solutions:

[0008] A clock data recovery method for long-distance industrial optical fiber communication comprises the following steps:

[0009] Step 1, generate 6 times clock;

[0010] Step 2: Use 6 times the clock to sample the signal at the optical fiber receiving end;

[0011] Step 3, processing the multi-clock sampling signal;

[0012] Step 4, performing jitter processing on the multi-clock sampling signal processed in step 3;

[0013] Step 5: Recover clock data according to the signals obtained in step 3 and step 4.

[0014] Moreover, the specific implementation method of step 1 is: input the active crystal oscillator as the clock source into the FPGA, and the FPGA internal phase-locked loop PLL generates three clocks CLK, CLK60 and CLK120 with a phase difference of 60° according to the clock source, and then these three clocks are inverted to obtain CLK180, CLK240 and CLK300 respectively.

[0015] Moreover, the specific implementation method of step 2 is: using 6 times the clock to respectively capture the DIN signal transition edge of the external optical fiber receiving end of the same data signal input to the FPGA.

[0016] Moreover, the process of capturing the signal transition edge is:

[0017] Set the DIN signal to pass through the D flip-flop with clocks CLK, CLK, CLK, CLK in sequence, and define the output signal A(0);

[0018] The DIN signal passes through the D flip-flop with clocks CLK60, CLK, CLK, CLK, and the output signal is defined as B(0);

[0019] The DIN signal passes through the D flip-flops with clocks CLK120, CLK60, CLK, CLK, and CLK in sequence, and the output signal is defined as C(0);

[0020] The DIN signal passes through the D flip-flops with clocks CLK180, CLK120, CLK60, CLK, and CLK in sequence, and the output signal is defined as D(0);

[0021] The DIN signal passes through the D flip-flops with clocks CLK240, CLK180, CLK120, CLK60, and CLK in sequence, and the output signal is defined as E(0);

[0022] The DIN signal passes through the D flip-flops with clocks CLK300, CLK240, CLK180, CLK120, and CLK60 in sequence, and the output signal is defined as F(0).

[0023] Moreover, the specific implementation method of step 3 is as follows: the collected signal X(0) (X=A, B, C, D, E, F) in step 2 is passed through a D flip-flop whose clock is CLK to output a signal X(1), and the collected signal X(0) and the output signal X(1) are subjected to XOR and AND logic to generate signals Xp and Xn, wherein Xp=1 represents a rising edge transition of X(0), and Xn=1 represents a falling edge transition;

[0024] Select the CLK clock cycle as the sampling cycle, and generate the flag caseX according to the relationship between the generated signals Xp and Xn in different detection clocks and judgment conditions;

[0025] The flag caseX passes through a first-level D flip-flop to obtain caseXX (X = A, B, C, D, E, F), where caseX is the cache of the previous sampling cycle of caseXX;

[0026] Set each recovered bit stream to dataX (X = A, B, C, D, E, F), and the serial data recovered by the oversampling clock data to DATA. When caseXX = 1, the single-channel recovered data dataX = X(1); otherwise dataX = 0, and DATA is the result of the OR operation of all dataX (X = A, B, C, D, E, F).

[0027] Moreover, the specific implementation method of step 4 is: set the flag bit DV to indicate the validity of the data, when the data needs to be discarded, DV=0, when the data needs to be resampled, DV=1, when the jitter processing is performed, set each recovered bit stream to dataX' (X=A, B, C, D, E, F), and the serial data recovered by the oversampling clock data is DATA';

[0028] When caseFF=1 and caseA=1, the jitter tolerance is 1 / 6 bit width or caseEE=1 and caseA=1, the jitter tolerance is 1 / 3 bit width, dataA'=A(1); otherwise dataA'=0; caseFF is obtained by caseF through a first-level D flip-flop, caseAA is obtained by caseA through a first-level D flip-flop, and caseEE is obtained by caseE through a first-level D flip-flop;

[0029] When caseFF=1 and caseB=1, the jitter tolerance is 1 / 3 bit width, dataB'=B(1); otherwise dataB'=0;

[0030] When caseAA=1 and caseE=1, the jitter tolerance is 1 / 3 bit width, dataE'=E(1); otherwise dataE'=0;

[0031] When caseAA=1 and caseF=1, the jitter tolerance is 1 / 6 bit width or caseBB=1 and caseF=1, the jitter tolerance is 1 / 3 bit width, dataF'=F(1); otherwise dataF'=0, caseBB is obtained by caseB through a first-level D flip-flop;

[0032] When there is no jitter tolerance satisfying caseCC=1 or caseDD=1, dataC'=0, dataD'=0;

[0033] Among them, DATA' is the result of OR operation of all dataX' (X=A,B,C,D,E,F)).

[0034] Moreover, the specific implementation method of step 5 is: setting the flag bit DJ, DJ=1 when discarding or supplementing the signal, otherwise DJ=0, enabling signals DJ and DV, sending the recovered serial data DATA in step 3 and the recovered serial data DATA' in step 4 into the cache FIFO, the cache FIFO outputs according to the relationship between sampling processing, jitter processing and the flag bit, and the signal DATA_RX output by the cache FIFO is the recovered data, where DATA_RX is serial data.

[0035] Moreover, the relationship between the step sampling process, the dithering process and the flag bit is:

[0036] DJ=0,DV=0 or 1,DATA is valid, DATA' is invalid

[0037] DJ=1,DV=0,DATA is invalid, DATA' is invalid

[0038] DJ=1, DV=1, DATA is valid, DATA' is valid.

[0039] The advantages and positive effects of the present invention are:

[0040] 1. The present invention uses 6 times the clock for oversampling, determines the serial data jump edge and aggregates it under the same clock, and dynamically selects the sampling clock. According to the level jitter tolerance, the validity of the sampled data under different conditions is confirmed. After data processing, the data sampled by multiple clocks is restored to serial data under the local clock, and finally the serial data is converted into parallel data. In the process of clock data recovery, the present invention can avoid the influence of level "jitter" caused by crystal oscillator error, inter-symbol interference, baseline drift, etc., and the accuracy of clock data recovery is high.

[0041] 2. Since the physical layer of optical fiber communication is integrated inside the FPGA, the carrying capacity is strong, the flexibility is high and the cost is low, the processing process of the present invention is all implemented in the FPGA.

[0042] 3. The present invention avoids the influence of level "jitter" caused by crystal oscillator error, inter-symbol interference, baseline drift, etc., and is therefore more suitable for sites using long-distance industrial optical fiber communications. It has strong anti-interference capability and extremely low bit error rate. Experimental results show that the application effect is good. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 Structural diagram of optical fiber communication board;

[0044] Figure 2 This is a schematic diagram of multi-clock sampling and signal processing of the present invention;

[0045] Figure 3 This is a schematic diagram of signal edge jump processing of the present invention;

[0046] Figure 4 Schematic diagram of signal jitter and sampling points at the optical fiber receiving end of the present invention

[0047] Figure 5 Schematic diagram of enabling and serial data processing of the present invention

[0048] Figure 6 It is the simulation result diagram of the software of the present invention;

[0049] Figure 7 This is a waveform diagram actually measured at the receiving end of long-distance industrial optical fiber communication of the present invention. DETAILED DESCRIPTION

[0050] The present invention is further described in detail below with reference to the accompanying drawings.

[0051] Figure 1 The on-board structure of optical fiber communication is given, which includes three parts: active crystal oscillator, FPGA chip and optical fiber transceiver. Among them, the active crystal oscillator provides the basic clock for FPGA; the optical fiber transceiver uses two wires, one for receiving and one for transmitting, to connect with FPGA to reduce the use of pins and enhance the chip's load capacity; the optical fiber transceiver uses a dedicated transceiver connector with a specific rate, which is directly connected to the optical fiber line.

[0052] Optical fiber communication is mainly implemented by FPGA. In the protocol model implemented by FPGA, the application layer provides user data for system acquisition, control, and communication with MCU; the protocol layer is used to define the data frame structure and implement functions such as transmission control, protocol processing, and diagnosis; the physical layer belongs to the underlying structure and implements functions such as encoding / decoding, scrambling / descrambling, and clock data recovery.

[0053] In the physical layer, the transmitter converts parallel data into serial data through encoding (such as 4B / 5B encoding, MLT-3 encoding, etc.) and scrambling (such as adding physical layer frame headers, idle codes, etc.). The receiver first recovers the data from a single signal through clock data recovery; then, after descrambling and decoding operations, the serial data is converted into parallel data for use by the protocol layer and application layer. In the optical fiber transmission system, the signal receiving end recovers the valid clock and correct data from the signal containing noise and transmission distortion, which is called clock data recovery. Clock data recovery must be able to avoid the influence of factors such as crystal oscillator error, inter-symbol interference, baseline drift, etc. to ensure the accuracy of the data.

[0054] Clock data recovery is mainly based on two types of technologies: (1) phase-locked loop technology; (2) oversampling technology. The higher the sampling frequency of oversampling technology, the higher the accuracy of data recovery. However, higher clock frequencies pose certain challenges to FPGA layout and routing.

[0055] Based on the above description, the present invention proposes a clock data recovery method for long-distance industrial optical fiber communication, comprising the following steps:

[0056] Step 1: Generate a 6-fold clock.

[0057] Generally, the higher the multiple of clock oversampling, the better the data recovery effect, but the higher the multiple of oversampling, the more FPGA logic resources are required, and the difficulty of layout and routing is also increased. Taking comprehensive considerations, the present invention adopts clock data recovery with 6 times clock oversampling.

[0058] The specific implementation method of this step is: input the active crystal oscillator as the clock source into the FPGA, and the internal phase-locked loop PLL of the FPGA generates three clocks CLK, CLK60 and CLK120 with a phase difference of 60° according to the clock source, and then inverts these three clocks to obtain CLK180, CLK240 and CLK300. Clock data recovery is achieved by judging the rising / falling edge of the bit stream by different clocks. If CLK is 100MHz, the actual effective sampling clock is 600MHz.

[0059] Step 2: Use the 6-fold clock to sample the signal at the optical fiber receiving end.

[0060] like Figure 2 As shown, the signal input from the external optical fiber receiving end to the FPGA is DIN, where the DIN signal is a serial bit stream input. Use 6 times the clock to capture the DIN signal transition edge of the same data signal input from the external optical fiber receiving end to the FPGA. Due to the phase difference, the 6 clocks will capture the DIN transition edge in sequence. Due to the characteristics of the FPGA chip device, the sampled signal needs to run under the same clock.

[0061] To ensure that the DIN signal can be captured by the local clock and avoid duplication or missed capture, the following methods are adopted:

[0062] The DIN signal passes through the D flip-flop with clocks CLK, CLK, CLK, CLK in sequence, and the output signal is defined as A(0);

[0063] The DIN signal passes through the D flip-flop with clocks CLK60, CLK, CLK, CLK, and the output signal is defined as B(0);

[0064] The DIN signal passes through the D flip-flops with clocks CLK120, CLK60, CLK, CLK, and CLK in sequence, and the output signal is defined as C(0);

[0065] The DIN signal passes through the D flip-flops with clocks CLK180, CLK120, CLK60, CLK, and CLK in sequence, and the output signal is defined as D(0);

[0066] The DIN signal passes through the D flip-flops with clocks CLK240, CLK180, CLK120, CLK60, and CLK in sequence, and the output signal is defined as E(0);

[0067] The DIN signal passes through the D flip-flops with clocks CLK300, CLK240, CLK180, CLK120, and CLK60 in sequence, and the output signal is defined as F(0).

[0068] Step 3: Process the multi-clock sampling signal.

[0069] The collected signal X(0) (X = A, B, C, D, E, F) in step 2 is passed through a D flip-flop with a clock of CLK to output the signal X(1). The collected signal X(0) and the output signal X(1) are passed through a D flip-flop with a clock of CLK to generate the output signal X(1). Figure 3 The XOR and AND logics shown generate signals Xp and Xn, where Xp=1 represents a rising edge transition of X(0), and Xn=1 represents a falling edge transition.

[0070] The minimum width of the optical fiber communication signal is one bit width. Usually, when the clock detects a signal edge jump, the data midpoint is the ideal sampling point, and the signal collected at the ideal sampling point is stable and accurate.

[0071] Define the CLK time period as the sampling period, and generate 6 cases as shown in Table 1. Define the flag caseX (X = A, B, C, D, E, F), when the judgment conditions in the table are met, the corresponding caseX = 1, otherwise caseX = 0. For example, CLK300 detects the rising edge of the data, indicating that the previous sampling period Fp = 1, the current sampling period Ap = Bp = Cp = Dp = Ep = 1, only considering the judgment conditions of this period, the sampling clock selects CLK120 to obtain ideal data, at this time caseB = 1, caseA = caseC = caseD = caseE = caseF = 0.

[0072] Table 1 Sampling signal determination and processing

[0073]

[0074] Select the CLK time period as the sampling period, and generate a flag caseX according to the relationship between the generated signals Xp and Xn in different detection clocks and judgment conditions; pass the flag caseX through a first-level D flip-flop to obtain caseXX (X=A, B, C, D, E, F), where caseX is the cache of the previous sampling period of caseXX.

[0075] Assume that each channel of recovered bit stream is dataX (X = A, B, C, D, E, F), and the serial data recovered by oversampling clock data is DATA. When caseXX = 1, the single channel recovered data is dataX = X (1); otherwise, dataX = 0. Since only one caseXX = 1 each time, DATA is the result of the "OR" operation of all dataX (X = A, B, C, D, E, F).

[0076] Step 4: performing jitter processing on the multi-clock sampling signal processed in step 3.

[0077] In actual applications, the crystal oscillator will produce errors within the allowable range. The DIN signal is sent according to the clock of the transmitter, and the local clock of the receiver may be faster or slower. In long-distance optical fiber communication, non-ideal factors will also cause the high-level width of the optical fiber to increase. Both of these points will cause "jitter" before and after the level jump edge of the input FPGA, such as Figure 4 As shown in Figure 1, edge jitter can cause the ideal sampling point to change.

[0078] Due to crystal oscillator errors, the clocks at the optical fiber transmitter and receiver will deviate. When the local clock is fast, the receiver needs to periodically discard the signal; when the local clock is slow, the receiver needs to periodically resample the signal. Define the flag DJ, when discarding or resampling the signal, DJ = 1, otherwise DJ = 0. There are mainly three situations:

[0079] When the sending and receiving clocks are consistent, caseX = caseXX = 1 and remains unchanged, which is an ideal situation;

[0080] When the local clock is fast (with a short period), data will be repeatedly collected. When the local clock is fast, the sampling clock will become an adjacent clock, and the signal will be set to 1 in the alphabetical order of "caseAA=1→caseBB=1→……→caseFF=1". Taking the CLK clock period as the sampling period, when caseFF=1 and caseA=1, the data is repeatedly collected and needs to be discarded.

[0081] When the local clock is slow (long period), the receiving end should avoid data leakage. When the local clock is slow, the sampling clock will become the adjacent clock, and the signal will be set to 1 in reverse order of "caseFF=1→caseEE=1→...→caseAA=1". Taking the CLK clock period as the sampling period, when caseAA=1 and caseF=1, the data needs to be supplemented.

[0082] In the above case, the jitter caused by the crystal oscillator error is less than 1 / 6 of the bit width. Taking 100Mbps as an example, the allowable jitter error is 1 / 6*10ns=1.65ns.

[0083] During long-distance transmission, due to the existence of non-ideal factors such as inter-symbol interference and baseline drift, the jitter problem at the optical fiber receiving end is more obvious. The proportion of optical fiber high level will increase, resulting in an increase in jitter. Especially in 100Mbps optical fiber communication, the jitter tolerance is usually around 2ns.

[0084] The jitter amount increases, so that caseX and caseXX are not limited to the adjacent sampling clock situation (such as "caseF→caseAA"). It may occur to cross the sampling clock situation similar to "caseF→caseBB". Taking the CLK clock period as the sampling period, considering the case of only crossing one sampling clock, the jitter tolerance is extended to 1 / 3 of the bit width. At this time, the allowable jitter error is 1 / 3*10ns=3.3ns.

[0085] Taking into account the crystal oscillator error and non-ideal factors, the determination and processing methods are shown in Table 2. The flag bit DV is defined to indicate the validity of the data. When the data needs to be discarded, DV = 0; when the data needs to be resampled, DV = 1.

[0086] Table 2 Special signal determination and processing

[0087]

[0088] When jitter processing is performed, set each recovered bit stream to dataX' (X = A, B, C, D, E, F), and the serial data recovered from the oversampling clock data to DATA'. Process dataX' as follows:

[0089] When the judgment conditions of the above case 1 or case 4 are met, dataA'=A(1); otherwise, dataA'=0.

[0090] When the judgment condition of the above situation 3 is met, dataB'=B(1); otherwise, dataB'=0.

[0091] When the judgment condition of the above case 6 is met, dataE'=E(1); otherwise, dataE'=0.

[0092] When the judgment conditions of the above case 2 or case 5 are met, dataF'=F(1); otherwise, dataF'=0.

[0093] Since there is no case where the jitter tolerance satisfies caseCC=1 or caseDD=1, dataC′=0 and dataD′=0.

[0094] Among them, DATA' is the result of the "OR" operation of all dataX' (X=A, B, C, D, E, F).

[0095] Step 5: Recover clock data according to the signals obtained in step 3 and step 4.

[0096] like Figure 5 As shown, enable signals DJ and DV, send the recovered serial data DATA in step 3 and the recovered serial data DATA' in step 4 into the cache FIFO, and the cache FIFO outputs according to the relationship among sampling processing, jitter processing and flag bits as shown in Table 3. The signal DATA_RX output by the cache FIFO is the recovered data, wherein DATA_RX is serial data.

[0097] Table 3 Enable and serial data correspondence

[0098] DJ DV DATA DATA' 0 0 / 1 efficient invalid 1 0 invalid invalid 1 1 efficient efficient

[0099] The physical layer of optical fiber communication uses 4B / 5B encoding. The transmitter will send an idle code when there is no data to send, and the communication frame header uses non-coded numbers. The receiver can determine the beginning of the communication frame based on the idle code and frame header of DATA_RX, and thus recover the 5B code in the serial data; then, through descrambling and decoding, the optical fiber communication data is output to the protocol layer and application layer for subsequent work.

[0100] The software simulation results are as follows Figure 6As shown, the simulation example is the clock data recovery case when the local clock CLK is fast. The signal changes in the manner of caseEE=1→caseFF=1→caseAA=1, satisfying case 1 of Table 2, at which time DJ=1, DV=0. The recovered serial data DATA, DATA' are always output. DJ, DV, DATA, DATA' are processed by the cache FIFO and the serial signal DATA_RX is output. DATA_RX is then processed to obtain the 5B code, i.e. the parallel data 5B_data, and its valid flag 5B_en. It can be seen from the simulation results that this method can correctly realize the clock data recovery with good effect.

[0101] According to the clock data recovery method for long-distance industrial optical fiber communication, a test environment is built. A dual-core 650nm wavelength plastic optical fiber line is used for testing to observe the jitter at the optical fiber receiving end. Figure 7 It can be seen that the level jitter time is about 2ns.

[0102] Test the effect of optical fiber communication. Calculate the physical layer clock data recovery error, and the number of errors in 10 billion communications is 0. The clock data recovery method for long-distance industrial optical fiber communication proposed in the present invention has high accuracy, strong chip loading capacity, high flexibility and low cost, and has good effect in industrial field application.

[0103] It should be emphasized that the embodiments described in the present invention are illustrative rather than restrictive. Therefore, the present invention includes but is not limited to the embodiments described in the specific implementation manner. Any other implementation manners derived by those skilled in the art based on the technical solution of the present invention also fall within the scope of protection of the present invention.

Claims

1. A clock data recovery method for long-distance industrial optical fiber communication, characterized in that: The following steps are involved: Step 1, generate 6 times clock; Step 2: Use 6 times the clock to sample the signal at the optical fiber receiving end; Step 3, processing the multi-clock sampling signal; The specific implementation method of step 3 is as follows: the collected signal X(0) in step 2 is passed through a D flip-flop whose clock is CLK to output a signal X(1), and the collected signal X(0) and the output signal X(1) are subjected to XOR and AND logic to generate signals Xp and Xn, wherein Xp=1 represents a rising edge transition of X(0), and Xn=1 represents a falling edge transition, wherein X represents the output signal A, B, C, D, E or F; Select the CLK clock cycle as the sampling cycle, and generate the flag caseX according to the relationship between the generated signals Xp and Xn in different detection clocks and judgment conditions; The flag caseX is passed through a first-level D flip-flop to obtain caseXX, where caseX is the cache of the previous sampling cycle of caseXX; Set each channel of recovered bit stream to dataX, and the serial data recovered by the oversampling clock data to DATA. When caseXX=1, the single channel recovered data dataX=X(1); otherwise dataX=0, and DATA is the result of the OR operation of all dataX. Step 4, performing jitter processing on the multi-clock sampling signal processed in step 3; The specific implementation method of step 4 is: set the flag bit DV to indicate the validity of the data, when the data needs to be discarded, DV=0, when the data needs to be resampled, DV=1, when jitter processing, set each channel of recovered bit stream to dataX', and the serial data recovered by the oversampling clock data to DATA'; When caseFF=1 and caseA=1, the jitter tolerance is 1 / 6 bit width or caseEE=1 and caseA=1, the jitter tolerance is 1 / 3 bit width, dataA'=A(1); otherwise dataA'=0, where caseFF is obtained by caseF after a first-level D flip-flop, caseAA is obtained by caseA after a first-level D flip-flop, and caseEE is obtained by caseE after a first-level D flip-flop; When caseFF=1 and caseB=1, the jitter tolerance is 1 / 3 bit width, dataB'=B(1); otherwise dataB'=0; When caseAA=1 and caseE=1, the jitter tolerance is 1 / 3 bit width, dataE'=E(1); otherwise dataE'=0; When caseAA=1 and caseF=1, the jitter tolerance is 1 / 6 bit width or caseBB=1 and caseF=1, the jitter tolerance is 1 / 3 bit width, dataF'=F(1); otherwise dataF'=0, where caseBB is obtained by caseB after a first-level D flip-flop; When there is no jitter tolerance in caseCC and caseDD, dataC'=0, dataD'=0; Wherein, DATA' is the result of OR operation of all dataX'(X=A,B,C,D,E,F); Step 5: Recover clock data according to the signals obtained in step 3 and step 4.

2. The clock data recovery method for long-distance industrial optical fiber communication according to claim 1, characterized in that: The specific implementation method of step 1 is: input the active crystal oscillator as the clock source into the FPGA, and the FPGA internal phase-locked loop PLL generates three clocks CLK, CLK60 and CLK120 with a phase difference of 60° according to the clock source, and then inverts these three clocks to obtain CLK180, CLK240 and CLK300 respectively.

3. The clock data recovery method for long-distance industrial optical fiber communication according to claim 1, characterized in that: The specific implementation method of step 2 is: using 6 times the clock to respectively capture the DIN signal transition edges of the external optical fiber receiving end of the same data signal input to the FPGA.

4. The clock data recovery method for long-distance industrial optical fiber communication according to claim 3, characterized in that: The process of capturing the DIN signal transition edge of the same data signal input to the FPGA from the external optical fiber receiving end is as follows: Set the DIN signal to pass through the D flip-flop with clocks CLK, CLK, CLK, CLK in sequence, and define the output signal A(0); The DIN signal passes through the D flip-flop with clocks CLK60, CLK, CLK, CLK, and the output signal is defined as B(0); The DIN signal passes through the D flip-flops with clocks CLK120, CLK60, CLK, CLK, and CLK in sequence, and the output signal is defined as C(0); The DIN signal passes through the D flip-flops with clocks CLK180, CLK120, CLK60, CLK, and CLK in sequence, and the output signal is defined as D(0); The DIN signal passes through the D flip-flops with clocks CLK240, CLK180, CLK120, CLK60, and CLK in sequence, and the output signal is defined as E(0); The DIN signal passes through the D flip-flops with clocks CLK300, CLK240, CLK180, CLK120, and CLK60 in sequence, and the output signal is defined as F(0).

5. The clock data recovery method for long-distance industrial optical fiber communication according to claim 1, characterized in that: The specific implementation method of step 5 is: set the flag bit DJ, when the signal is discarded or supplemented, DJ=1, otherwise DJ=0, enable signals DJ and DV, send the recovered serial data DATA in step 3 and the recovered serial data DATA' in step 4 into the cache FIFO, the cache FIFO outputs according to the relationship between sampling processing, jitter processing and the flag bit, and the signal DATA_RX output by the cache FIFO is the recovered data DATA_RX, where DATA_RX is serial data.

6. The clock data recovery method for long-distance industrial optical fiber communication according to claim 5, characterized in that: The relationship between the sampling process, the dithering process and the flag bit is: DJ=0,DV=0 or 1, and DJ has high priority, DATA is valid, DATA' is invalid DJ=1,DV=0,DATA is invalid, DATA' is invalid DJ=1, DV=1, DATA is valid, DATA' is valid.

Images