Solid-state imaging device

Abstract

One embodiment provides a solid-state imaging device capable of ensuring a signal flat period of signal output and achieving high speed. The solid-state imaging device of the embodiment includes a plurality of pixels, a plurality of sampling switches, a plurality of sample-and-hold circuits, and a plurality of output switches. The plurality of pixels are arranged in at least a column direction. The plurality of sampling switches sample signals output from the pixels belonging to the column in parallel. The plurality of sample-and-hold circuits sample and hold the signals output from the plurality of sampling switches. The plurality of output switches output the signals held by the plurality of sample-and-hold circuits at predetermined timings.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-153592 (filed on September 21, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to solid-state imaging devices. Background Technology

[0003] In solid-state imaging devices, a method is sometimes employed where, during analog-to-digital (AD) conversion, a sample-and-hold technique is used to temporarily sample the output signal from the pixels. When implementing this sample-and-hold, sampling noise in the final signal output depends on the sampling period. To address this, processing is required in external digital circuitry such as integrated circuits (ICs). Furthermore, a certain sampling period is needed to ensure the charging and discharging time of the sample-and-hold, which becomes an obstacle to high-speed operation. Ensuring the charging and discharging period of this sampling while requiring the signal flatness required for digital processing becomes a challenge when increasing the overall system speed. Summary of the Invention

[0004] One embodiment provides a solid-state imaging device that can ensure signal flatness during signal output and achieve high speed.

[0005] According to one embodiment, a solid-state imaging device includes a plurality of pixels, a plurality of sampling switches, a plurality of sample-and-hold circuits, and a plurality of output switches. The plurality of pixels are arranged at least in a column direction. The plurality of sampling switches sample signals output from the pixels belonging to the columns in parallel. The plurality of sample-and-hold circuits sample and hold the signals output from the plurality of sampling switches. The plurality of output switches output the signals stored by the plurality of sample-and-hold circuits at predetermined timings. Attached Figure Description

[0006] Figure 1 This is a block diagram schematically illustrating a solid-state imaging device according to one embodiment.

[0007] Figure 2 This is a diagram that schematically illustrates an example of the structure of a pixel involved in one implementation.

[0008] Figure 3 This is a diagram schematically illustrating an example of the structure of an output circuit involved in one implementation.

[0009] Figure 4 This is a diagram schematically illustrating an example of the structure of an output circuit involved in one implementation.

[0010] Figure 5 yes Figure 4 The timing diagram of the circuit.

[0011] Figure 6 This is a diagram schematically illustrating an example of the structure of an output circuit involved in one implementation.

[0012] Figure 7 yes Figure 7 The timing diagram of the circuit.

[0013] Figure 8 This is a diagram illustrating an example of the structure of an inverter according to one implementation method.

[0014] Figure 9 This is a diagram illustrating an example of the structure of a source follower involved in one implementation.

[0015] Figure 10 This is a diagram schematically illustrating an example of the structure of an output circuit involved in one implementation.

[0016] Figure 11 This is a diagram illustrating an example of the structure of an inverter according to one implementation method. Detailed Implementation

[0017] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, in circuit diagrams, power supply voltages are sometimes not shown, but the required power supply voltage is appropriately applied to the constituent elements. For example, in a source follower, an appropriate power supply voltage is applied to the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and the resistor connected to the MOSFET.

[0018] (First Embodiment)

[0019] Figure 1 This is a schematic block diagram illustrating a solid-state imaging apparatus according to one embodiment. The solid-state imaging apparatus 1 includes a pixel array 10, a control circuit 12, a row scanning circuit 14, a column scanning circuit 16, and an output circuit 18. Furthermore, the solid-state imaging apparatus 1 may, as needed, include a storage circuit (not shown), an image processing circuit, a display unit, various input / output interfaces, and other circuits, modules, devices, etc.

[0020] The pixel array 10 constitutes the light-receiving part in the solid-state imaging device 1. The plurality of pixels 100 are configured, for example, in a two-dimensional array, and the pixel array 10 is constituted by the plurality of pixels 100 configured in an array.

[0021] The control circuit 12 executes the control of various circuits, modules, etc. in the solid-state imaging device 1. The control circuit 12 is configured, for example, with a suitable processor.

[0022] The row scanning circuit 14 outputs a signal that specifies the row of pixels 100 in the pixel array 10, and outputs a signal appropriately from the pixels 100 belonging to the predetermined row based on the signal.

[0023] The column scanning circuit 16 outputs signals that specify the columns of pixels 100 in the pixel array 10. Output signals from pixels 100 belonging to the rows specified by the row scanning circuit 14 are output to the output circuit 18 for each column belonging to the columns specified by the column scanning circuit 16.

[0024] The output circuit 18 includes signal processing circuitry for each row, which appropriately processes the analog signals output from the pixels 100 and outputs them appropriately for each row specified by the row scanning circuit 14. That is, for pixels 100 belonging to one or more rows selected by the row scanning circuit 14, signal processing is performed column-wise, and then the signal for the pixels 100 along the row is output as a row signal. When the row scanning circuit 14 selects multiple rows at the same timing, the signals belonging to multiple rows are processed in parallel. Each signal processing circuit in the output circuit 18 includes, for example, an amplifier that appropriately amplifies the output from the pixels 100. In this disclosure, by controlling the sample-and-hold function in the amplifier, noise reduction and processing speed improvement in the solid-state imaging device 1 are achieved.

[0025] The signal output from output circuit 18 is appropriately processed by an image processing circuit (not shown) or the like, and then output or stored in a storage circuit or the like. For example, output circuit 18 may also output an analog line signal, which is converted into a digital signal by an ADC (Analog to Digital Converter) connected to the next stage, and digital signal processing such as image processing is performed. Furthermore, output circuit 18 may also include an ADC, in which case it may output a line signal that has been converted from an analog signal output from pixel 100 into a digital signal via the ADC.

[0026] Figure 2 This is a diagram illustrating an example of the structure of pixel 100. Pixel 100 includes a light-receiving element (PD) and pixel circuitry.

[0027] The light-receiving element (PD) is, for example, a photodiode. The anode of the PD is grounded, and current is output from the cathode based on the intensity of the received light. The PD can also be an APD (Avalanche Photodiode), a SPAD (Single Photon Avalanche Diode), etc. In the case of these diodes, the anode may not be grounded, but rather a suitable negative voltage may be applied. The received light can be, for example, visible light, infrared light, or light with other wavelengths.

[0028] The pixel circuit is a circuit that outputs the analog signal from the light-receiving element PD at appropriate timing, and is provided in each pixel 100, i.e., relative to each light-receiving element PD. As another example, it may be structured such that multiple pixels 100, i.e., relative to multiple light-receiving elements PD, have a common charge detection section. As an example, the pixel circuit includes transistors M1, M2, M3 and source follower 102, but is not limited to this structure; even other structures can be connected to the output circuit of this disclosure.

[0029] Transistor M1 is a transistor that transmits the signal output from the photodetector PD to the charge detection unit FJ. The signal output from the photodetector PD is output to the charge detection unit FJ via transistor M1 at a timing based on the voltage Vsh applied to the gate.

[0030] Transistor M2 is used to reset the charge detection unit FJ. After reading the signal from the charge detection unit FJ, transistor M2 resets the potential of the charge detection unit FJ to a potential based on the power supply voltage Vdd, based on the timing of the voltage Vrs applied to the gate. By resetting the charge detection unit FJ, the signal received by the light-receiving element PD during the subsequent light-receiving timing can be properly detected.

[0031] The source follower 102 is used as a buffer for the signal in the charge detection unit FJ. The source follower 102 is not a necessary structure; it can be omitted depending on the structure of the pixel 100, or it can be other structures.

[0032] Transistor M3 operates as a shift register. At appropriate timing based on voltage Vsr, transistor M3 outputs an analog signal based on the intensity of light received by the photodetector PD.

[0033] Pixel 100 outputs an analog signal from transistor M3, and inputs this analog signal to output circuit 18 at a timing controlled by column scan circuit 16. That is, column scan circuit 16 applies a signal Vsr to each pixel 100 to control the timing of transistor M3 being turned on (ON).

[0034] Figure 3 This is a diagram illustrating an example of the structure of the output circuit 18. During timing controlled by the row scanning circuit 14 and the column scanning circuit 16, the analog signal output from pixel 100 is input to the output circuit 18. The output circuit 18 has multiple output circuits 20A, 20B, ... arranged row by row.

[0035] Output circuit 20 is a circuit that samples and holds the analog signal output from pixel 100 and then outputs it. By sampling and holding, the signal output from pixel 100 is appropriately amplified and output at an appropriate timing.

[0036] The signals output from each output circuit 20A, 20B, ... are output as digital row signals at the timing of the output rows controlled by the row scanning circuit 14. Furthermore, although not shown, in order to properly serialize the outputs from the output circuit 18 for each column, a buffer or similar device may be appropriately provided in the subsequent stage of the output circuit 18. Additionally, since the signals to be output are serial signals for each row, a row buffer or similar device may be appropriately provided. As another example, the buffer may also be installed inside the output circuit described later. For example, the following... Figure 4 The source follower 214 can also act as a line cache.

[0037] In addition, Figure 3 The present invention includes output circuits 20A, 20B, ... within the output circuit 18, but is not limited to this. For example, a circuit such as a regulator or amplifier that appropriately controls current, voltage, etc., may be provided between the pixel array 10 and the output circuit 18. On the other hand, output circuits 20A, 20B, ... may be configured instead of such regulators or amplifiers, or they may be provided as circuits that appropriately amplify and stabilize the signals for horizontal output. That is, the structure in this disclosure is shown as an example, and the circuit structure can be appropriately modified within the scope of achieving the same operation.

[0038] Figure 4 This is a circuit diagram schematically illustrating an example of an output circuit according to one embodiment. The output circuit 20 includes: an inverter 200; bias circuits 202 and 206; source followers 204, 210, and 214; a sampling switch 208; and an output switch 212. Additionally, as shown, other capacitors, switches, etc., may be appropriately included.

[0039] Outputs from pixels 100 belonging to the same row are input to an output circuit 20. This signal is transmitted via wires arranged row by row. Furthermore, it is not necessary to have output circuits 20 in a one-to-one correspondence across all rows; instead, one output circuit 20 may be provided for each plurality of rows with different timings. As another example, pixels 100 in each row may be connected to multiple output circuits 20, or the control circuit 12 or the row scanning circuit 14 may appropriately switch which output circuit 20 a row is connected to.

[0040] Inverter 200 inverts the analog signal output from pixel 100 for output. The inversion of the signal from which the bias voltage is applied by the bias circuit 202 is performed by an appropriate timing switch.

[0041] The source follower 204 is connected to the inverter 200 and functions as a buffer to control the impedance of the signal inverted by the inverter 200 and to output it. Additionally, the source follower 204 can also have its gain adjusted to function as an amplifier.

[0042] The sampling switch 208 is connected to the source follower 204 and operates to distribute the signal AMP output by the source follower 204 to any one of the parallel-connected source followers 210 for sampling. For example... Figure 4 As shown, the output circuit 20 includes a first sampling switch 208A and a second sampling switch 208B. These two sampling switches 208 are controlled in a manner where the ON timing is exclusive.

[0043] The source follower 210 operates as a sample-and-hold circuit. When the signal output from the source follower 204 is distributed to two paths via the first sampling switch 208A and the second sampling switch 208B, a first sample-and-hold circuit 210A and a second sample-and-hold circuit 210B, composed of two source followers 210 connected in parallel, are provided. The first sample-and-hold circuit 210A is connected to the first sampling switch 208A, and the second sample-and-hold circuit 210B is connected to the second sampling switch 208B. Each source follower 210 is configured with circuit elements to operate as a sample-and-hold circuit.

[0044] Output switch 212 is a switch that connects multiple source followers 210 to the output terminals of output circuit 20 at appropriate timing, and selects the output from the source follower 210, which is a suitable sample-and-hold circuit. Similarly to the source follower 210, when the signal AMP is distributed to two paths, it includes a first output switch 212A that controls the output from the first sample-and-hold circuit 210A and a second output switch 212B that controls the output from the second sample-and-hold circuit 210B. That is, the first output switch 212A is connected to the first sample-and-hold circuit 210A, and the second output switch 212B is connected to the second sample-and-hold circuit 210B.

[0045] Each sampling switch 208 and each output switch 212, for example, is an nMOS, and is switched between on / off states based on the voltage applied to the gate.

[0046] The source follower 214 is a circuit that acts as a buffer, outputting the sample-and-hold circuit output via multiple output switches 212. Through the source follower 214, the output circuit 20 outputs the final signal OS.

[0047] Figure 5 This is a timing diagram of multiple pixels 100 and output circuit 20. Vrs is the reset timing in pixel 100. When Vrs becomes High, the potential of charge detection unit FJ is reset. After Vrs is controlled to Low, the input signal SF of output circuit 20 changes according to the intensity of light input to photodetector PD via shift register.

[0048] At an appropriate timing, the bias circuit is connected to the signal transmission path, and a bias voltage is applied. After the voltages at each node are reset by the bias circuit, the signal AMP, which is the output of the source follower 204, changes based on the input signal SF.

[0049] The signal AMP is transmitted to either source follower 210 based on the action of the sampling switch 208. For example, when Vsp1 becomes High, the first sampling switch 208A becomes on, and in the first sample-and-hold circuit 210A, the signal AMP begins sampling and holding, and the timing potential of Vsp1 becoming Low is held in the first sample-and-hold circuit 210A. This transition is caused by... Figure 5 The transformation of BF1 in the model is represented.

[0050] The signal BF1 held in the first sample-and-hold circuit 210A is output at a timing when Vsel1 becomes High and the first output switch 212A is turned on, and is output to the ADC 22 via the source follower 214. During the period when Vsel1 is High, the signal BF1 is included in the hold period (signal flat period) of the sample-and-hold operation, thus enabling the output signal to be output in a state that avoids noise until it becomes a hold signal. That is, the first sample-and-hold circuit 210A does not include the signal during the transition of BF1 based on AMP, so that it is output at a timing when the signal BF1 is flat after the transition. As a result, when the timing of the AD conversion in the ADC 22 is when the signal OS is stable at a predetermined value, the generation of noise caused by the sample-and-hold operation in the AD conversion can be eliminated.

[0051] During the sampling and holding of BF1, processing of the input signal from the next pixel 100 is performed. For the signal from the next pixel 100, the signal is repeatedly generated from the timing when it is reset under Vrs commonly applied to the pixels 100 in the column. That is, the signal SF output from pixel 100 is converted into signal AMP via inverter 200 and source follower 204. At this timing, Vsp2 is set to High, the second sampling switch 208B is turned on, and sampling and holding of signal AMP is performed in the second sample-and-hold circuit 210B. Similarly, during the processing of the next pixel 100 in the first sample-and-hold circuit 210A, signal BF2 is output as signal OS via source follower 214.

[0052] As can be read from the timing diagram, the timing of the first sampling switch 208A turning on is during the period when the second output switch 212B is on, and the timing of the second sampling switch 208B turning on is during the period when the first output switch 212A is on. Furthermore, the two sampling switches will not turn on at the same timing, and similarly, the two output switches will not turn on at the same timing.

[0053] As described above, according to this embodiment, the signal value can be fixed to a predetermined value during the period when the signal OS is output as 1 bit. As a result, noise caused by the sampling period during sample-and-hold in the AD conversion of ADC 22 can be suppressed.

[0054] More specifically, in a sample-and-hold circuit, there is generally a sampling period and a holding period for the sampled signal. By controlling the timing as in this embodiment, the signal value during the sampling period is not output from the output signal OS, but the signal value during the holding period after sampling can be output appropriately. As a result, noise caused by fluctuations in the signal value during the sampling period can be suppressed in the AD conversion of ADC 22.

[0055] In addition, Figure 4 The text describes a configuration with two sampling switches 208 connected in parallel, two source followers 210 that perform sample-and-hold operations on each sampling switch 208, and an output switch 212 that selects which sample-and-hold circuit's output to use as the final output. However, it is not limited to this configuration. For example, the structure could be configured such that the signal is distributed to three or more paths, allowing for appropriate selection of sample-and-hold and output.

[0056] (Second Implementation)

[0057] In the first embodiment described above, the outputs from the pixels 100 belonging to a column are input to each element of the output circuit 20 along the same path. As the number of pixels increases and the number of rows increases, the load capacity in the outputs from the pixels 100 belonging to a column increases. In this embodiment, a solid-state imaging device 1 that suppresses signal fluctuations dependent on this load capacity will be described.

[0058] Figure 6 This is a diagram schematically illustrating an example of the output circuit according to the second embodiment. The solid-state imaging device 1 has two or more paths for outputting signals from the pixels 100 in columns, and each path has an input switch 300.

[0059] In the solid-state imaging device 1, for example, pixels 100 belonging to odd-numbered columns and pixels 100 belonging to even-numbered columns are assigned to pixel groups by row. Figure 6 In this example, the solid-state imaging device 1 connects the pixels 100 to the output circuit 20 via two paths in each row. That is, the pixels 100 are assigned by row into groups of pixels belonging to odd-numbered columns and groups of pixels belonging to even-numbered columns, with each group of pixels having a path for transmitting signals to the output circuit 20.

[0060] Each path has an input switch 300. For example, Figure 6 As shown, a first input switch 300A is provided in the path connecting the pixels 100 belonging to the odd-numbered columns to the output circuit 20, and a second input switch 300B is provided in the path connecting the pixels 100 belonging to the even-numbered columns to the output circuit 20.

[0061] Each input switch 300 is an nMOS, and its connection state is set to on / off by applying a voltage to its gate. By incorporating these input switches 300, the output circuit 20 is connected at appropriate timing according to pixel groups.

[0062] Figure 7This is a timing diagram of multiple pixels 100 and output circuit 20. Vrs1 and Vrs2 are signals for resetting pixels 100 belonging to odd and even columns, respectively. In this embodiment, control is also performed in the pixel circuit of pixel 100 so that the reset timing is different for each pixel group.

[0063] When Vrs1 becomes Low after becoming High, a signal SF1 is output from pixel 100 belonging to the odd column via a shift register. This SF1 is input as signal SF to the output circuit 20 at the timing when Vsw1 becomes High and the first input switch 300A is turned on.

[0064] When Vcp becomes High at this timing, the node connected to the bias circuit in the output circuit 20 is switched to a reset potential. That is, the signal AMP is reset. When Vcp becomes Low, the signal AMP becomes the inverted and amplified signal SF via the inverter 200 and the source follower 204.

[0065] The subsequent timing is the same as in the first embodiment described above, outputting the sampled and held signal at an appropriate timing.

[0066] Such as Figure 7 As shown, the first input switch 300A and the second input switch 300B are controlled to be exclusively turned on. Accordingly, for the signal SF input to the output circuit 20, the signal SF1 from the odd-numbered pixel 100 or the signal SF2 from the even-numbered pixel 100 is exclusively selected to be input to the output circuit 20.

[0067] As described above, according to this embodiment, signals input to the output circuit 20 can be separated by pixel groups. Compared to the case where there is one path for each pixel 100 belonging to a row, the load capacity in the output circuit 20 can be reduced when the signals are allocated to pixel groups. Therefore, when the number of pixels in the light-receiving area of ​​the solid-state imaging device 1 is increased, for example, when the resolution is improved, noise and power consumption caused by the load capacity can be reduced.

[0068] Furthermore, the rising response of signal SF can be separated from the reset control in pixel 100. Therefore, it is possible to transmit to output circuit 20 in a state where the output from pixel 100 is more stable.

[0069] In addition, Figure 6In this embodiment, the output from pixel 100 is divided into two paths, but this is not a limitation. For example, it could be done by dividing multiple pixels 100 belonging to the same row into three or more pixel groups, and sampling and holding the output from each pixel group at appropriate timing. This method can be implemented in the same way as the second embodiment described above, by having paths for passing rows by pixel groups, and having a third input switch, then a fourth input switch, ..., and any number of input switches that connect these paths to the sample-and-hold circuit at appropriate timing.

[0070] (Installation Example 1)

[0071] Next, examples of circuit installation in the first and second embodiments described above will be explained. In the output circuit 20, the inverter 200, source follower 204, source follower 210, and source follower 214 can be installed using nMOS transistors.

[0072] Figure 8 This diagram illustrates an example of an inverter in this mounting example. The inverter is constructed, for example, with a resistor R1 and an nMOS M4. One end of resistor R1 is connected to the power supply voltage Vdd, and the other end is connected to the drain of the nMOS M4. The source of the nMOS M4 is connected to the power supply voltage Vss.

[0073] The input voltage Vin is input to the gate of the nMOS M4. The output voltage Vout is output from the node connected to the drain of the nMOS M4.

[0074] In this way, an inverter can also be constructed using nMOS.

[0075] Figure 9 This diagram illustrates an example of a source follower in this mounting example. The source follower is constructed, for example, with an nMOS M5 and a resistor R2. The drain of the nMOS M5 is connected to the power supply voltage Vdd, and the source is connected to one end of the resistor R2. The other end of the resistor R2 is connected to the power supply voltage Vss.

[0076] The input voltage Vin is input to the gate of the nMOS M5. The output voltage Vout is output from the node connected to the source of the nMOS M5.

[0077] In this way, an nMOS transistor can also be used to construct a source follower.

[0078] By making the inverters and source followers nMOS-based structures, the circuit area can be reduced.

[0079] (Installation Example 2)

[0080] Figure 10This is a diagram illustrating another specific example of the circuit elements of the output circuit 20 in the foregoing embodiments. The output circuit 20 may also be installed using a negative feedback amplifier circuit instead of a source follower. In this case, the output circuit 20 includes: an inverter 200; bias circuits 202, 206; negative feedback amplifier circuits 220, 222, 224; a sampling switch 208; and an output switch 212.

[0081] Such as Figure 10 As shown, for example, can Figure 4 , Figure 6 The source follower in the circuit is replaced with a negative feedback amplifier circuit.

[0082] Figure 11 This is a diagram illustrating an example of an inverter in this installation example. As shown... Figure 11 As shown, the inverter 200 can also be configured with a negative feedback circuit and an inverting amplifier circuit.

[0083] Alternatively, negative feedback amplifier circuits 220, 222, and 224 can also be configured to be connected to the same circuit. Figure 11 The negative feedback amplifier circuit shown has the same structure.

[0084] Figure 10 and Figure 11 The amplifier circuit shown can also be constructed using CMOS (Complementary MOS). Although the circuit area increases compared to the first mounting example, the stability of the output signal can be improved by using CMOS.

[0085] Furthermore, in the aforementioned embodiments, the output of each row is processed appropriately, but this is not limited to the row direction; the output of each column can also be processed appropriately. Thus, the output circuit can be configured in an appropriate location within the circuit receiving continuously input signals, similar to the aforementioned embodiments, allowing for appropriate sample-and-hold functionality.

[0086] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A solid-state imaging device, comprising: Multiple pixels, which are configured at least in the column direction; Multiple sampling switches that sample the signals output by the pixels belonging to the column in parallel; Multiple sample-and-hold circuits that sample and hold signals output from the multiple sample switches; as well as Multiple output switches that output the signals stored in the multiple sample-and-hold circuits at predetermined timings. The plurality of sampling switches includes a first sampling switch and a second sampling switch that are turned on at different timings. The plurality of sample-and-hold circuits include: A first sample-and-hold circuit, which is connected to the first sample switch; and The second sample-and-hold circuit is connected to the second sampling switch. The plurality of output switches include a first output switch and a second output switch that turn on at different timings. The first output switch is connected to the first sample-and-hold circuit, and the second output switch is connected to the second sample-and-hold circuit. The timing of the first sampling switch being turned on falls within the period during which the second output switch is turned on. The timing of the second sampling switch being turned on falls within the period during which the first output switch is turned on.

2. The solid-state imaging device according to claim 1, The pixels are arranged in two dimensions in the row direction and the column direction.

3. The solid-state imaging device according to claim 1 or 2, The column is divided into multiple groups to form multiple pixel groups corresponding to the column belonging to the multiple groups. The solid-state imaging device has multiple input switches that are exclusively turned on and connected to each of the pixel groups obtained by the division.

4. The solid-state imaging device according to claim 1, The pixels are arranged in two dimensions in the row direction and the column direction. The solid-state imaging device includes: The first input switch is connected in the row to a plurality of pixels belonging to the even-numbered column; and A second input switch, which connects to a plurality of pixels belonging to the odd-numbered column in the row. The first input switch and the second input switch are turned on in an exclusive manner.

5. The solid-state imaging device according to claim 1 or 2, It includes: an inverter and a first source follower located between the pixel and the sampling switch; and a second source follower connected to the output switch. The signal is output via the second source follower. The inverter, the first source follower, the second source follower, and the plurality of sample-and-hold circuits are composed of nMOS, i.e., n-type metal-oxide-semiconductor field-effect transistors.

6. The solid-state imaging device according to claim 1 or 2, Between the pixel and the sampling switch, there is: An inverter, which is connected to the pixel; The first negative feedback amplifier circuit is connected to the inverter and the sampling switch; and The second negative feedback amplifier circuit is connected to the output switch. The output signal is via the second negative feedback amplifier circuit. The inverter consists of a negative feedback amplifier circuit and an inverting amplifier circuit. The multiple sample-and-hold circuits are composed of negative feedback amplifier circuits.

7. The solid-state imaging device according to claim 1 or 2, It has a buffer that stores the parallel signals output via the plurality of output switches. The signal stored in the buffer is output as a serial signal along the row direction.

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