Large dynamic range readout circuit and method for a graphene photodetector

Abstract

The application belongs to the technical field of CMOS integrated circuit design, and relates to a large dynamic range readout circuit and method of a graphene photodetector; the readout circuit comprises a bias module, an integration module, a voltage comparison module and a switch selection module; the bias module is used for providing a static working point bias voltage to the integration module and injecting a photoelectric signal generated by the graphene photodetector into the integration module; the integration module is used for processing a current signal generated by the graphene photodetector and converting the current signal into a voltage signal; the voltage comparison module is used for comparing an output voltage of the integration module with a threshold voltage; and the switch selection module is used for selecting different integration capacitances according to an output of the voltage comparison module. According to the size of the photocurrent generated in the graphene photodetector, different integration capacitances are selected, the detection rate and dynamic range of the graphene photodetector in dim light are improved, and the noise of the circuit is reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of CMOS integrated circuit design, and particularly relates to a large dynamic range readout circuit and method of a graphene photodetector. BACKGROUND

[0002] The photodetector technology is widely used in military and civilian fields. Its principle is that the conductivity of the irradiated material changes due to radiation. Its working mechanism includes the following processes: (1) the photosensitive device forms photo-generated carriers under irradiation, and the diffusion or drift movement of the carriers forms a photocurrent, wherein the photocurrent is related to the material of the photosensitive device, and different materials have different light responses in the same irradiation range, and the generated photocurrent also has differences; (2) the current signal generated by the photosensitive device is read out, that is, the photocurrent is integrated, and the current signal is converted into a voltage signal by a readout circuit, and the readout circuit converts the current signal into a voltage signal through an integration circuit. The readout circuit is an important component in the photodetector system, and the readout effect will affect the final imaging quality; (3) a series of processing is performed on the voltage signal to finally form an image.

[0003] Traditional photodetectors represented by materials such as mercury cadmium telluride and indium antimonide have the characteristics of fast response speed and high quantum efficiency, but also have problems such as high manufacturing cost, large size, and incompatibility with CMOS process lines. The new type of material photodetector represented by graphene has high carrier migration rate, small size, compatibility with CMOS process lines, and great potential in dynamic range, which is expected to make up for the shortcomings of traditional photodetectors.

[0004] The photosensitive device of the graphene photodetector has a large dynamic range, and the range of change of the photocurrent is large. Current research on graphene photodetectors mostly focuses on the performance of the graphene photosensitive device, and there is little research on the integration of the graphene device and the readout circuit. The role of the readout circuit is to convert the weak current signal generated by the graphene photosensitive device into a voltage signal, and the readout performance of the readout circuit has a great influence on the detection effect of the graphene photodetector. The current readout circuit of the graphene photodetector adopts the structure of a traditional capacitance feedback transimpedance amplification type (CTIA) readout circuit. This circuit structure uses a fixed integration capacitor, and this circuit structure has the problems of low detection dynamic range, low detection efficiency, and large noise. On the one hand, when the integration capacitor is set too small, the integration capacitor will quickly saturate, the dynamic range of the detector will decrease, and the detection effect will be affected. On the other hand, when the integration capacitor is set too large, the integration process becomes slow, and the detection rate is affected. SUMMARY

[0005] In order to solve the problems of low dynamic range and low detection rate caused by only using a single integration capacitor in the integration process of the readout circuit in the existing graphene photodetector, the application provides a large dynamic range readout circuit and method for a graphene photodetector.

[0006] In the first aspect of the application, the application provides a large dynamic range readout circuit for a graphene photodetector, which comprises a bias module, an integration module, a voltage comparison module and a switch selection module; the bias module is used to provide a static working point bias voltage to the integration module and inject a photoelectric signal generated by the graphene photodetector into the integration module; the integration module is used to process a current signal generated by the graphene photodetector and convert the current signal into a voltage signal; the voltage comparison module is used to compare an output voltage from the integration module with a threshold voltage; and the switch selection module is used to select different integration capacitors according to the output of the voltage comparison module.

[0007] Further, the bias module comprises a bias voltage Vsk, a bias voltage Vdet and a bias voltage Vref; wherein one end of the bias voltage Vsk is connected to the pixel resistor RB, one end of the bias voltage Vdet is connected to the light-sensitive pixel resistor RL, the other end of the dark pixel resistor RB is connected to the other end of the bias voltage Vdet, and the connection ends of the dark pixel and the light-sensitive pixel resistor are connected to the integration module, respectively; and the bias voltage Vref is connected to the integration module.

[0008] Further, the integration module comprises an integration capacitor Cmin, an operational amplifier and a reset switch; two ends of the reset switch are connected to the two ends of the integration capacitor Cmin, respectively, and the negative phase input end and the output end of the operational amplifier, and the integration capacitor Cmin is connected in parallel to the operational amplifier; when the reset switch is turned off, integration starts, and after the integration time is reached, the reset switch is turned on, integration ends, and the output end of the operational amplifier outputs the integration voltage Vout1; after integration by the integration capacitor Cmin, the output end of the operational amplifier outputs the integration voltage Vout1 into the voltage comparison module.

[0009] Further, the operational amplifier OP is a PMOS differential input folded cascode amplifier, comprising four NMOS tubes and eight PMOS tubes; wherein the source of the PMOS tube M0, the PMOS tube M3 and the PMOS tube M4 is connected to the power supply voltage VDD, the NMOS tube M10 and the NMOS tube M11 are grounded GND; the gate of the PMOS tube M1 is connected to the input voltage Vip, the drain is connected to the source of the NMOS tube M10 and the NMOS tube M7, and the source is connected to the source of the PMOS tube M2 and the drain of M0; the gate of M0 is connected to the bias voltage Bbias1; the gate of M2 is connected to the input voltage Vin, the drain is connected to the source of the NMOS tube M7 and the NMOS tube M8, the drain of M7 is connected to the drain of the PMOS tube M5 and the gate of M3; the drain of M8 is connected to the drain of the PMOS tube M6, and the connection end is the output voltage Vout of the operational amplifier; the gates of M5 and M6 are connected, and are connected to the bias voltage Bbias4; the gates of M7 and M8 are connected, and are connected to the bias voltage Bbias3; the gates of M10 and M11 are connected, and are connected to the bias voltage Bbias2.

[0010] Further, the voltage comparison module comprises a comparator and an inverter, the negative phase input end of the comparator is connected to the output end of the integral module, the integral voltage Vout1, the positive phase input end of the comparator is connected to the threshold voltage, the comparator compares the integral voltage Vout1 with the threshold voltage Vth, and after comparing the output Vout of the operational amplifier with the threshold voltage Vth, a logic signal "1" or "0" is output; the output end of the comparator is connected to the switch selection module; the input end of the inverter is connected to the output end of the comparator, and the output end of the inverter is connected to the switch selection module.

[0011] Further, the comparator comprises five NMOS tubes and six PMOS tubes; wherein the source of the NMOS tube M21, the NMOS tube M30 and the NMOS tube M31 is grounded GND; the source of the PMOS tube M28, the PMOS tube M24, the PMOS tube M26, the PMOS tube M27, the PMOS tube M25 and the PMOS tube M29 is connected to the power supply voltage VDD; the gate of M21 is connected to the bias voltage Vbias, the drain is connected to the source of the NMOS tube M22 and the source of the NMOS tube M23, the gate of M22 is connected to the voltage Vi1, and the gate of M23 is connected to the voltage Vi2; the drain of M22 is connected to the drain of M28, M24 and M27, and the gates of M24 and M26; the drain of M23 is connected to the drain of M29, M25 and M26, and the gates of M25 and M27; the drain of M28 is connected to the drain and gate of M30, and the drain and gate of M30 are shorted; the drain of M29 is connected to the drain of M31, and the connection end of M29 and M31 is the output voltage Vout.

[0012] Further, the switch selection module comprises a switch TG1, a switch TG2 and a control capacitor Cmax; a first control end of the switch TG1 is connected to an output end of the comparator, a second control end of the switch TG1 is connected to an output end of the inverter; a first control end of the switch TG2 is connected to an output end of the inverter, a second control end of the switch TG2 is connected to an output end of the comparator; an input end of the switch TG1 is connected to an input end of the integration module, an output end of the TG1 is connected to one end of the capacitor Cmax; an input end of the TG2 is connected to one end of the integration capacitor Cmax, an output end of the TG2 is connected to the ground GND.

[0013] In the second aspect of the present application, the present application further provides a large dynamic range readout circuit method of a graphene photodetector, the method comprising:

[0014] The bias module generates bias voltages Vsk, Vdet and Vref, under the action of the bias voltages, the illumination causes the resistance value of the pixel element resistor RL of the graphene photodetector to change, and a photocurrent signal is generated;

[0015] The integration module rapidly integrates the photocurrent signal on the integration capacitor Cmin, outputs an integration voltage Vout1, and enters the voltage comparison module;

[0016] The voltage comparison module compares the integration voltage Vout1 with the threshold voltage Vth of the comparator, and a set of logic control signals is formed after the output end of the voltage comparator passes through the inverter;

[0017] The switch selection module controls the opening and closing of the switch TG1 or / and the switch TG2 according to the logic control signals, so that the control capacitor Cmax acts as an integration capacitor or a bypass capacitor.

[0018] Further, the process in which the control capacitor Cmax acts as an integration capacitor or a bypass capacitor comprises:

[0019] When the integration voltage Vout1 is smaller than the threshold voltage Vth, the switch selection module controls the switch TG2 between the control capacitor Cmax and the ground to be turned on according to the logic control signals, controls the switch TG1 between the integration capacitor Cmin and the control capacitor Cmax to be turned off, and makes the control capacitor Cmax act as a bypass capacitor;

[0020] When the integration voltage Vout1 is larger than the threshold voltage Vth, the switch selection module controls the switch TG2 between the control capacitor and the ground to be turned off according to the logic control signals, controls the switch TG1 between the integration capacitor Cmin and the control capacitor Cmax to be turned on, and makes the control capacitor Cmax act as an integration capacitor, and the control capacitor Cmax and the integration capacitor Cmin together act as an equivalent integration capacitor.

[0021] The beneficial effects of the present application are:

[0022] In the existing graphene photodetector, the module of the readout circuit is composed of an operational amplifier, an integration capacitor and a switch. The readout circuit has the following problems: first, the detection rate and dynamic range of the photodetector are reduced due to the use of only one integration capacitor; second, the noise of the circuit is relatively large. The graphene readout circuit proposed in the present application can select different integration capacitors according to the size of the photocurrent generated by the photosensitive device in the graphene photodetector, and solve the problems of improving the detection rate of the graphene photodetector in dim light, improving the dynamic range of the graphene photodetector and reducing the noise of the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a schematic diagram of the principle structure of the graphene photodetector readout circuit in the embodiment of the present application;

[0024] Figure 2 is a schematic diagram of the circuit structure of the graphene photodetector readout circuit in the embodiment of the present application;

[0025] Figure 3 is a schematic diagram of the operational amplifier in the embodiment of the present application;

[0026] Figure 4 is a schematic diagram of the voltage comparator in the embodiment of the present application;

[0027] Figure 5 is a schematic diagram of the inverter in the embodiment of the present application;

[0028] Figure 6 is a schematic diagram of the switch selection module in the embodiment of the present application;

[0029] Figure 7 is a flowchart of the graphene photodetector readout method in the embodiment of the present application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0031] The present application will be further described in combination with the drawings and embodiments.

[0032] Figure 1 is a schematic diagram of the principle structure of the graphene photodetector readout circuit in the embodiment of the present application, like Figure 1As shown, the readout circuit comprises a bias module, an integration module, a voltage comparison module and a switch selection module; the bias module is used to provide a static working point bias voltage to the integration module, and inject a photoelectric signal generated by the graphene photodetector into the integration module; the integration module is used to process a current signal generated by the graphene photodector, and convert the current signal into a voltage signal; the voltage comparison module is used to compare an output voltage from the integration module with a threshold voltage; and the switch selection module is used to select different integration capacitances according to an output of the voltage comparison module.

[0033] Figure 2 Figure 1 is a circuit structure schematic diagram of a graphene photodetector readout circuit in an embodiment of the present application, as shown in the figure, Figure 2 As shown, the bias module comprises a bias voltage Vsk, a bias voltage Vdet and a bias voltage Vref; wherein one end of the bias voltage Vsk is connected to a dark pixel resistor RB, one end of the bias voltage Vdet is connected to a light sensing pixel resistor RL, the other end of the dark pixel resistor RB is connected to the other end of the bias voltage Vdet, and the connection end of the dark pixel resistor and the light sensing pixel resistor is connected to the integration module; and the bias voltage Vref is connected to the integration module.

[0034] In the embodiment of the present application, under the action of the bias voltages Vsk, Vdet and Vref, the resistance of the light sensing pixel resistor RL of the graphene photodetector changes under illumination, and the resistance of the dark pixel resistor RB does not change, at this time, a photoelectric current is generated. Under no light condition, the dark pixel resistor RB and the light sensing pixel resistor RL of the graphene photodetector are kept the same, the bias voltages Vsk, Vdet and Vref are adjusted so that the integration current is zero, and then the correction of the readout circuit is completed to prevent noise such as dark current from interfering with the photoelectric current signal. Under the condition of illumination, the resistance of the pixel of the graphene photodetector changes, and a photoelectric current is generated under the action of the bias voltage.

[0035] The photoelectric current generated under the action of the bias module and the illumination enters the integration module, and the integration module comprises an integration capacitor Cmin, a folded common-source common-gate operational amplifier OP and a reset switch Srst; two ends of the reset switch are respectively connected to two ends of the integration capacitor Cmin, and a negative phase input end and an output end of the operational amplifier, and the integration capacitor Cmin is connected in parallel with the operational amplifier; when the reset switch is turned off, integration starts, after the integration time is reached, the reset switch is turned on, integration ends, and the output end of the operational amplifier outputs an integration voltage Vout1; after integration by the integration capacitor Cmin, the output end of the operational amplifier outputs the integration voltage Vout1 into the voltage comparison module.

[0036] In some embodiments of the present application, the integral capacitor Cmin has a capacitance of 5fF, and the operational amplifier adopts a PMOS differential input folded cascode structure with high gain and large dynamic range. Figure 3 As shown, the operational amplifier OP is a PMOS differential input cascode amplifier, which includes four NMOS tubes and eight PMOS tubes; wherein the sources of the PMOS tube M0, the PMOS tube M3 and the PMOS tube M4 are connected to the power supply voltage VDD, and the NMOS tube M10 and the NMOS tube M11 are grounded GND; the gate of the PMOS tube M1 is connected to the input voltage Vip, the drain is connected to the source of the NMOS tube M10 and the NMOS tube M7, and the source is connected to the source of the PMOS tube M2 and the drain of M0; the gate of M0 is connected to the bias voltage Bbias1; the gate of M2 is connected to the input voltage Vin, the drain is connected to the source of the NMOS tube M7 and the NMOS tube M8, the drain of M7 is connected to the drain of the PMOS tube M5 and the gate of M3; the drain of M8 is connected to the drain of the PMOS tube M6, and the connection end is used as the output voltage Vout of the operational amplifier; the gates of M5 and M6 are connected, and are connected to the bias voltage Bbias4; the gates of M7 and M8 are connected, and are connected to the bias voltage Bbias3; the gates of M10 and M11 are connected, and are connected to the bias voltage Bbias2. When the reset switch is turned off, the integration starts, and after the integral time is reached, the reset switch is turned on, the integration ends, and the operational amplifier outputs the integral voltage Vout1.

[0037] After integration by the small integral capacitor Cmin, the output voltage Vout1 of the operational amplifier enters the voltage comparison module, and the voltage comparator is as shown. Figure 4 The voltage comparison module includes a comparator and an inverter, the negative phase input end of the comparator is connected to the output integral voltage Vout1 of the integral module, the positive phase input end of the comparator is connected to the threshold voltage, the comparator compares the integral voltage Vout1 with the threshold voltage Vth, and after comparing the output voltage Vout1 of the operational amplifier with the threshold voltage Vth, a logic signal "1" or "0" is output; the output end of the comparator is connected to the switch selection module; the input end of the inverter is connected to the output end of the comparator, and the output end of the inverter is connected to the switch selection module. The voltage comparator compares the output voltage Vout1 from the operational amplifier with the threshold voltage (Vth).

[0038] As shown in Figure 4As shown, the comparator comprises five NMOS tubes and six PMOS tubes; wherein the sources of the NMOS tube M21, the NMOS tube M30 and the NMOS tube M31 are connected to the ground GND; the sources of the PMOS tube M28, the PMOS tube M24, the PMOS tube M26, the PMOS tube M27, the PMOS tube M25 and the PMOS tube M29 are connected to the power supply voltage VDD; the gate of the M21 is connected to the bias voltage Vbias, the drain of the M21 is connected to the source of the NMOS tube M22 and the source of the NMOS tube M23, the gate of the M22 is connected to the voltage V11, the gate of the M23 is connected to the voltage V12; the drain of the M22 is connected to the drain of the M28, the M24 and the M27 and the gate of the M24 and the M26; the drain of the M23 is connected to the drain of the M29, the M25 and the M26 and the gate of the M25 and the M27; the drain of the M28 is connected to the drain and the gate of the M30, the drain and the gate of the M30 are shorted; the drain of the M29 is connected to the drain of the M31, and the connection end of the M29 and the M31 is used as the output voltage Vout.

[0039] After the voltage comparator compares the output voltage Vout of the operational amplifier with the threshold voltage, a logic value "1" (or "0") is outputted. The output of the voltage comparator is connected to the inverter and the switch selection module, as shown in the figure. Figure 5 As shown, the inverter comprises a PMOS tube and an NMOS tube, the gates of the PMOS tube and the NMOS tube are connected to each other, and the drains are connected to each other; and the connected gate is connected to the voltage Vin; and the connected drain is connected to the voltage Vout.

[0040] The switch selection module comprises a switch TG1, a switch TG2 and a control capacitor Cmax; the first control end of the switch TG1 is connected to the output end of the comparator, the second control end of the switch TG1 is connected to the output end of the inverter; the first control end of the switch TG2 is connected to the output end of the inverter, the second control end of the switch TG2 is connected to the output end of the comparator; the input end of the switch TG1 is connected to the input end of the integration module, the output end of the TG1 is connected to one end of the capacitor Cmax; the input end of the TG2 is connected to one end of the integration capacitor Cmax, and the output end of the TG2 is connected to the ground GND.

[0041] In some embodiments of the present application, the structure of the switch TG1 and the switch TG2 is as shown in the figure. Figure 6 As shown, the switch comprises a PMOS tube and an NMOS tube, the source and the drain of the PMOS tube and the NMOS tube are connected to each other in exchange, wherein the gate of the PMOS tube is connected to the gate of the NMOS tube is connected to C; and the source of the PMOS tube, that is, the drain of the NMOS tube is connected to the voltage Vin, and the drain of the PMOS tube, that is, the source of the NMOS tube is connected to the output voltage Vout.

[0042] It can be understood that in the embodiment of the present application, the integral voltage Vout1 is the voltage output by the integral module, that is, the output terminal of the integral module is the output voltage Vout of the operational amplifier, and the output voltage will be the output voltage of the entire readout circuit; therefore, the output voltage Vout is the integral voltage Vout1 of the integral module and also the output voltage of the operational amplifier.

[0043] The output of the voltage comparator passes through an inverter to obtain a non-logical value "0" (or "1"), and when the logical signal is "1" "0", the switches TG1 and TG2 are closed, and the rest of the switches are in an open state. A set of logic control signals is formed by the output of the voltage comparator and the output of the inverter, and the control signal can select whether the capacitor Cmax is used as an integral capacitor or a bypass capacitor. When the output Vout1 of the operational amplifier is greater than the threshold voltage of the voltage comparator, the control signal of the switch TG1 is "0" and "1", TG1 is open, the control signal of the switch TG2 is "1" and "0", TG2 is closed, and at this time the capacitor Cmax functions as a bypass capacitor in the circuit, which can reduce the noise of the circuit; when the output Vout1 of the operational amplifier is less than the threshold voltage Vth of the voltage comparator, the control signal of the switch TG1 is "1" and "0", TG1 is closed, and the control signal of the switch TG2 is "0" and "1", TG2 is open. At this time, the capacitor functions as an integral capacitor, and the equivalent integral capacitor of the circuit is the sum of Cmin and Cmax, and the circuit has a larger dynamic range.

[0044] The working principle of the large dynamic range readout circuit of the graphene photodetector is as follows:

[0045] Under the action of the bias voltage, the resistance value of the photosensitive pixel of the graphene photodetector changes, and then a photoelectric current is generated. The photoelectric current is quickly integrated on a small integral capacitor, and the output value of the integral voltage enters the voltage comparator to compare with the threshold voltage of the voltage comparator. The output of the voltage comparator passes through an inverter to form a set of logic control signals, which in turn control whether the large capacitor functions as an integral capacitor or a bypass capacitor. When the value entering the voltage comparator is less than the threshold voltage, the switch between the large integral capacitor and the ground is turned on, and at this time the large integral capacitor functions as a bypass capacitor, which can reduce the noise of the circuit; when the value entering the voltage comparator is greater than the threshold voltage, the switch between the large capacitor and the ground is turned on, and at this time the large capacitor functions as an integral capacitor, and the equivalent integral capacitor of the integral circuit is the sum of the large capacitor and the small capacitor, which can increase the dynamic range of the circuit.

[0046] Based on the above principles and the above embodiment, Figure 7is a flow chart of a graphene photodetector readout method in the embodiment of the present application, as shown in the figure, the present application also provides a graphene photodetector readout circuit method, the method comprises: Figure 7

[0047] The bias module generates bias voltages Vsk, Vdet, Vref, under the action of the bias voltage, the light causes the resistance value of the photosensitive pixel resistor RL of the graphene photodetector to change, and a photocurrent signal is generated;

[0048] The integration module rapidly integrates the photocurrent signal on the small integration capacitor Cmin, outputs an integration voltage Vout1, and enters the voltage comparison module;

[0049] The voltage comparison module compares the integration voltage Vout1 with the threshold voltage Vth of the comparator, and a set of logic control signals is formed after the output end of the voltage comparator passes through the inverter;

[0050] The switch selection module controls the opening and closing of the switch TG1 or / and the switch TG2 according to the logic control signal, so that the control capacitor Cmax acts as an integration capacitor or a bypass capacitor.

[0051] Further, the process that the control capacitor Cmax acts as an integration capacitor or a bypass capacitor comprises:

[0052] When the integration voltage Vout1 is less than the threshold voltage Vth, the switch selection module controls the switch TG2 between the control capacitor Cmax and the ground to be turned on according to the logic control signal, controls the switch TG1 between the integration capacitor Cmin and the control capacitor Cmax to be closed, and makes the control capacitor Cmax act as a bypass capacitor;

[0053] When the integration voltage Vout1 is greater than the threshold voltage Vth, the switch selection module controls the switch TG2 between the control capacitor and the ground to be disconnected according to the logic control signal, controls the switch TG1 between the integration capacitor Cmin and the control capacitor Cmax to be turned on, and makes the control capacitor Cmax act as an integration capacitor, and the control capacitor Cmax and the integration capacitor Cmin together act as an equivalent integration capacitor.

[0054] It can be understood that the graphene photodetector large dynamic range readout circuit and the graphene photodetector large dynamic range readout method both belong to the same concept of the present application, and the corresponding features can be mutually quoted, and the present application will not be repeated.

[0055] Those skilled in the art can understand that all or part of the steps in the above-mentioned embodiments can be completed by programs instructing related hardware, and the programs can be stored in a computer readable storage medium, which can include ROM, RAM, magnetic disk or optical disk, etc. ​

[0056] While embodiments of the application have been shown and described, it is to be understood that the embodiments described are merely exemplary of the principles and application of the present application. Numerous modifications and adaptations will occur to those skilled in the art without departing from the spirit and scope of the present application. The scope of the application is defined by the appended claims and their equivalents.

Claims

1. A large dynamic range readout circuit for a graphene photodetector, characterized in that, The readout circuit includes a bias module, an integration module, a voltage comparison module, and a switch selection module. The bias module provides a static operating point bias voltage to the integration module and injects the photoelectric signal generated by the graphene photodetector into the integration module. The integration module processes the current signal generated by the graphene photodetector and converts it into a voltage signal. The voltage comparison module compares the output voltage from the integration module with a threshold voltage. The switch selection module selects different integration capacitors based on the output of the voltage comparison module. The voltage comparison module includes a comparator and an inverter. The negative input of the comparator is connected to the integrated voltage Vout1 at the output of the integrator module, and the positive input of the comparator is connected to a threshold voltage. The comparator compares the integrated voltage Vout1 with the threshold voltage Vth. After comparing the integrated voltage Vout1 and the threshold voltage Vth, it outputs a logic signal "1" or "0". The output of the comparator is connected to the switch selection module. The input of the inverter is connected to the output of the comparator, and the output of the inverter is connected to the switch selection module. The integrated voltage Vout1 serves as the output voltage Vout. The switch selection module includes switches TG1 and TG2, and a control capacitor Cmax. The first control terminal of switch TG1 is connected to the output terminal of the comparator, and the second control terminal of switch TG1 is connected to the output terminal of the inverter. The first control terminal of switch TG2 is connected to the output terminal of the inverter, and the second control terminal of switch TG2 is connected to the output terminal of the comparator. The input terminal of switch TG1 is connected to the input terminal of the integrator module, and the output terminal of switch TG1 is connected to one end of the control capacitor Cmax. The input terminal of switch TG2 is connected to one end of the control capacitor Cmax, the other end of the control capacitor Cmax is connected to the output terminal of the integrator module, and the output terminal of switch TG2 is connected to ground (GND).

2. The large dynamic range readout circuit of a graphene photodetector according to claim 1, characterized in that, The bias module includes a bias voltage Vsk, a bias voltage Vdet, and a bias voltage Vref; wherein, the bias voltage Vsk is connected to one end of the dark pixel resistor RB, the bias voltage Vdet is connected to one end of the photosensitive pixel resistor RL, the other end of the dark pixel resistor RB and the other end of the photosensitive pixel resistor RL are connected, and the connection terminals of the two pixel resistors are respectively connected to the integration module and the switch selection module; the bias voltage Vref is connected to the integration module.

3. The large dynamic range readout circuit of a graphene photodetector according to claim 1, characterized in that, The integration module includes an integrating capacitor Cmin, an operational amplifier, and a reset switch. The two ends of the reset switch are connected to the two ends of the stage of the integrating capacitor Cmin, and the negative input and output of the operational amplifier, respectively. The integrating capacitor Cmin is connected in parallel with the operational amplifier. The negative input of the operational amplifier is connected to the output of the bias module, and the positive input of the operational amplifier is connected to the bias voltage Vref of the bias module. When the reset switch is open, integration begins. After the integration time is reached, the reset switch is closed, integration ends, and the output of the operational amplifier outputs the integrated voltage Vout1. After integration by the integrating capacitor Cmin, the output integrated voltage Vout1 of the operational amplifier enters the voltage comparison module.

4. The large dynamic range readout circuit of a graphene photodetector according to claim 3, characterized in that, The operational amplifier OP is a PMOS differential input common-source common-gate amplifier, comprising four NMOS transistors and seven PMOS transistors. The sources of PMOS transistors M0, M3, and M4 are connected to the power supply voltage VDD, while the sources of NMOS transistors M10 and M11 are grounded to GND. The gate of PMOS transistor M1 is connected to the input voltage Vip, and its drain is connected to the drain of M10 and the source of NMOS transistor M7, while its source is connected to the source of PMOS transistor M2 and the drain of M0. The gate of M0 is connected to the bias voltage Bbias1, and the gate of M2 is connected to the input voltage Vi. n, the drain of M11 is connected to the drain of NMOS transistor M8, the drain of M7 is connected to the drain of PMOS transistor M5 and the gate of M3; the drain of M8 is connected to the drain of PMOS transistor M6, and the connection terminal serves as the output voltage Vout of the operational amplifier; the gates of M5 and M6 are connected and connected to the bias voltage Bbias4; the gates of M7 and M8 are connected and connected to the bias voltage Bbias3; the gates of M10 and M11 are connected and connected to the bias voltage Bbias2; the gates of M3 and M4 are connected, the drain of M3 is connected to the source of M5, and the drain of M4 is connected to the source of M6.

5. The large dynamic range readout circuit of a graphene photodetector according to claim 1, characterized in that, The comparator includes five NMOS transistors and six PMOS transistors; the sources of NMOS transistors M21, M30, and M31 are grounded to GND; the sources of PMOS transistors M28, M24, M26, M27, M25, and M29 are connected to the power supply voltage VDD; the gate of M21 is connected to the bias voltage Vbias, and its drain is connected to the source of NMOS transistor M22 and NMOS transistor M23. The source of M22 is connected to the gate of M22, and the gate of M23 is connected to the voltage Vi2. The drain of M22 is connected to the gates of M28, M24, and M26, as well as the drains of M24 and M27. The drain of M23 is connected to the gates of M29, M25, and M27, as well as the drains of M25 and M26. The drain of M28 is connected to the drain and gate of M30, and the drain and gate of M30 are shorted. The drain of M29 is connected to the drain of M31, and the connection between M29 and M31 serves as the output voltage Vout.

6. A method for a large dynamic range readout circuit of a graphene photodetector, characterized in that, The method includes: The bias module generates bias voltages Vsk, Vdet, and Vref. Under the influence of these bias voltages, illumination causes a change in the resistance value of the photosensitive pixel resistor RL of the graphene photodetector, generating a photocurrent signal. The integration module rapidly integrates the photocurrent signal on the integrating capacitor Cmin, outputs the integrated voltage Vout1, and inputs it into the voltage comparison module. The voltage comparison module compares the integrated voltage Vout1 with the comparator's threshold voltage Vth. The output of the comparator is then converted into a set of logic control signals by an inverter. The switch selection module controls the opening and closing of switch TG1 or / and switch TG2 according to the logic control signal, so that the control capacitor Cmax is used as an integrating capacitor or as a bypass capacitor. The voltage comparison module includes a comparator and an inverter. The negative input of the comparator is connected to the integrated voltage Vout1 at the output of the integrator module, and the positive input of the comparator is connected to a threshold voltage. The comparator compares the integrated voltage Vout1 with the threshold voltage Vth. After comparing the integrated voltage Vout1 and the threshold voltage Vth, it outputs a logic signal "1" or "0". The output of the comparator is connected to the switch selection module. The input of the inverter is connected to the output of the comparator, and the output of the inverter is connected to the switch selection module. The integrated voltage Vout1 serves as the output voltage Vout. The switch selection module includes switches TG1 and TG2, and a control capacitor Cmax. The first control terminal of switch TG1 is connected to the output terminal of the comparator, and the second control terminal of switch TG1 is connected to the output terminal of the inverter. The first control terminal of switch TG2 is connected to the output terminal of the inverter, and the second control terminal of switch TG2 is connected to the output terminal of the comparator. The input terminal of switch TG1 is connected to the input terminal of the integrator module, and the output terminal of switch TG1 is connected to one end of the control capacitor Cmax. The input terminal of switch TG2 is connected to one end of the control capacitor Cmax, the other end of the control capacitor Cmax is connected to the output terminal of the integrator module, and the output terminal of switch TG2 is connected to ground (GND).

7. The method for a large dynamic range readout circuit of a graphene photodetector according to claim 6, characterized in that, The process of using the control capacitor Cmax as an integrating capacitor or as a bypass capacitor includes: When the integral voltage Vout1 is smaller than the threshold voltage Vth, the switch selection module turns on the switch TG2 between the control capacitor Cmax and ground according to the logic control signal, turns off the switch TG1 between the integral capacitor Cmin and the control capacitor Cmax, and uses the control capacitor Cmax as a bypass capacitor. When the integral voltage Vout1 is greater than the threshold voltage Vth, the switch selection module disconnects the switch TG2 between the control capacitor Cmax and ground according to the logic control signal, and turns on the switch TG1 between the integral capacitor Cmin and the control capacitor Cmax, so that the control capacitor Cmax is used as the integral capacitor, and together with the integral capacitor Cmin, they are used as the equivalent integral capacitor.

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