Method for testing electrical properties of a device and test structure therefor

Abstract

The embodiment of the present application relates to the field of semiconductor, and provides a kind of device electrical performance test method and its test structure, method comprises: providing at least two transistors, first conductive plug and second conductive plug, first conductive layer is in contact with all first conductive plug, second conductive layer is in contact with all second conductive plug, wherein a transistor is the transistor to be measured;First conductive layer and second conductive layer are carried out graphic processing, form first electrical connection layer and second electrical connection layer, first electrical connection layer is only in contact with all first conductive plug corresponding to the transistor to be measured, second electrical connection layer is only in contact with all second conductive plug corresponding to the transistor to be measured;Variable test signal is provided to first electrical connection layer, second electrical connection layer and the gate of the transistor to be measured, and the output signal of first electrical connection layer and second electrical connection layer is acquired;Based on output signal, detect the electrical performance of the transistor to be measured.The embodiment of the present application is favorable to improve the accuracy of the measured device electrical performance.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor, and in particular to a method for testing electrical performance of a device and a test structure thereof. BACKGROUND

[0002] In the manufacturing process of electronic products, especially integrated circuits, the electrical performance of a device often needs to be tested. In product failure analysis or competitive product analysis, the saturation current of a device in an integrated circuit chip is an important parameter, which represents the current driving capability of the device. Designing a test method that can accurately measure the saturation current of a device in an integrated circuit chip can help product designers understand the current driving capability of important devices in mainstream products in the market, and provide a reference for the design of new products.

[0003] However, when testing the electrical performance of a device in an integrated circuit chip, the resistance of the probe itself, the contact resistance between the probe and the device under test, and the resistance between the internal structures of the device under test will all interfere with the test structure and affect the measurement of the electrical performance of the device, such as reducing the accuracy of measuring the saturation current of a device in an integrated circuit chip.

[0004] Therefore, there is an urgent need to involve a new method for testing the electrical performance of a device to improve the accuracy of measuring the electrical performance of the device. SUMMARY

[0005] Embodiments of the present application provide a method for testing the electrical performance of a device and a test structure thereof, which at least helps to improve the accuracy of measuring the electrical performance of the device.

[0006] According to some embodiments of the present application, the device electrical performance testing method provided by the embodiments of the present application comprises: providing a device, the device comprising at least two spaced-apart transistors, the transistors having a source, a drain and a gate, the transistors further comprising at least two first conductive plugs in contact with the source and at least two second conductive plugs in contact with the drain, the device further comprising a first conductive layer and a second conductive layer, the first conductive layer being in contact with all the first conductive plugs corresponding to the at least two transistors, and the second conductive layer being in contact with all the second conductive plugs corresponding to the at least two transistors, one of the transistors being a transistor to be tested; performing a patterning process on the first conductive layer to form a first electrical connection layer, the first electrical connection layer being in contact with all the first conductive plugs corresponding to the transistor to be tested; performing a patterning process on the second conductive layer to form a second electrical connection layer, the second electrical connection layer being in contact with all the second conductive plugs corresponding to the transistor to be tested; providing a variable test signal to the first electrical connection layer, the second electrical connection layer and the gate of the transistor to be tested, and obtaining output signals of the first electrical connection layer and the second electrical connection layer; and detecting the electrical performance of the transistor to be tested based on the output signals.

[0007] According to some embodiments of the present application, the testing structure provided by the embodiments of the present application comprises: at least two spaced-apart transistors, the transistors having a source, a drain and a gate, the transistors further comprising at least two first conductive plugs in contact with the source and at least two second conductive plugs in contact with the drain, one of the transistors being a transistor to be tested; a first electrical connection layer, the first electrical connection layer being in contact with all the first conductive plugs corresponding to the transistor to be tested; and a second electrical connection layer, the second electrical connection layer being in contact with all the second conductive plugs corresponding to the transistor to be tested.

[0008] The technical solutions provided by the embodiments of the present application have at least the following advantages:

[0009] In actual work of the device, the source of the plurality of transistors is controlled through the first conductive layer, and the drain of the plurality of transistors is controlled through the second conductive layer. In the test circuit, in order to measure the electrical performance of a single transistor, one of the at least two transistors is set as a to-be-tested transistor, and the first conductive layer and the second conductive layer are subjected to patterning treatment to form a first electrical connection layer corresponding to the first conductive layer and a second electrical connection layer corresponding to the second conductive layer. The first electrical connection layer is only in contact and electrical connection with all the first conductive plugs corresponding to the to-be-tested transistor, and the second electrical connection layer is only in contact and electrical connection with all the second conductive plugs corresponding to the to-be-tested transistor. In this way, it is beneficial to avoid interference of the transistors adjacent to the to-be-tested transistor on the test result of the to-be-tested transistor, so as to realize the test on the electrical performance of the single to-be-tested transistor.

[0010] In addition, since the first electrical connection layer is in contact and electrical connection with all the first conductive plugs corresponding to the to-be-tested transistor, it is beneficial to truly simulate the state of mutual parallel connection between the plurality of first conductive plugs in actual work of the to-be-tested transistor, so as to reduce the difference between the resistance at the source in the test circuit and the resistance at the source in the actual work circuit. Since the second electrical connection layer is in contact and electrical connection with all the second conductive plugs corresponding to the to-be-tested transistor, it is beneficial to truly simulate the state of mutual parallel connection between the plurality of second conductive plugs in actual work of the to-be-tested transistor, so as to reduce the difference between the resistance at the drain in the test circuit and the resistance at the drain in the actual work circuit. Moreover, the first electrical connection layer provides a test voltage to the source through each first conductive plug of the to-be-tested transistor, and the second electrical connection layer provides a test voltage to the drain through each second conductive plug of the to-be-tested transistor, so that the test voltage on the source is distributed evenly, and the test voltage on the drain is also distributed evenly, which is beneficial to increase the area where the source and the drain are in a working state. Therefore, forming the first electrical connection layer and the second electrical connection layer is beneficial to improve the accuracy of the electrical performance of the to-be-tested transistor measured by the test circuit, thereby improving the accuracy of the saturation current value of the to-be-tested transistor. BRIEF DESCRIPTION OF DRAWINGS

[0011] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not restrictive, of the embodiments, unless otherwise specified, the drawings do not constitute a proportional limitation.

[0012] Figure 1 A partial top view of the internal structure of the device provided by the embodiments of the present application;

[0013] Figure 2 A schematic diagram of a test method for electrical performance of the device provided by the embodiments of the present application;

[0014] Figure 3 For Figure 2 A partial cross-sectional structure schematic view along the AA1 direction;

[0015] Figure 4 For Figure 2 The corresponding test method schematic diagram;

[0016] Figure 5 Another schematic diagram of the test method for electrical performance of the device provided in the embodiments of the present application;

[0017] Figure 6 For Figure 5 The corresponding test method schematic diagram. DETAILED DESCRIPTION

[0018] As known from the background art, the accuracy of the test results generated by the test method for measuring electrical performance of a device needs to be improved.

[0019] It is found through analysis that the test of the volt-ampere characteristic curve of the device in the integrated circuit chip is currently performed on the conductive layer, which is usually electrically connected between the plurality of conductive structures (such as field effect transistors) in the device, and thus the result measured by the test is not the volt-ampere characteristic curve of a single conductive structure.

[0020] In some embodiments, the device has at least two transistors spaced apart from each other, the transistors have a source, a drain and a gate, and further have at least two first conductive plugs in contact with the source and at least two second conductive plugs in contact with the drain, the device further has a first conductive layer and a second conductive layer, and the first conductive layer is in contact and electrically connected with all the first conductive plugs corresponding to the at least two transistors, and the second conductive layer is in contact and electrically connected with all the second conductive plugs corresponding to the at least two transistors. When the electrical performance of a single transistor is to be measured, a probe for testing is arranged on the conductive plug in contact with the transistor to avoid interference of the adjacent transistor with the test result of the transistor.

[0021] In the actual work of the device, the first conductive plugs are arranged on the sources of the plurality of transistors, the plurality of first conductive plugs are electrically connected through the first conductive layer, the second conductive plugs are arranged on the drains of the plurality of transistors, and the plurality of second conductive plugs are electrically connected through the second conductive layer, so that the sources of the plurality of transistors are controlled through the first conductive layer and the drains of the plurality of transistors are controlled through the second conductive layer.

[0022] However, on one hand, in actual operation, the at least two first conductive plugs connected with the source of the transistor under test are all in contact with the same first conductive layer, and the at least two second conductive plugs connected with the drain of the transistor under test are all in contact with the same second conductive layer, so that in the actual operation circuit, the first conductive plugs are in parallel connection and the second conductive plugs are in parallel connection, and thus the equivalent resistance of the at least two first conductive plugs at the source is smaller than the resistance of a single first conductive plug, and the equivalent resistance of the at least two second conductive plugs at the drain is smaller than the resistance of a single second conductive plug. When the transistor under test is tested, the probe for testing the source is arranged on only one of the first conductive plugs, so that in the testing circuit, the resistance at the source is the resistance of the single first conductive plug, which is larger than the resistance at the source in the actual operation circuit, and the probe arranged on only one of the first conductive plugs causes the test voltage applied to the source by the probe through the first conductive plug to be unevenly distributed on the source, i.e., the voltage at the local area of the source close to the first conductive plug can reach the size of the test voltage, while the voltage at other areas of the source cannot reach the size of the test voltage, which means that the area of the source actually in the working state is smaller than the area in the actual operation. Similarly, in the testing circuit, the resistance at the drain is the resistance of the single second conductive plug, which is larger than the resistance at the drain in the actual operation circuit, and when the probe for testing the drain is arranged on only one of the second conductive plugs, the area of the drain actually in the working state is also smaller than the area in the actual operation.

[0023] In the testing circuit, the resistance at the source is larger than the resistance at the source in the actual operation circuit, and the resistance at the drain is larger than the resistance at the drain in the actual operation circuit, or the area of the source actually in the working state is smaller than the area in the actual operation, or the area of the drain actually in the working state is smaller than the area in the actual operation, all of which will cause the saturation current value of the transistor under test measured by the testing circuit to be smaller than the saturation current value of the transistor under test in the actual operation, thereby affecting the accuracy of the test result of the transistor under test.

[0024] On the other hand, the resistance of the probe arranged on the first conductive plug and the second conductive plug of the transistor under test, and the contact resistance between the probe and the first conductive plug or the second conductive plug will all occupy a part of the test voltage, so that the voltage actually applied to the source or the drain by the probe is smaller than the voltage value set to the probe and should be applied to the source or the drain, thereby causing the saturation current value of the transistor under test measured by the testing circuit to be smaller than the saturation current value of the transistor under test in the actual operation, thereby affecting the accuracy of the test result of the transistor under test.

[0025] The embodiment of the present application provides a kind of device electrical performance test method, comprising: the first conductive layer and second conductive layer are carried out graphic processing, form the first electric connection layer corresponding with the first conductive layer and the second electric connection layer corresponding with the second conductive layer, avoid the source electrode of the transistor to be measured and the source electrode of other transistors to be connected by the first electric connection layer, avoid the drain electrode of the transistor to be measured and the drain electrode of other transistors to be connected by the second electric connection layer, so as to facilitate avoiding the test result of the transistor to be measured caused by other transistors interference, to realize the test of single transistor electrical performance.In addition, the first electric connection layer and the second electric connection layer facilitate simulating the state that multiple first conductive plugs are mutually connected in parallel and multiple second conductive plugs are mutually connected in parallel when the transistor to be measured is actually working, to reduce the difference between the resistance at source electrode in test circuit and the resistance at source electrode in actual working circuit and reduce the difference between the resistance at drain electrode in test circuit and the resistance at drain electrode in actual working circuit, and the first electric connection layer and the second electric connection layer facilitate increasing the area of source electrode and drain electrode in working state, so as to facilitate improving the accuracy of the electrical performance of the transistor to be measured measured by test circuit, thereby improving the accuracy of the saturation current value of the transistor to be measured.

[0026] To make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that in the embodiments of the present application, many technical details are proposed in order to make the readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed by the present application can be implemented.

[0027] The embodiment of the present application provides a kind of device electrical performance test method, and the semiconductor structure provided by the embodiment of the present application will be described in detail below with reference to the drawings. Figure 1 The partial top view structure schematic diagram inside the device provided by the embodiment of the present application is shown in the figure. Figure 2 The partial top view structure schematic diagram inside the device provided by the embodiment of the present application is shown in the figure. Figure 3 The partial top view structure schematic diagram inside the device provided by the embodiment of the present application is shown in the figure. Figure 2 The partial top view structure schematic diagram inside the device provided by the embodiment of the present application is shown in the figure. Figure 4 The partial top view structure schematic diagram inside the device provided by the embodiment of the present application is shown in the figure. Figure 2 The partial top view structure schematic diagram inside the device provided by the embodiment of the present application is shown in the figure. Figure 5 The partial top view structure schematic diagram inside the device provided by the embodiment of the present application is shown in the figure. Figure 6 The partial top view structure schematic diagram inside the device provided by the embodiment of the present application is shown in the figure. Figure 5 The partial top view structure schematic diagram inside the device provided by the embodiment of the present application is shown in the figure.

[0028] Reference Figures 1 to 6 The device electrical performance test method includes the following steps:

[0029] Reference Figure 1 AndFigure 2 The device comprises at least two transistors spaced apart from each other, each transistor having a source 110, a drain 120 and a gate 130, and further having at least two first conductive plugs 140 in contact with the source 110 and at least two second conductive plugs 150 in contact with the drain 120, and further comprising a first conductive layer 102 in contact with all the first conductive plugs 140 corresponding to the at least two transistors, and a second conductive layer 103 in contact with all the second conductive plugs 150 corresponding to the at least two transistors, wherein one of the transistors is a transistor to be tested 101.

[0030] It should be noted that the device has a substrate 100, and the source 110 and the drain 120 of each transistor are located in the substrate 100. In the direction of the substrate 100 pointing to the first conductive plug 140, Figure 1 The part of the substrate 100 enclosed in the dashed box I in FIG. 1 is the source 110, and the part of the substrate 100 enclosed in the dashed box II in FIG. 1 is the drain 120, and the gate 130 is located above the surface of the substrate 100. Figure 1 In the example of FIG. 1, the source 110 or the drain 120 of two adjacent transistors is shared, and the gate 130 of all the transistors is shared. In actual applications, the source, the drain and the gate of different transistors can not be shared. Continuing to refer to FIG. 1, Figure 1 The device further comprises a third conductive layer 131 in contact with the gates 130 of all the transistors, a fourth conductive plug 114 on the substrate 104, and a fifth conductive layer 124 in contact with the fourth conductive plug 114.

[0031] It should be noted that, Figure 1 In the example of FIG. 1, the same source 110 has four first conductive plugs 140, the same drain 120 has four second conductive plugs 150, the gate 130 has one third conductive plug 131, and the substrate 104 has eight fourth conductive plugs 114. In actual applications, the number of first conductive plugs on the same source and the number of second conductive plugs on the same drain are both not less than two, and the number of third conductive plugs and the number of fourth conductive plugs are not limited.

[0032] It should be noted that the transistor to be measured 101 can include a plurality of sub-transistors, that is, the local region of the substrate 100 corresponding to one first conductive plug 140 in the transistor to be measured 101 is the source electrode of one sub-transistor, the source electrode 110 of the transistor to be measured 101 is collectively formed by the source electrodes of a plurality of sub-transistors, and the local region of the substrate 100 corresponding to one second conductive plug 150 in the transistor to be measured 101 is the drain electrode of one sub-transistor, the drain electrode 120 of the transistor to be measured 101 is collectively formed by the drain electrodes of a plurality of sub-transistors, Figure 1 In the embodiment, one transistor to be measured 101 includes four sub-transistors, and in actual application, the number of sub-transistors in the same transistor to be measured 101 is not limited. The electrical performance of the sub-transistors in the transistor to be measured 101 can be reflected by the electrical performance of the transistor to be measured 101. In addition, the transistors other than the transistor to be measured 101 can also include a plurality of sub-transistors.

[0033] It should be noted that in some embodiments, the first conductive plug 140 is flush with the top surface of the substrate 100, the second conductive plug 150 is flush with the top surface of the substrate 100, the third conductive plug 131 is flush with the top surface of the substrate 100, and the fourth conductive plug 114 is flush with the top surface of the substrate 100. Moreover, in the direction in which the substrate 100 points to the first conductive plug 140, the thickness of the first conductive layer 102, the thickness of the second conductive layer 103, the thickness of the fourth conductive layer 132, and the thickness of the fifth conductive layer 124 are equal, that is, the first conductive layer 102, the second conductive layer 103, the fourth conductive layer 132, and the fifth conductive layer 124 are structures arranged in the same layer.

[0034] In combination with reference to Figure 1 and Figure 2 The first conductive layer 102 is subjected to a patterning process to form a first electrically connecting layer 112, and the first electrically connecting layer 112 is in contact with and electrically connected to all the first conductive plugs 140 corresponding to the transistor to be measured 101. The second conductive layer 103 is subjected to a patterning process to form a second electrically connecting layer 113, and the second electrically connecting layer 113 is in contact with and electrically connected to all the second conductive plugs 150 corresponding to the transistor to be measured 101.

[0035] Since the first electrically-conductive layer 112 is only in contact with all the first electrically-conductive plugs 140 corresponding to the transistor 101 under test, and the second electrically-conductive layer 113 is only in contact with all the second electrically-conductive plugs 150 corresponding to the transistor 101 under test, in this way, the first electrically-conductive layer 112 and the second electrically-conductive layer 113 are beneficial to simulate the state that the plurality of first electrically-conductive plugs 140 are in parallel with each other and the plurality of second electrically-conductive plugs 150 are in parallel with each other when the transistor 101 under test is actually working, so as to reduce the difference between the resistance at the source 110 in the test circuit and the resistance at the source 110 in the actually working circuit, and reduce the difference between the resistance at the drain 120 in the test circuit and the resistance at the drain 120 in the actually working circuit, and furthermore, the first electrically-conductive layer 112 and the second electrically-conductive layer 113 are beneficial to increase the area of the source 110 and the drain 120 in the working state, so as to be beneficial to improve the accuracy of the electrical performance of the transistor 101 under test measured by the test circuit, so as to improve the accuracy of the saturation current value of the transistor 101 under test, so as to improve the accuracy of the electrical performance and the saturation current value of the sub-transistor in the transistor 101 under test measured.

[0036] In addition, the fifth electrically-conductive layer 124 is in contact with all the fourth electrically-conductive plugs 114, which is beneficial to simulate the state that the plurality of fourth electrically-conductive plugs 114 are in parallel with each other when the transistor 101 under test is actually working, and furthermore, is beneficial to increase the area of the substrate 104 in the working state, so as to be beneficial to improve the accuracy of the electrical performance of the transistor 101 under test measured by the test circuit, so as to improve the accuracy of the saturation current value of the transistor 101 under test.

[0037] In some embodiments, in combination with reference to Figure 2 and Figure 3The surface where the source 110 of the transistor 101 is located is a first plane, and the orthographic projection of the first electrically-conductive layer 112 on the first plane covers the orthographic projection of all the first electrically-conductive plugs 140 corresponding to the transistor 101 on the first plane. The surface where the drain 120 of the transistor 101 is located is a second plane, and the orthographic projection of the second electrically-conductive layer 113 on the second plane covers the orthographic projection of all the second electrically-conductive plugs 150 corresponding to the transistor 101 on the second plane. In this way, the first electrically-conductive layer 112 facilitates uniform application of the test voltage or test current on the source 110 through each first electrically-conductive plug 140 corresponding to the transistor 101, and the second electrically-conductive layer 113 facilitates uniform application of the test voltage or test current on the drain 120 through each second electrically-conductive plug 150 corresponding to the transistor 101, so that the working state of the transistor 101 in the test circuit is closer to the working state of the transistor 101 in the actual working circuit, thereby improving the accuracy of the electrical performance of the transistor 101 measured through the first electrically-conductive layer 112 and the second electrically-conductive layer 113, and improving the accuracy of the electrical performance and saturation current value of the sub-transistors in the transistor 101 measured.

[0038] In addition, the surface where the substrate 104 is located is a third plane, and the orthographic projection of the fifth electrically-conductive layer 124 on the third plane covers the orthographic projection of all the fourth electrically-conductive plugs 114 on the substrate 104 on the third plane. The plane where the gate 130 is located away from the base 100 is a fourth plane, and the orthographic projection of the third electrically-conductive layer on the fourth plane covers the orthographic projection of all the third electrically-conductive plugs 131 on the gate 130 on the fourth plane. In this way, the fifth electrically-conductive layer 124 facilitates uniform application of the test voltage or test current on the substrate 104 through each fourth electrically-conductive plug 114 corresponding to the substrate 104, and the third electrically-conductive layer facilitates simulation of the state of transmission of the electrical signal to the gate 130 in the actual working circuit, so that the working state of the transistor 101 in the test circuit is closer to the working state of the transistor 101 in the actual working circuit, thereby improving the accuracy of the electrical performance of the transistor 101 measured, and improving the accuracy of the electrical performance of the sub-transistors in the transistor 101 measured.

[0039] In some embodiments, the step of patterning the first conductive layer 102 can further include forming at least one third electrically connecting layer 122, each third electrically connecting layer 122 being in contact with only the first conductive plug 140 corresponding to one transistor other than the transistor under test 101. The step of patterning the second conductive layer 103 can further include forming at least one fourth electrically connecting layer 123, each fourth electrically connecting layer 123 being in contact with only the second conductive plug 150 corresponding to one transistor other than the transistor under test 101. The one transistor other than the transistor under test 101 can include a column of sub-transistors, Figure 2 In the example where the one transistor other than the transistor under test 101 includes a column of four sub-transistors, the number of sub-transistors in the one transistor other than the transistor under test 101 is not limited in actual applications.

[0040] In this way, when the one transistor other than the transistor under test 101 needs to be tested for electrical performance, the third electrically connecting layer 122 and the fourth electrically connecting layer 123 can simulate the state in which the plurality of first conductive plugs 140 and the plurality of second conductive plugs 150 are in parallel with each other when the one transistor other than the transistor under test 101 is actually working, so as to reduce the difference between the resistance at the source 110 in the test circuit and the resistance at the source 110 in the actually working circuit and reduce the difference between the resistance at the drain 120 in the test circuit and the resistance at the drain 120 in the actually working circuit. In addition, the first electrically connecting layer 112 and the second electrically connecting layer 113 are conducive to increasing the area of the source 110 and the drain 120 in the working state, thereby being conducive to improving the accuracy of the electrical performance of the one transistor other than the transistor under test 101 measured by the test circuit and improving the universality of the test method provided in the embodiments.

[0041] It should be noted that the orthographic projection of the third electric connection layer 122 on the first plane can cover the orthographic projection on the first plane of all the first conductive plugs 140 on the transistors corresponding to the third electric connection layer 122, and the orthographic projection of the fourth electric connection layer 123 on the second plane can cover the orthographic projection on the second plane of all the second conductive plugs 150 on the transistors corresponding to the fourth electric connection layer 123. In this way, when a transistor other than the transistor to be tested 101 needs to be tested for electrical performance, the third electric connection layer 122 facilitates uniform application of a test voltage or test current to the source 110 through each first conductive plug 140 corresponding to a transistor other than the transistor to be tested 101, and the fourth electric connection layer 123 facilitates uniform application of a test voltage or test current to the drain 120 through each second conductive plug 150 corresponding to a transistor other than the transistor to be tested 101, so that the working state of a transistor other than the transistor to be tested 101 in the test circuit is closer to the working state of the transistor in the actual working circuit, thereby improving the accuracy of the electrical performance of the transistor to be tested 101 measured by the third electric connection layer 122 and the fourth electric connection layer 123.

[0042] It should be noted that when the first conductive layer 102 and the second conductive layer 103 are a structure provided in the same layer, the patterning process of the first conductive layer 102 and the second conductive layer 103 can be performed simultaneously, which facilitates simplifying the process steps of preparing the first electric connection layer 112 and the second electric connection layer 113, and when the third electric connection layer 122 and the fourth electric connection layer 123 need to be formed, the first electric connection layer 112, the second electric connection layer 113, the third electric connection layer 122 and the fourth electric connection layer 123 can also be formed by the same patterning process, so as to simplify the process steps of preparing the third electric connection layer 122 and the fourth electric connection layer 123. In other embodiments, the first electric connection layer and the second electric connection layer can also be prepared in steps, and when the third electric connection layer and the fourth electric connection layer need to be formed, the third electric connection layer and the fourth electric connection layer can also be prepared in steps.

[0043] In some embodiments, the first conductive layer 102 and the second conductive layer 103 are both located in the device, and before the first conductive layer 102 and the second conductive layer 103 are subjected to the patterning process, the test method further comprises: performing a planarization process on the device until the top surface of the first conductive layer 102 and the top surface of the second conductive layer 103 are exposed. In addition, when the first conductive layer 102, the second conductive layer 103, the fourth conductive layer 132 and the fifth conductive layer 124 are a structure provided in the same layer, the above-mentioned planarization process will also expose the top surface of the fourth conductive layer 132 and the top surface of the fifth conductive layer 124.

[0044] In this process, focused ion beam (FIP) technology can be used to pattern the first conductive layer 102 and the second conductive layer 103. FIP technology is a novel micro-nano fabrication technology that integrates morphology observation, sample preparation, composition analysis, thin film deposition, and maskless etching. Moreover, the compatibility of FIP technology with semiconductor processes allows these two technologies to be combined, greatly improving the accuracy and speed of material, process, and device analysis and repair in the microelectronics industry. Therefore, patterning the first conductive layer 102 and the second conductive layer 103 using FIP technology is beneficial for improving the dimensional accuracy of the formed first electrical connection layer 112 and the second electrical connection layer 113.

[0045] The process parameters for focused ion beam (FIB) technology include a voltage of 20kV to 30kV and a beam current of 5nA to 20nA. When the process parameters are within this range, while ensuring high dimensional accuracy of the formed first electrical connection layer 112 and second electrical connection layer 113, it is beneficial to improve the efficiency of fabricating the first electrical connection layer 112 and second electrical connection layer 113. In some embodiments, the operating mode of the apparatus used to form the FIB can be adjusted to an ion-enhanced etching mode. This improves the alignment accuracy of the FIB during the patterning process of the first conductive layer 102 and second conductive layer 103, and allows for fine-tuning of the shape of the initially formed first electrical connection layer 112 and second electrical connection layer 113, thereby further improving the dimensional accuracy of the formed first electrical connection layer 112 and second electrical connection layer 113.

[0046] refer to Figures 2 to 6 After forming the first electrical connection layer 112 and the second electrical connection layer 113, the test method further includes: providing a variable test signal to the first electrical connection layer 112, the second electrical connection layer 113 and the gate of the transistor under test 101, and acquiring the output signals of the first electrical connection layer 112 and the second electrical connection layer 113.

[0047] The steps of providing a variable test signal and acquiring an output signal include: providing a first test signal to the first electrical connection layer 112 and acquiring a first output signal of the first electrical connection layer 112, wherein the first test signal is a fixed voltage signal; providing a second test signal to the second electrical connection layer 113 and acquiring a second output signal of the second electrical connection layer 113; and providing a third test signal to the gate 130 of the transistor under test 101, wherein the third test signal is a voltage signal.

[0048] It should be noted that in some embodiments, the first test signal can be 0V, that is, by providing the first test signal to the first electrical connection layer 112, the source electrode is in a 0V state. In addition, for different types of transistors 101 to be tested, the gate 130 voltage of the transistor 101 to be tested in the saturation state can be different, so when testing different types of transistors 101 to be tested, the voltage signal provided by the third test signal to the gate 130 can be different.

[0049] The method of providing the first test signal and the second test signal and obtaining the first output signal and the second output signal can be at least in the following two ways:

[0050] In some embodiments, referring to Figure 2 and Figure 4 , the first probe d and the second probe e are provided, the first test signal is provided through the first probe d, and the first output signal is obtained through the second probe e; the third probe c and the fourth probe b are provided, the second output signal is obtained through the third probe c, and the second test signal is provided through the fourth probe b, wherein the first output signal and the second test signal are both current signals, and the first test signal and the second output signal are both voltage signals.

[0051] The first probe d and the second probe e are both in contact with the first electrical connection layer 112, and the contact positions of the first probe d and the second probe e with the first electrical connection layer 112 are different; the third probe c and the fourth probe b are both in contact with the second electrical connection layer 113, and the contact positions of the third probe c and the fourth probe b with the first electrical connection layer 112 are different.

[0052] In addition, referring to Figure 4 , the test method further comprises: providing a voltage detection module, the voltage detection module being electrically connected between the first probe d and the third probe c, the voltage detection module obtaining a source-drain voltage value based on the first test signal and the second output signal; providing a current detection module, the current detection module being electrically connected between the second probe e and the fourth probe b, the current detection module obtaining a source-drain current value based on the first output signal and the second test signal.

[0053] The first probe d, the voltage detection module, and the third probe c form a first circuit closed loop, and the current in the first circuit closed loop is minimal, approximately zero, so the resistance of the first probe d and the third probe c itself, the contact resistance between the first probe d and the first electrical connection layer 112, and the contact resistance between the third probe c and the second electrical connection layer 113 generate a voltage drop in the first circuit closed loop, which is approximately zero. Therefore, in the first circuit closed loop, the source-drain voltage value can be accurately obtained through the voltage detection module, thereby facilitating the improvement of the accuracy of measuring the electrical performance of the transistor 101 to be tested.

[0054] The second probe e, the current detection module, and the fourth probe b form a second circuit closed loop with the transistor 101, and the first circuit closed loop and the second circuit closed loop do not interfere with each other. In the second circuit closed loop, the current flowing through the second probe e, the fourth probe b, and the transistor 101 is the same, and thus the resistance of the second probe e and the fourth probe b, the contact resistance between the second probe e and the first electrical connection layer 112, and the contact resistance between the fourth probe b and the second electrical connection layer 113 do not interfere with the source-drain current value obtained by the current detection module.

[0055] Therefore, the method of measuring the transistor 101 by the first probe d, the second probe e, the third probe c, and the fourth probe b can improve the accuracy of the source-drain voltage value obtained by the voltage detection module, thereby improving the accuracy of the electrical performance of the transistor 101 measured.

[0056] In other embodiments, referring to Figure 5 and Figure 6 , a source probe g is provided to provide a first test signal and obtain a first output signal, and a drain probe h is provided to provide a second test signal and obtain a second output signal. The first test signal and the second test signal are both voltage signals, and the first output signal and the second output signal are both current signals.

[0057] In addition, referring to Figure 6 , the test method further includes providing a voltage detection module electrically connected between the source probe g and the drain probe h, and obtaining a source-drain voltage value based on the first test signal and the second test signal by the voltage detection device. A current detection module is electrically connected between the source probe g and the drain probe h, and a source-drain current value is obtained based on the first output signal and the second output signal by the current detection device.

[0058] In the above two embodiments, when the contact electrical connection between the gates 130 of all transistors forms a third conductive layer, the device further has a third conductive plug 131 in contact with the third conductive layer. The method of providing a third test signal to the gate 130 of the transistor 101 under test can include providing a fifth probe a to provide a third test signal to the third conductive plug 131 through the fifth probe a.

[0059] The fifth probe a is in contact with the third conductive plug 131. In some embodiments, the third conductive plug 131 is in contact with the fourth conductive layer 132 away from the surface of the substrate 100, and the fifth probe a indirectly provides the third test signal to the gate 130 by applying the third test signal to the fourth conductive layer 132.

[0060] Further, when the fourth conductive plug 114 and the fifth conductive layer 124 in contact with the fourth conductive plug 114 on the substrate 104 in the device are electrically connected, the testing method further comprises: providing a sixth probe f, and electrically connecting the sixth probe f with the fifth conductive layer 124, so that the sixth probe f applies a constant voltage signal to the substrate 104 through the fifth conductive layer 124 and the fourth conductive plug 114. In some embodiments, the constant voltage signal applied to the substrate 104 by the sixth probe f is 0 V.

[0061] In the above various embodiments, after the output signals of the first electrically connecting layer 112 and the second electrically connecting layer 113 are obtained, the electrical performance of the transistor 101 to be tested is detected based on the output signals.

[0062] The electrical performance of the transistor 101 to be tested includes a volt-ampere characteristic curve.

[0063] In some embodiments, the volt-ampere characteristic curve of the transistor 101 to be tested can be obtained based on the source-drain voltage value and the source-drain current value. Further, when the voltage corresponding to the third test signal provided to the gate 130 of the transistor 101 to be tested is equal to the source-drain voltage value, the saturation current of the transistor 101 to be tested can be obtained according to the volt-ampere characteristic curve of the transistor 101 to be tested. In other embodiments, based on the source-drain voltage value and the source-drain current value, the equivalent resistance of the transistor 101 to be tested at each stage can also be obtained.

[0064] It should be noted that when the voltage corresponding to the third test signal provided to the gate 130 of the transistor 101 to be tested is equal to the source-drain voltage value, the transistor 101 to be tested is in a saturated state, and the source-drain current value obtained at this time is the saturation current value of the transistor 101 to be tested. In some embodiments, the voltage signal corresponding to the first test signal provided by the first probe d is 0 V, the test signal provided by the third probe c is adjusted so that the source-drain voltage value changes from 0 V to 12 V, the voltage signal applied to the substrate 104 by the sixth probe f is 0 V, and the gate voltage of the transistor 101 to be tested when it is in a saturated state is 1.1 V, i.e., the voltage signal applied to the gate 139 by the fifth probe a is 1.1 V. When the source-drain voltage value is equal to the gate voltage 1.1 V, the source-drain current value corresponding to the source-drain voltage value at this time is the saturation current value of the transistor 101 to be tested.

[0065] In summary, by forming the first electric connection layer 112 and the second electric connection layer 113, the state of the plurality of first conductive plugs 140 being in parallel with each other and the state of the plurality of second conductive plugs 150 being in parallel with each other in the actual working transistor 101 are simulated, so as to reduce the difference between the resistance at the source 110 in the test circuit and the resistance at the source 110 in the actual working circuit and reduce the difference between the resistance at the drain 120 in the test circuit and the resistance at the drain 120 in the actual working circuit. In addition, the first electric connection layer 112 and the second electric connection layer 113 are beneficial to increase the area of the source 110 and the drain 120 in the working state, thereby improving the accuracy of the electrical performance of the transistor 101 measured by the test circuit and improving the accuracy of the saturation current value of the transistor 101, so as to help the product designers to understand the current driving capability of the important devices in the mainstream products in the market and provide a reference for the design of new products.

[0066] Another embodiment of the present application also provides a test structure for implementing the above test method.

[0067] Reference Figure 1 The test structure comprises: at least two transistors spaced from each other, the transistor having a source 110, a drain 120 and a gate 130, the transistor further having at least two first conductive plugs 140 in contact with the source 110 and at least two second conductive plugs 150 in contact with the drain 120, wherein one transistor is the transistor 101 to be tested; a first electric connection layer 112, the first electric connection layer 112 being in contact with all the first conductive plugs 140 corresponding to the transistor 101 to be tested; and a second electric connection layer 113, the second electric connection layer 113 being in contact with all the second conductive plugs 150 corresponding to the transistor 101 to be tested.

[0068] The test structure can further comprise: a third electric connection layer 122, each third electric connection layer 122 being in contact with the first conductive plugs 140 corresponding to one transistor other than the transistor 101 to be tested; and a fourth electric connection layer 123, each fourth electric connection layer 123 being in contact with the second conductive plugs 150 corresponding to one transistor other than the transistor 101 to be tested.

[0069] In addition, the test structure has a substrate 100, and the test structure further comprises: a third conductive layer formed by the contact between the gates 130 of all the transistors, a third conductive plug 131 in contact with the third conductive layer, a fourth conductive layer 132 in contact with the third conductive plug 131, a substrate 104, a fourth conductive plug 114 on the substrate 104 and a fifth conductive layer 124 in contact with the fourth conductive plug 114.

[0070] It should be noted that the transistor to be measured 101 can include multiple sub-transistors, i.e. the local region of the substrate 100 corresponding to one first conductive plug 140 in the transistor to be measured 101 is the source electrode of one sub-transistor, the source electrode 110 of the transistor to be measured 101 is collectively formed by the source electrodes of multiple sub-transistors, and the local region of the substrate 100 corresponding to one second conductive plug 150 in the transistor to be measured 101 is the drain electrode of one sub-transistor, the drain electrode 120 of the transistor to be measured 101 is collectively formed by the drain electrodes of multiple sub-transistors, in addition, one transistor other than the transistor to be measured 101 can include a column of sub-transistors, Figure 1 For example, in the above embodiment, one transistor to be measured 101 includes a column of four sub-transistors, and one transistor other than the transistor to be measured 101 includes a column of four sub-transistors, but in actual application, the number of sub-transistors in the same transistor to be measured 101 and the number of sub-transistors in one transistor other than the transistor to be measured 101 are not limited.

[0071] Since the first electrically connecting layer 112 is only in contact with all the first conductive plugs 140 corresponding to the transistor to be measured 101, and the second electrically connecting layer 113 is only in contact with all the second conductive plugs 150 corresponding to the transistor to be measured 101, in this way, the first electrically connecting layer 112 and the second electrically connecting layer 113 are conducive to simulating the state of multiple first conductive plugs 140 being in parallel with each other and multiple second conductive plugs 150 being in parallel with each other when the transistor to be measured 101 is actually working, so as to reduce the difference between the resistance at the source electrode 110 in the test circuit and the resistance at the source electrode 110 in the actual working circuit, and reduce the difference between the resistance at the drain electrode 120 in the test circuit and the resistance at the drain electrode 120 in the actual working circuit, and the first electrically connecting layer 112 and the second electrically connecting layer 113 are conducive to increasing the area of the source electrode 110 and the drain electrode 120 in the working state, thereby being conducive to improving the accuracy of the electrical performance of the transistor to be measured 101 measured by the test circuit, thereby improving the accuracy of the saturation current value of the transistor to be measured 101, so as to improve the accuracy of the electrical performance and the saturation current value of the sub-transistors in the transistor to be measured 101 measured.

[0072] It should be understood by those skilled in the art that the above embodiments are specific embodiments for implementing the present application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, therefore, the protection scope of the present application should be limited by the scope defined in the claims.

Claims

1. A method of testing electrical performance of a device, characterized by, The method comprises the following steps: providing a device, the device comprising at least two transistors spaced apart from each other, each transistor having a source, a drain and a gate, and each transistor further comprising at least two first conductive plugs in contact with the source and at least two second conductive plugs in contact with the drain, the device further comprising a first conductive layer and a second conductive layer, wherein the first conductive layer is in contact with all the first conductive plugs corresponding to the at least two transistors, and the second conductive layer is in contact with all the second conductive plugs corresponding to the at least two transistors, and one of the transistors is a transistor to be tested; performing a patterning process on the first conductive layer to form a first electrical connection layer, wherein the first electrical connection layer is in contact with all the first conductive plugs corresponding to the transistor to be tested; performing a patterning process on the second conductive layer to form a second electrical connection layer, wherein the second electrical connection layer is in contact with all the second conductive plugs corresponding to the transistor to be tested; providing a first test signal to the first electrical connection layer and obtaining a first output signal of the first electrical connection layer, wherein the first test signal is a constant voltage signal; providing a second test signal to the second electrical connection layer and obtaining a second output signal of the second electrical connection layer; providing a third test signal to the gate of the transistor to be tested, wherein the third test signal is a voltage signal; and detecting an electrical property of the transistor to be tested based on the first output signal and the second output signal.

2. The method of claim 1, wherein the step of applying a voltage to the device is performed by applying a voltage to the device while the device is in a vacuum. The electrical property comprises a volt-ampere characteristic curve.

3. The method of claim 1, wherein the step of applying a voltage to the device is performed by applying a voltage to the device while the device is in a vacuum. Before the patterning process is performed on the first conductive layer and the second conductive layer, the method further comprises performing a planarization process on the device until the top surface of the first conductive layer and the top surface of the second conductive layer are exposed.

4. The method of claim 1, wherein the step of applying a voltage to the device is performed by applying a voltage to the device while the device is in a vacuum. The method for providing the first test signal and the second test signal and obtaining the first output signal and the second output signal comprises the following steps: providing a first probe and a second probe, wherein the first test signal is provided through the first probe, and the first output signal is obtained through the second probe; providing a third probe and a fourth probe, wherein the second output signal is obtained through the third probe, and the second test signal is provided through the fourth probe, wherein the first output signal and the second test signal are current signals, and the first test signal and the second output signal are voltage signals.

5. The method of claim 4, wherein the step of applying a voltage to the device is performed by applying a voltage to the device while the device is in a vacuum. The method for providing the first test signal and the second test signal and obtaining the first output signal and the second output signal further comprises the following steps: providing a voltage detection module, wherein the voltage detection module is electrically connected between the first probe and the third probe, and the voltage detection module obtains a source-drain voltage value based on the first test signal and the second output signal; providing a current detection module, wherein the current detection module is electrically connected between the second probe and the fourth probe, and the current detection module obtains a source-drain current value based on the first output signal and the second test signal.

6. The method of claim 1, wherein the step of applying a voltage to the device is performed by applying a voltage to the device while the device is in a vacuum. The method for providing the first test signal and the second test signal and obtaining the first output signal and the second output signal comprises: a source probe is provided, the first test signal is provided through the source probe, and the first output signal is obtained; a drain probe is provided, the second test signal is provided through the drain probe, and the second output signal is obtained, the first test signal and the second test signal are voltage signals, and the first output signal and the second output signal are current signals.

7. The method of claim 6, wherein the step of applying a voltage to the device is performed by applying a voltage to the device while the device is in a vacuum chamber. The method for providing the first test signal and the second test signal and obtaining the first output signal and the second output signal further comprises: a voltage detection module is provided, the voltage detection module is electrically connected between the source probe and the drain probe, and the voltage detection device obtains a source-drain voltage value based on the first test signal and the second test signal; a current detection module is provided, the current detection module is electrically connected between the source probe and the drain probe, and the current detection device obtains a source-drain current value based on the first output signal and the second output signal.

8. The method of claim 5 or 7, wherein the step of applying a voltage to the device is performed by applying a voltage to the device while the device is in a vacuum. Based on the source-drain voltage value and the source-drain current value, a volt-ampere characteristic curve of the transistor to be measured is obtained; when the third test signal corresponding to the voltage provided to the gate of the transistor to be measured is equal to the source-drain voltage value, a saturation current of the transistor to be measured is obtained according to the volt-ampere characteristic curve of the transistor to be measured.

9. The method of claim 1, wherein the device is a semiconductor device. The contact electrical connections between the gates of all the transistors constitute a third conductive layer, and the device further has a third conductive plug in contact with the third conductive layer; The method for providing the third test signal to the gate of the transistor to be measured comprises: a fifth probe is provided, and the third test signal is provided to the third conductive plug through the fifth probe.

10. The method of claim 1, wherein the device is a semiconductor device. The first conductive layer and the second conductive layer are patterned by using a focused ion beam technology.

11. The method of claim 10, wherein the step of applying a voltage to the device is performed by applying a voltage to the device while the device is in a vacuum chamber. The process parameters of the focused ion beam technology include: a voltage of 20 kV to 30 kV and a beam current of 5 nA to 20 nA.

12. The method of claim 1, wherein the device is a semiconductor device. A surface where a source surface of the transistor to be measured is located is a first plane, a normal projection of the first electrical connection layer on the first plane covers a normal projection of all the first conductive plugs corresponding to the transistor to be measured on the first plane; a surface where a drain surface of the transistor to be measured is located is a second plane, and a normal projection of the second electrical connection layer on the second plane covers a normal projection of all the second conductive plugs corresponding to the transistor to be measured on the second plane.

13. The method of claim 1, wherein the device is a semiconductor device. The step of patterning the first conductive layer further comprises: at least one third electrical connection layer is formed, each third electrical connection layer is in contact with only the first conductive plug corresponding to one transistor other than the transistor to be measured.

14. The method of claim 1, wherein the device is a semiconductor device. The step of patterning the second conductive layer further comprises: at least one fourth electrical connection layer is formed, each fourth electrical connection layer is in contact with only the second conductive plug corresponding to one transistor other than the transistor to be measured.

15. A test structure for carrying out the test method according to any one of claims 1 to 14, characterized in that ​ At least two transistors spaced apart from each other, the transistors having a source, a drain and a gate, the transistors further having at least two first conductive plugs in contact with the source and at least two second conductive plugs in contact with the drain, wherein one transistor is a transistor under test; a first electrical connection layer in contact with all the first conductive plugs corresponding to the transistor under test; a second electrical connection layer in contact with all the second conductive plugs corresponding to the transistor under test.

16. The test structure of claim 15, wherein, comprising: a third electrical connection layer in contact with the first conductive plugs corresponding to one transistor other than the transistor under test; a fourth electrical connection layer in contact with the second conductive plugs corresponding to one transistor other than the transistor under test.

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