Integrating resistive memory systems into multi-core CPU dies to enable massive memory parallelism

Abstract

A monolithic integrated circuit (IC) computing device is disclosed having multiple independent processing cores (multicore) and an embedded non-volatile resistive memory acting as system memory. The resistive system memory is fabricated on a substrate and logic circuitry including the processing cores is fabricated on the substrate. In addition, access circuitry for operating on the resistive system memory is disposed at least partially on the substrate, as well as circuitry including a memory controller, routing devices, and other logic components. Large main memory capacities of tens or hundreds of gigabytes (GB) are provided and can operate with multiple processing cores, all located on a single chip. This monolithic integration provides close physical proximity between the processing cores and the main memory, facilitating significant memory parallelism, reducing power consumption, and eliminating off-chip main memory access requests.

Description

[0001] Government licensing rights

[0002] This invention was completed with government support under contract number FA807514D0002 granted by the U.S. Air Force. The government holds certain rights to this invention. Technical Field

[0003] This disclosure generally relates to an integrated circuit that includes an on-chip network computing system, such as a multi-core chip with a large capacity embedded resistive system memory and very high parallelism between the processing core and the embedded system memory. Background Technology

[0004] Resistive memory represents the latest innovation in the field of integrated circuit technology. While most resistive memory technologies are still under development, various technical concepts have been proven by inventors and are undergoing one or more validation phases to demonstrate or refute related theories or technologies. Resistive memory technology is expected to offer a significant advantage over competing technologies in the semiconductor electronics industry.

[0005] Resistive memory cells can be configured to have multiple states with different resistance values. For example, a single-bit cell can be configured to exist in a relatively low resistance state, or alternatively, in a relatively high resistance state. Multiple-bit cells may have additional states with resistance values ​​different from each other and also different from the relatively low and relatively high resistance states. The states of resistive memory cells represent discrete logical information states, facilitating digital storage operations. When combined into arrays of many such memory cells, larger-capacity digital memory storage becomes feasible.

[0006] Resistive memory also shows significant promise in scaling its capabilities to more advanced (e.g., smaller) technology nodes. Partially made of thin films and with a relatively simple geometry compared to some integrated circuit devices, individual resistive memory cells can operate reliably with very small lithographic feature sizes. As feature sizes continue to shrink, the power efficiency and density of resistive memory further improve, enhancing the performance and flexibility of the technology.

[0007] Given the above, the practical development of resistive memory technology continues. Summary of the Invention

[0008] The following is a brief summary of this specification to provide a basic understanding of some aspects of it. This summary is not a comprehensive overview of the specification. It is not intended to identify the main or key elements of the specification, nor to describe the scope of any particular implementation or any claim. Its purpose is to present some concepts of this specification in a simplified form as a prelude to the more detailed descriptions presented in this disclosure.

[0009] This disclosure provides a monolithic integrated circuit (IC) computing device having multiple independent processing cores (multi-core) and an embedded non-volatile resistive memory that acts as system memory or random access memory (RAM). The resistive system memory is fabricated on a substrate, and the logic circuitry containing the processing cores is also fabricated on the substrate. Furthermore, access circuitry for operating on the resistive system memory, as well as circuitry including a memory controller, router devices, and other logic components, are at least partially disposed on the substrate. Because resistive memory is very small and highly scalable to advanced process nodes, large main memory capacities (e.g., hundreds of gigabytes (GB) or greater) can be implemented by many processing cores, all on a single die. This monolithic integration provides close physical proximity between the processing cores and the main memory, facilitating significant parallelism between them. Additional embodiments subdivide large main memory arrays into many subarrays, each independently accessible. Furthermore, the addition of numerous embedded processing cores, each operable to access any independent subarray, achieves massive parallelism between the processing cores and resistive system memory, resulting in extremely high performance in addition to reduced power consumption. This document provides various implementations described above, including alternative or additional features and characteristics.

[0010] In another embodiment, this disclosure provides an integrated circuit device. The integrated circuit device may include a plurality of processing cores formed on a substrate of the integrated circuit device, and a resistive memory array structure formed above the substrate of the integrated circuit device and at least partially covering the plurality of processing cores. The resistive memory array structure may include a plurality of resistive memory subarrays, each resistive memory subarray including non-volatile two-terminal resistive switching memory cells. Furthermore, the integrated circuit may include access circuitry formed at least partially on the substrate of the integrated circuit device, the access circuitry providing independent operative access to respective resistive memory subarrays of the plurality of resistive memory subarrays. In embodiments, the access circuitry may be integrated within logic circuitry that includes the processing cores formed on the substrate of the integrated circuit device. The access circuitry may be integrated into the processing cores in a fine-grained cohesive manner. Furthermore, the integrated circuit may include multiple memory controllers, comprising a first set of memory controllers and a second set of memory controllers. The first set of memory controllers is communicatively coupled to a first processing core among the multiple processing cores and is operable to receive a first memory instruction from the first processing core and execute the first memory instruction on a first set of resistive memory subarrays among the multiple resistive memory subarrays in response to the first memory instruction. The second set of memory controllers is communicatively coupled to a second processing core among the multiple processing cores and is operable to receive a second memory instruction from the second processing core and execute the second memory instruction on a second set of resistive memory subarrays among the multiple resistive memory subarrays in response to the second memory instruction. In one or more embodiments, the first memory instruction or the second memory instruction is a memory read that returns less than 128 bytes of data.

[0011] Additional embodiments of this disclosure provide a method of manufacturing an integrated circuit device. The method may include setting logic circuitry on a substrate of a chip, the logic circuitry including a plurality of processing cores and a cache memory for the processing cores, and access circuitry at least partially on the chip substrate for independent subarrays of resistive system memory. Furthermore, the method may include setting circuitry at least partially on the chip substrate, the circuitry including multiple memory controllers for each of the plurality of processing cores. According to various embodiments, the method may further include forming a non-volatile two-terminal resistive memory device including independent subarrays of resistive system memory overlaying the substrate and overlaying at least a portion of the logic circuitry, access circuitry, or circuitry including multiple memory controllers. Further, the method may include forming an electrical connection between corresponding portions of the access circuitry on the chip substrate and each independent subarray of the resistive system memory overlaying the chip substrate, and forming an electrical connection between the circuitry including each memory controller and corresponding portions of the access circuitry. The method may also include providing a communication path between a logic circuit containing multiple processing cores and a circuit containing multiple memory controllers, and configuring one of the multiple memory controllers to execute memory instructions on an associated independent subarray of the resistive system memory in response to a main memory request from a cache memory originating from the logic circuit.

[0012] In another embodiment of this disclosure, an integrated circuit device is provided. The integrated circuit device may include a plurality of processor tiles, wherein each processor tile includes a processing core, a cache memory and a cache controller, a memory controller, and a multiple data memory instruction set, wherein the plurality of processing tiles are formed on a substrate of the integrated circuit device. The integrated circuit device may also include a resistive memory array structure formed on the substrate of the integrated circuit device, the resistive memory array structure including a plurality of independently addressable subarrays formed of non-volatile double-ended resistive switching memories, wherein a portion of the independently addressable subarrays is managed by the memory controller. Furthermore, the integrated circuit device may include access circuitry at least partially formed on the substrate of the integrated circuit device, the access circuitry interconnecting the memory controller with the memory controller-managed portions of the independently addressable subarrays. In various embodiments, the integrated circuit device may also include command and data buses interconnecting corresponding processor tiles among the plurality of processor tiles, wherein the resistive memory array structure acts as system memory for the processing cores of the processor tiles.

[0013] The following description and accompanying drawings illustrate certain illustrative aspects of this specification. However, these aspects indicate only a few of the various ways in which the principles of this specification can be employed. Other advantages and novel features of this specification will become apparent from the following detailed description when considered in conjunction with the accompanying drawings. Attached Figure Description

[0014] Many aspects, embodiments, objects, and advantages of the invention will become apparent when considered in conjunction with the accompanying drawings, in which like reference numerals refer to like parts throughout. Numerous specific details are set forth in this specification to provide a thorough understanding of this disclosure. However, it should be understood that certain aspects of this disclosure may be practiced without these specific details, or using other methods, components, materials, etc. In other instances, well-known structures and apparatuses are shown in block diagram form to facilitate the description of this disclosure.

[0015] Figure 1 A block diagram illustrating an example monolithic subchip-level computing architecture for an integrated circuit (IC) chip in an embodiment of this disclosure is provided.

[0016] Figure 2 A block diagram of an example circuit layout for a portion of a substrate in a disclosed monolithic computing architecture, according to another embodiment, is shown.

[0017] Figure 3 A simplified perspective view of a monolithic computing device in one or more embodiments is shown, the monolithic computing device having resistive system memory overlaid on a substrate circuit.

[0018] Figure 4 A block diagram depicts an example operational arrangement for memory access in an embedded resistive system memory for a disclosed monolithic computing device.

[0019] Figure 5 A block diagram is shown of an on-chip network architecture for embedded memory access by multiple processing cores of the disclosed IC chip in one or more embodiments.

[0020] Figure 6 A block diagram of an on-chip network architecture for multi-core embedded memory access according to another disclosed embodiment is depicted.

[0021] Figure 7 An example 2D arrangement of a processing core and memory controller device for a monolithic IC computing architecture is shown in one or more of the disclosed aspects.

[0022] Figure 8An example 2D arrangement of the processing core and memory controller device for a monolithic IC computing architecture is depicted in an additional aspect.

[0023] Figure 9 A block diagram of an example parallel memory access architecture for implementing large-scale memory parallelism in an open IC chip is depicted in another aspect.

[0024] Figure 10 A graph depicts the memory parallelism for the Example 64 processor architecture, which features embedded resistive memory for different parallel instruction modes.

[0025] Figure 11 A processing tile having multiple embedded resistive memory clusters monolithically integrated with a processor core is shown in at least one embodiment.

[0026] Figure 12 A flowchart is shown as an example method for manufacturing a monolithic IC chip with embedded resistive memory and high memory parallelism in one or more aspects.

[0027] Figure 13 A flowchart is depicted in one embodiment of an example method for implementing a main memory request in conjunction with a cache process of the disclosed IC chip.

[0028] Figure 14 A flowchart is shown of an example method for manufacturing a monolithic IC chip with embedded resistive memory, according to another disclosed embodiment.

[0029] Figure 15 A block diagram of an example electronic operating environment according to certain embodiments of this disclosure is shown. Detailed Implementation

[0030] introduction

[0031] This disclosure relates to a monolithic integrated circuit (IC) device having multiple processing cores and an embedded non-volatile resistive memory serving as main memory (or random access memory (RAM)) for the multiple processing cores. The use of non-volatile main memory facilitates applications that do not require a continuous external power supply, as the threat of data loss is avoided or greatly mitigated. Furthermore, highly scalable resistive-switched dual-ended memory cells (also known as resistive-switched memory cells, resistive memory cells, or resistive memory) can provide very high system memory capacities, such as tens or hundreds of gigabits (Gb) or more, far exceeding the capacity of embedded dynamic random access memory (DRAM). To achieve data throughput approaching or exceeding that of modern DRAM memory between the processing cores and system memory, high parallelism between the processing cores and the embedded resistive system memory is provided. High parallelism can be achieved through various mechanisms, including a large number of processing cores, a very large number of independently operable resistive memory subarrays, an embedded memory controller serving each processing core, and multi-threaded, multiple-data, and non-blocking multiple-data memory instruction sets, etc. In at least some exemplary embodiments, but by no means limited to these examples, a 20mm x 20mm IC chip based on 16-nanometer (nm) process technology is provided, having at least 64 processing cores in a single two-dimensional (2D) cross array, more than 32GB of non-volatile system memory, arranged in more than 8,000 independently operable memory subarrays, each subarray having 2048 x 2048 cells. In this embodiment, stacking two of these 2D cross arrays implements 64GB of non-volatile system memory and more than 16,000 independent subarrays. Similarly, stacking eight 2D cross arrays implements 256GB of non-volatile system memory and more than 64,000 independent subarrays. Furthermore, utilizing the extremely high wiring density obtained through very large-scale integration (VLSI) semiconductor manufacturing technology, high data throughput between multiple cores and system memory can be achieved, supporting thousands or tens of thousands of concurrent memory requests. Other examples within the scope of this disclosure include other process technologies (e.g., 14nm process technology, 12nm process technology, 7nm process technology, etc.), which enable even larger memory capacities, individually accessible subarrays, the number of cells per subarray, or the like, or combinations thereof. Furthermore, additional or alternative features of monolithic memory chips with multi-core processors and embedded resistive memory, known in the art or to those skilled in the art through the context provided herein, are considered to be within the scope of this disclosure.

[0032] As used herein, the term "processing core" refers to any suitable analog or digital instruction and data execution device that can be included within an integrated circuit chip. Suitable examples of processing cores include general-purpose devices such as a central processing unit (CPU). Other suitable examples include special-purpose devices such as accelerators. Examples include graphics processing units (GPUs), digital signal processors (DSPs), physical processing units (PPUs), special-purpose instruction set processors (ASIPs), network processors, image processors, etc. Other examples known in the art or that are known to those skilled in the art through the context provided herein are considered to be within the scope of this disclosure.

[0033] In one or more additional embodiments, the multi-core processor tiles of the disclosed monolithic IC computing chip can utilize the access capability of subpage sizes of memory subarrays with dual-ended resistor switching. For other memory technologies, such as DRAM or FLASH memory, the minimum memory that each memory request can access is one page (e.g., an entire row of data in an array or subarray). If a memory request only needs to save a portion of the data to a page, irrelevant data is returned, thus reducing the throughput of useful data. As used herein, the term "useful data throughput" refers to the ratio of desired or target data transferred between main memory and a set of processing cores to the total amount of data transferred (including irrelevant data). By enabling memory access requests with subpage sizes, finer-grained data access can be achieved. For example, in some cases (e.g., 1 byte, 2 bytes, 4 bytes, etc.), the fetch size can be similar to or equal to the size of the useful data, or only moderately larger. This results in higher useful data throughput between the processing cores and system memory. Therefore, the disclosed embodiments can minimize or avoid data redundancy, further reduce power consumption, and maximize useful data throughput.

[0034] In the various embodiments disclosed herein, variable access granularity can be implemented. In such embodiments, the disclosed processing core (or cache controller) can specify a non-fixed data fetch size. Conventional memory is limited to fetching large contiguous blocks of data (e.g., 128 bytes for many DRAM main memory systems) on each main memory access. This is efficient for programs exhibiting good space multiplexing, promoting high memory bandwidth. However, for programs with low space multiplexing, fetching large blocks of data results in lower useful data throughput because most of the data returned by each memory request is ignored or wasted. Resistive memory can support multiple fetch sizes and can support variable fetch sizes that change with each memory request. As a result, the disclosed computing architecture incorporates dynamic fetch size requests into resistive main memory, which can be dynamically configured to match the space multiplexing of the target memory observed at runtime.

[0035] According to one or more additional embodiments, the disclosed monolithic computing chip can be fabricated partially or entirely using complementary metal-oxide-semiconductor (CMOS) manufacturing processes. This enables processing logic circuitry, cache and cache controller circuitry, routing device circuitry, memory controller circuitry, and high-capacity embedded resistive memory arrays to be fabricated through a series of CMOS logic processing steps to form a complete computing architecture on a single IC chip. In one or more embodiments, this includes multiple processing cores, command and data routing devices, and integrated command and data paths between the processing cores and routing devices, resulting in an on-chip network architecture including very high-capacity resistive system memory. This represents a significant advancement in system-on-chip devices compared to the prior art.

[0036] Various resistive memory technologies and their features, applicable to various implementations, are considered to be within the scope of this disclosure. As used herein, a resistive-switched memory cell can be a two-terminal memory device comprising circuitry having conductive contacts (e.g., electrodes or terminals) and an active region between two conductive contacts. In the context of resistive-switched memory, the active region of a two-terminal memory device exhibits multiple stable or semi-stable resistive states, each with a different resistance. Furthermore, in response to an appropriate electrical signal applied to the two conductive contacts, a corresponding state among the multiple states can be formed or activated. The appropriate electrical signal can be a voltage value, a current value, a voltage or current polarity or the like, or a suitable combination thereof. Examples of, but not exhaustive, resistive-switched two-terminal memory devices may include resistive random access memory (ReRAM), phase-change RAM (PCRAM), conductive bridged RAM (CB-RAM), and magnetic RAM (MRAM).

[0037] An example of resistive memory is the filamentary resistive memory cell. Generally, the composition of a filamentary resistive memory cell can vary depending on the device, with different components selected to achieve the desired characteristics (e.g., volatile / non-volatile resistive switching, on / off current ratio, switching time, read time, memory endurance, programming / erase cycle, etc.). An example of a filamentary resistive memory cell may include: a conductive layer, such as a metal, a metal alloy (including, for example, metal-metal alloys such as TiW, and various suitable metal-nonmetal alloys), a metal-nitride (e.g., including TiN, TaN, or other suitable metal-nitride compounds); an optional interface layer (e.g., a doped p-type (or n-type) silicon (Si) carrier layer, such as a p-type or n-type Si carrier layer, p-type or n-type polycrystalline silicon, p-type or n-type polycrystalline SiGe, etc.); a resistor-switching layer (RSL, also known as an active layer, resistor-switching dielectric (RSM), etc.); and an active metallized layer capable of being ionized. Under suitable conditions, the active metallized layer can provide filament-forming ions to the RSL. In such embodiments, the conductive filaments (e.g., formed by ions) can promote conductivity through at least a subset of the RSL, and as an example, the resistance of the filament-based device can be determined by the tunneling resistance between the filaments and the conductive layer.

[0038] RSL may include, for example, an undoped amorphous Si-containing layer, a semiconductor layer with intrinsic properties, or silicon nitride (e.g., SiN, Si3N4, SiN...). x etc., where x is a positive number), silicon suboxide (e.g., SiO2). x (where x is between 0.1 and 2), silicon subnitride, metal oxides, metal nitrides, non-stoichiometric silicon compounds, silicon and nitrogen-containing materials, metal and nitrogen-containing materials, etc. Other examples of amorphous and / or non-stoichiometric materials suitable for RSL may include Si. X Ge Y O Z (where X, Y, and Z are the corresponding appropriate positive numbers), silicon dioxide (e.g., SiO2). N (where N is a suitable positive number), silicon oxynitride, undoped amorphous silicon (a-Si), amorphous SiGe (a-SiGe), TaO B (where B is a suitable positive number), HfO C (where C is a suitable positive number), TiO D (where D is a suitable number), Al2O E (where E is a suitable positive number), other suitable oxides, nitrides (e.g., AlN, SiN), or suitable combinations thereof (e.g., see below).

[0039] In some embodiments, an RSL used as part of a non-volatile memory device (non-volatile RSL) may include a relatively large number (e.g., compared to a volatile selector device) of material voids or defects to trap neutral metal particles within the RSL (e.g., at relatively low voltages, such as <~3 volts). A large number of voids or defects can facilitate the formation of a thick, stable structure of neutral metal particles. In such a structure, these trapped particles can maintain the non-volatile memory device in a low-resistance state without external stimuli (e.g., electricity), thereby enabling non-volatile operation. In other embodiments, an RSL for a volatile selector device (volatile RSL) may have very few material voids or defects. Due to the scarcity of voids / defects trapping the particles, the conductive filaments formed in such an RSL may be very thin and unstable without appropriately high external stimuli (e.g., electric fields, voltages greater than about 0.5 volts, 1 volt, 1.5 volts, etc., currents, Joule heating, or suitable combinations thereof). Furthermore, the particles can be selected to have high surface energy and good diffusivity within the RSL. This allows the conductive filament to form rapidly in response to appropriate stimuli, but it is also easily deformable, for example, in response to external stimuli that decrease below the deformation threshold. Note that a volatile RSL and conductive filament for a selector device can have different electrical properties than the conductive filament and non-volatile RSL used in a non-volatile memory device. For example, the selector device RSL can have a higher material resistance and a higher on / off current ratio, etc.

[0040] Active metal-containing layers for filament-based memory cells may include the following: silver (Ag), gold (Au), titanium (Ti), titanium nitride (TiN) or other suitable titanium compounds, nickel (Ni), copper (Cu), aluminum (Al), chromium (Cr), tantalum (Ta), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), hafnium (Hf), and palladium (Pd). In some aspects of this disclosure, other suitable conductive materials and combinations of compounds, oxides, nitrides, alloys, or the foregoing or similar materials may be used in the active metal-containing layer. Furthermore, in at least one embodiment, non-stoichiometric compounds, such as non-stoichiometric metal oxides or metal nitrides (e.g., AlO2), are used. x AlN x CuO x CuN x AgO x AgN x (e.g., where x is a suitable positive number 0 < x < 2, which can have different values ​​for different non-stoichiometric compounds) or other suitable metal compounds, can be used for active metal-containing layers.

[0041] In some embodiments, the disclosed filamentary resistive switching device may include an active metal layer comprising a metal nitride selected from the group consisting of TiN. x TaN x AlN x CuN x WN x and AgN x , where x is a positive number. In another embodiment, the active metal layer may include a metal oxide selected from the group consisting of: TiO2 x TaO x AlO x CuO x WO x and AgO x In one or more embodiments, the active metal layer may comprise a metal nitride selected from the group consisting of: TiO2 a N b AlO a N b CuO a N b WO a N b and AgO a N b Where a and b are positive numbers. The disclosed filamentary resistive switching device may further include a switching layer comprising a switching material selected from the group consisting of: SiO y AlN y TiO y TaO y AlO y CuO y TiN x TiN y TaN x TaN y SiO x SiN y AlN x CuN x CuN y AgN x AgN y TiO x TaO x AlO x CuO x AgO x and AgO y Where x and y are positive numbers, and y is greater than x. The various combinations described above are contemplated and considered to be within the scope of embodiments of the present invention.

[0042] In one example, the disclosed filamentary resistive switching device includes a particle donor layer (e.g., an active metal-containing layer) comprising a metal compound and a resistive switching layer. In an alternative embodiment of this example, the particle donor layer comprises a metal nitride: MN x For example, AgN x TiN x AlN x The resistive switching layer includes metal nitrides: MN y For example, AgO y TiO y AlO y And so on, where y and x are positive numbers, and in some cases y is greater than x. In an alternative implementation of this example, the particle donor layer comprises a metal oxide: MO x For example, AgO x TiO x AlO x The resistive switching layer includes metal oxides: MO y For example, AgO y TiO y AlO y And so on, where y and x are positive numbers, and in some cases y is greater than x. In another choice, the metal compound of the particle donor layer is MN. x (e.g. AgN) x TiN x AlN x (etc.), and resistive switching layer selection is free for MO. y (For example, AgO) x TiO x AlO x (etc.) and SiO y The group consisting of the comparative atomic weights x and y can be suitable stoichiometric or non-stoichiometric values ​​in this disclosure. As used herein, variables x, a, b, etc., representing the value or ratio of one element relative to another (or other) element in a compound may have different values ​​applicable to the respective compound and are not intended to represent the same or similar values ​​or ratios in the compound.

[0043] As described above, applying a programming voltage (also known as a “programming pulse”) to one of the electrodes of a dual-terminal memory can cause the formation of a conductive filament (e.g., RSL) in the interface layer. Conventionally, and as generally stated herein, the TE receives the programming pulse and the BE is grounded (or held at a lower voltage or opposite polarity than the programming pulse), but this is not intended to limit all implementations. Conversely, applying an “erase pulse” to one of the electrodes (typically a pulse with the opposite polarity to the programming pulse or applied as a programming pulse to the opposite electrode) can disrupt the continuity of the filament, for example, by driving metal particles or other materials forming the filament back to the active metal source of a non-volatile filamentary device. For volatile filamentary devices, reducing the voltage below the activation threshold voltage (or, in some implementations, a holding voltage) can cause the metal particles to disperse, forming a volatile filament, resulting in discontinuities in the volatile filament. The characteristics of this conductive filament and its presence or absence affect the electrical characteristics of the dual-terminal memory cell, for example, reducing the resistance between the terminals and / or increasing the conductance between the terminals when the conductive filament is present, contrary to the case when the conductive filament is absent.

[0044] Following a programming or erasing pulse, a read pulse is almost certain. The amplitude of this read pulse is typically lower than that of the programming or erasing pulse and is usually insufficient to affect the conductive filament and / or alter the state of a two-terminal (non-volatile) memory cell. By applying a read pulse to one of the electrodes of the two-terminal memory, the measured current (e.g., I0) is... on This can indicate the conductivity state of a dual-ended memory cell. For example, when a conductive filament has been formed (e.g., in response to the application of a programming pulse), the cell's conductivity is greater than in other cases, and the measured current (e.g., I) in response to a read pulse... on The reading will be larger. On the other hand, when the conductive filament is removed (e.g., in response to the application of an erase pulse), the cell resistance is higher due to the relatively high resistance of the interface layer, resulting in lower cell conductance and a lower measurement current (e.g., I) in response to the read pulse. off The reading will be smaller.

[0045] Conventionally, when a conductive filament is formed, a memory cell is referred to as being in a "conducting state" with high conductivity. When the conductive filament is absent, the memory cell is referred to as being in a "turn-off state." Non-volatile memory cells in either the conducting or turning-off states can be logically mapped to binary values, such as, for example, "1" and "0." It should be understood that the conventions used herein associated with the states of cells or with the associated logical binary mappings are not intended to be limiting, as other conventions, including the opposite conventions, can be used in conjunction with the disclosed subject matter. The techniques detailed herein are described and illustrated in conjunction with single-level cell (SLC) memory, but it should be understood that the disclosed techniques can also be used with multi-level cell (MLC) memory, in which a single memory cell can retain a set of measurably distinct states representing multiple bits of information. In embodiments of this disclosure, by merging MLC memory cells instead of SLC memory, the capacity of the disclosed memory array can be increased proportionally to the number of bits per MLC memory cell (e.g., a two-bit MLC cell can double the disclosed memory capacity, a four-bit MLC cell can quadruple the disclosed memory capacity, and so on).

[0046] As used herein, resistive memory structures can be formed as two-dimensional (2D) arrays between intersecting wires of an IC chip, such as between back-end-of-line wires (e.g., metals, metal alloys / compounds, doped semiconductors, etc.). Stacking multiple 2D arrays can affect a three-dimensional (3D) array called a 3D cross array. In a 3D cross array, a double-ended memory cell is formed at the intersection of two metal lines within each 2D array, and multiple such 2D arrays stacked on top of each other form a 3D cross structure. Two general conventions are provided for the arrangement of memory cells in 2D or 3D arrays. The first convention is a 1T1R memory array, in which each memory cell is isolated from the electrical effects of the surrounding circuitry (e.g., current, including leakage path current) by an associated transistor. The second convention is a 1TnR memory array (where n is a positive number greater than 1), in which a subarray of multiple memory cells (e.g., 2K*2K cells, or other suitable array size) is isolated from the electrical effects of the surrounding circuitry and the subarray by a single transistor (or group of transistors). In a 1TnR configuration, each memory cell may include a selector device (e.g., a volatile two-terminal wire resistor) electrically connected in series with a two-terminal non-volatile memory cell between intersecting wires in a cross array. This selector device has a very high turn-off resistance and can significantly suppress current leakage between the wires when the applied voltage through the wires is lower than the activation amplitude of the selector device. Because two-terminal memory cells can be fabricated in thin films much smaller than transistors and can be highly scalable, 1TnR arrays with large n values ​​can achieve very high storage densities.

[0047] Example monolithic computing architecture

[0048] Various aspects or features of this disclosure are described with reference to the accompanying drawings, wherein the same reference numerals are always used to refer to the same elements. Numerous specific details are set forth in this specification to provide a thorough understanding of this disclosure. However, it should be understood that certain aspects of the disclosure may be practiced without these specific details, or by utilizing other methods, components, materials, etc. In other examples, well-known structures and apparatuses are shown in block diagram form to facilitate the description of this disclosure.

[0049] Figure 1 A block diagram of an example monolithic subchip-level computing architecture 100 according to one or more embodiments of the present disclosure is shown. In some embodiments, the computing architecture 100 may form part of a monolithic on-chip network architecture. In particular, the computing architecture 100 may include a plurality of processor tiles 104. NMMultiple processor tiles are connected to X resistive memory subarrays 130 serving the non-volatile system memory (e.g., random access memory, or RAM) of the multiple processor tiles. The resistive memory subarrays 130 utilize the high density and scalability of dual-ended resistive memory technology (e.g., resistive switching, dual-ended memory, also known as resistive random access memory, or ReRAM) to achieve large storage capacity of embedded non-volatile system memory. Due to the non-volatility of the system memory, reduced power consumption and simplified power maintenance circuitry can be implemented for the computing architecture 100. Furthermore, small or self-limiting memory access requests can maximize the useful data throughput of the computing architecture 100. Further, by implementing massive memory parallelism, total data throughput approaching or even exceeding that of modern DRAM memory systems can be achieved through various disclosed embodiments, resulting in significant improvements to embedded system-on-chip (or network-on-chip) architectures through this disclosure.

[0050] As shown in the figure, the computing architecture 100 may include a substrate layer 110, which includes logic circuits and other active device circuits, including multiple processor tiles 104. NM Where N and M are suitable positive integers. In one embodiment, substrate layer 110 includes N*M processor tiles. In a particular embodiment, N*M includes a number selected from the group consisting of: 64 processor tiles, 128 processor tiles, 256 processor tiles, and 512 processor tiles. In other embodiments, substrate layer 110 may include other numbers of processor tiles (e.g., 8, 16, or 32 processor tiles, 1024 processor tiles, 2048 processor tiles, or other suitable numbers).

[0051] Above the substrate layer 110 are multiple back-end layers 115. The back-end layers 115 are located above the substrate layer 110 and can be wholly or partially connected to the processor tile 104. NM Overlap. Not depicted in computing architecture 100 (but see, for example, Figure 2 and Figure 3 (e.g., see below) are memory access circuitry for electrically accessing the back-end layer 115, including resistive memory (ReMEM) cells fabricated between the back-end layers 115. The memory access circuitry may include row and column control, sensing arrays, voltage and current control circuitry, multiplexers, clock sources, etc. (see below for example). Figure 4 and Figure 14 The back-end layer may partially or completely cover the memory access circuitry and other active or passive components formed in the substrate layer 110.

[0052] Processor tile 104 formed on substrate layer 110 NMIt can be formed using CMOS manufacturing processes. Furthermore, the memory access circuitry for accessing and controlling the ReMEM memory bank 130 can also be formed using CMOS manufacturing processes. For example, the logic and access circuitry can be formed entirely or at least partially using front-end-of-line CMOS processes. Additionally, the ReMEM memory bank 130 can also be formed using CMOS processes, at least partially including back-end CMOS processes. This facilitates the integration of a single monolithic chip, including the substrate layer 110 and the back-end layer 115, into a single die or wafer (e.g., a 20mm x 20mm chip, or other suitable-sized chip).

[0053] Example component diagrams for each processor tile 104 are shown by processor tile 120. Processor tile 120 may include a processing core (or multiple cores) 122, including logic circuitry formed on substrate layer 110. Additionally, for example, a cache memory and cache controller 124 may be provided for cached data associated with one or more process threads executed by processing core 122, retrieving cached data in response to a cache hit, or issuing memory requests to one or more of X ReMEM memory banks 130 in response to a cache miss, where X is a suitable positive integer. Memory access circuitry may be within processor tile 120 (or adjacent to processor tile 120 in some embodiments), providing electrical connections and control components to enable independent access to each of the X ReMEM memory banks 130.

[0054] As shown, processor tile 120 may include one or more memory controllers 125 to facilitate the execution of memory operations on ReMEM memory bank 130 connected to processor tile 120. Memory controllers 125 may be configured to operate in conjunction with the physical requirements of the resistive memory cells forming ReMEM memory bank 130. Example configurations include read latency configuration, write latency configuration, overlay configuration, power control for activating / deactivating a subset of ReMEM memory bank 130 or for activating one or more bits or bytes of memory included in ReMEM memory bank 130, address decoding for identifying the physical location of memory cells identified by a memory request, error correction coding and instructions, data verification instructions for verifying correct read or write results, and so on. In some embodiments, processor tile 120 includes multiple memory controllers 125 per processor core 122. As an example, processor tile 120 may include three memory controllers per processor core (e.g., see below). Figure 7 As an alternative example, processor tile 120 may include eight memory controllers per processor core (see below for example). Figure 8In other implementations, a suitable number of memory controllers may be provided for each processor core 122.

[0055] The memory controller 125 can also operate with a stored multiple-data instruction set 126. The multiple-data instruction set can provide instructions and rules for issuing multiple concurrent memory requests to the processor core 122 (or per processor core 122, or in the case of multiple cores per tile). One example includes a multi-threaded instruction set for each thread executing on the processor core 122 to issue at least one memory request to system memory (e.g., ReMEM memory bank 130). According to this example, the processor core 122 is capable of concurrently executing n threads, where n is a suitable positive integer (e.g., 4 threads, or other suitable number). Another example of a multiple-data instruction set includes single-instruction multiple-data (SIMD) instructions. This type of multiple-data instruction set refers to instructions (single instructions) that are implemented concurrently on multiple processing cores or within multiple process threads, utilizing different datasets (multiple data). Scatter-gather is an example of SIMD instructions that can be incorporated into a multiple-data instruction set and can operate with the memory controller 125. In general, SIMD instructions can be described as vector instructions, which are extensions of ordinary scalar instruction sets. Spread-aggregate refers to the following SIMD instructions, which can perform multiple memory operations (e.g., to different physical memory access locations) within a given instruction, allowing multiple reads or writes from the same SIMD instruction at non-contiguous memory addresses. For y memory operations, also known as y-way spread-aggregate (e.g., 8-way spread-aggregate, or other suitable integers), y*n physical location accesses can be issued concurrently by the memory controller 125 of each processor core 122. As another example, the Multiple Data Instruction Set 126 may include non-blocking spread-aggregate SIMD instructions, wherein multiple non-blocking memory requests for each process thread of processor core 122 (or cache controller 124) are organized sequentially by the controller memory 125. Non-blocking memory requests are memory requests that can be completed or otherwise executed independently of other memory requests, and therefore can be issued concurrently by processor core 122 (or cache controller 124) without halting activity on processor core 122. Multiple non-blocking memory requests, such as z memory requests, can be organized by memory controller 125 to be issued concurrently for every n process threads, each thread having a defined y physical location access. This can result in z*y*n concurrent physical memory accesses per processor core 122, thereby achieving large-scale memory parallelism between processor core 122 and the resistive system memory of computing architecture 100. In one or more embodiments, memory controller 125 can be configured to sequentially stack 8-depth non-blocking memory requests and make requests to 8*y subarrays of the resistive system memory (e.g., each subarray is a subset of ReMEM memory bank 130, see...). Figure 2 Although included in connecting to other processor tiles 104 NM (and subarrays within the memory storage body of the associated memory controller). As an illustrative and non-limiting example, with the multiple data instruction set 126 configured for 8-depth non-blocking organization, 8-way scatter-aggregate instructions, and 4 threads per core, the memory controller 125 can concurrently issue 8*8*4 or 256 memory requests per processor core 122 (or per cache controller 124). However, this example is by no means limiting, and other suitable values ​​of n process threads, y-way scatter-aggregate implementation, and z-non-blocking request organization can be implemented by computing architecture 100 and other computing architectures of the on-chip network system disclosed herein.

[0056] To facilitate access to tiles 104 connected to different processors NM The system memory of the processor tile 120 may include a router device 128. The router device 128 may be configured to provide information to other processor tiles 104. NM Distribute commands and data, as well as from other processor tiles 104 NM Receives commands and data. As an operational example, processor core 122 (or cache controller 124) connects to processor tile 104. 01 When decoding the memory address associated with ReMEM memory bank 130 (e.g., in response to a cache miss or other request from processor core 122), the processor tile 104 can be accessed. 01 The router device 128, located on this processor tile, will receive the memory commands (e.g., read, write, overwrite, etc.) and provide them to the processor tile 104. 01 The associated memory controller 125. Acknowledgments or data associated with memory requests can be sent by processor tile 104. 01 The router device 128 returns to the processor core 122 (or cache controller 124) of the processor tile 120. As a result, as an example implementation, the processor core 122 / cache controller 124 of the processor tile 120 can access not only the X ReMEM memory banks 130 connected to the processor tile 120, but also any ReMEM memory banks included within the computing architecture 100.

[0057] Each memory cell of the ReMEM memory bank 130 may include a series combination of a volatile resistor-switched selector device and a non-volatile resistor-switched memory cell. As a result, each ReMEM memory bank 130 may be embodied by multiple 1TnR subarrays. In one embodiment, n = 2048 * 2048 memory cells, although other sizes of 1TnR subarrays may be provided in various embodiments of the disclosed computing architecture. In alternative embodiments, the subarrays may be accessed by a set of multiple transistors. In these embodiments, instead of 1TnR, the subarrays may be 2TnR, 4TnR, or other suitable numbers.

[0058] Figure 2 The above is shown Figure 1 A block diagram of an example circuit layout for the independent subarray 240 of the ReMEM memory bank 130. Figure 2 In this implementation, the ReMEM memory bank 130 is managed by a memory bank controller 230. The memory bank controller 230 can activate up to L independently activatable subarrays 240 of the ReMEM memory bank 130. For example... Figure 2 As shown, the ReMEM memory bank 130 includes eight independently activatable subarrays 240, although in various embodiments the ReMEM memory bank 130 can be organized into other numbers of subarrays (e.g., 2 subarrays, 4 subarrays, 16 subarrays, 32 subarrays, etc.). Therefore, the number L of independently activatable subarrays... act It can vary according to one or more implementations, and in at least one implementation it can be dynamically determined, for example, in response to a read / write request, such as a request size attribute.

[0059] Access circuitry 210 is provided for each subarray 240. Access circuitry 210 is partially or wholly formed on the substrate (e.g., the one described above). Figure 1 Within the substrate layer 110, resistive memory cells associated with the subarray 240 are formed above the substrate (e.g., between back-end layers). Adjacent to the access circuitry 210, also formed in the substrate, is logic circuitry 220, which forms the processor core 122 of the processor tile 120. Figure 2 The access circuit 210 and processor circuit 220 configured therein are arranged within the coverage area of ​​the resistive memory subarray 240 on the substrate of the IC chip (see below for example). Figure 3 This allows for a compact architecture design, maximizing the number of processor cores, ReMEM memory bank 130, and resistive memory subarray 240. The proximity of the processor cores to the ReMEM memory bank 130 also reduces power consumption and maximizes efficiency associated with main memory access.

[0060] In at least one embodiment, the ReMEM memory bank 130 can be replicated on the IC die and above the IC die's substrate. Given a specific die size and subarray size, a given number N can be formed on the chip. sa The resistive memory subarray 240. Similarly, based on the area consumed by the access circuitry 210 and the processor circuitry 220, N can be formed on the chip. core One processor core.

[0061] In operation, a given main memory access (e.g., access to ReMEM memory bank 130) causes the memory bank controller 230 to activate an amount equal to L. act The system comprises several resistive memory subarrays 240. A memory controller 230 retrieves a number of bits from each active subarray 240, aggregates them, and subsequently returns the retrieved bits in response to a main memory access. The number of bits retrieved from each subarray is x L. act (Number of activated subarrays) = Extraction size of a given memory bank. The number of bits retrieved by each subarray can be configured during the fabrication of the disclosed computing architecture or can be selectively programmed in post-fabrication configuration. Unlike DRAM, resistive memory in a cross-array is decoupled from the page size of the cross-array. In other words, the granularity of data entering and leaving a subarray is independent of the subarray page size. Specifically, any number of memory cells can be activated individually by applying an appropriate voltage to selected cross-point cells of interest (e.g., up to a number of memory cells that can be activated by the maximum word line current that can be connected to the page). Even if a larger page size is chosen (e.g., to better amortize the substrate area consumed by the access circuitry), the extraction size of the page can be as small as 1 bit, or as large as the size that the maximum word line current can support, or any suitable number in between (e.g., 2 bits, 4 bits, 8 bits, etc.), and in some embodiments can be dynamically configured post-fabrication.

[0062] As mentioned above, a set equals L act The subarrays form a single ReMEM memory bank 130. In some embodiments, the memory bank controller 230 can be configured to change L for each memory request. act This changes the fetch size of a given ReMEM memory bank 130. For example, with the subarray fetch size set to 1 byte, the memory bank controller 230 can fetch a total of 4 bytes for a given memory transaction by activating and executing subarray fetches on four (4) subarrays 240. In other embodiments, for each memory bank controller 230, L act It is fixed, therefore the minimum memory request granularity is determined by the subarray extraction size x L. act Multiples of. In these later implementations, for such Figure 2 L shown act The minimum fetch size will be 8 x subarray fetch (e.g., 8 bytes for a 1-byte subarray fetch, 4 bytes for a 4-bit subarray fetch, and so on). Larger memory requests can be achieved by activating multiple ReMEM banks 130. As another example, to access a standard 64-byte cache block, 64 subarrays within 8 different ReMEM banks 130 (where the subarray fetch size is 1 byte) can be activated to retrieve 64 bytes of data. In these embodiments, the disclosed computing architecture can dynamically change the total fetch size for a given memory transaction by configuring the bank controller 230 to activate an appropriate number of subarrays 240 in response to a memory transaction.

[0063] With one controller 230 per memory bank, the maximum number of unprocessed memory requests at any given time (equal to the number of ReMEM memory banks 130) is N. sa / N act Different implementations of this disclosure can have different amounts of memory parallelism. The total main memory includes ~2,000 (K) x ~2,000 subarrays per 2D cross layer (or more precisely, 2048 x 2048 subarrays in a specific example) and 400 mm². 2 die In the implementation method, the number of subarrays N sa It could be ~64K subarrays. For example, in L... act In the implementation with an equal number of 8, the disclosed computing architecture can support up to ~8K of unfinished concurrent main memory requests across IC chips.

[0064] The maximum chip-wide memory parallelism is achieved when all memory requests use the minimum fetch size. If the amount of data fetched by each memory request exceeds the minimum data size, the resistive memory bank available for individual memory requests is actually smaller. However, the maximum amount of memory parallelism for smaller fetch sizes is useful, for example, for memory-intensive applications with irregular memory access patterns that lack spatial multiplexing. Many applications, including graphics computing and sparse matrix workloads, exhibit these characteristics and can maximize the parallelism of the disclosed computational architecture.

[0065] Figure 3A perspective view of an example resistive memory subarray 300 of the disclosed monolithic computing architecture according to alternative or additional embodiments of this disclosure is shown. Subarray 300 includes a substrate 310 layer located at the base of the IC die, and one or more layers 315 (e.g., back-end layers) above substrate 310. An example layout of logic circuitry and memory access circuitry is shown within and beneath the coverage area of ​​the resistive memory subarray 320 of the resistive main memory. This example layout provides a memory access decoder 330 along a first edge of substrate 310 and a memory access sense amplifier 340 along a second edge of substrate 310 perpendicular to the first edge. The remaining area of ​​substrate 310 includes non-memory circuitry 350, which may include logic circuitry, memory controller circuitry, router device circuitry, cache memory and cache controller circuitry, power control circuitry, multiplexers for routing power, connectors for routing data or instructions, and other suitable active or passive logic devices for processor devices (e.g., processing cores). It should be understood that such a processor device, also referred to herein as a processing core, may include general-purpose processors such as central processing units (CPUs), or dedicated processors such as accelerators (e.g., graphics processing units (GPUs), or any other suitable CMOS processing architecture.

[0066] exist Figure 3In the depicted arrangement, a set of access circuitry is provided for the resistive memory subarray 300 (and, implicitly, other resistive memory subarrays adjacent to the resistive memory subarray 300 within the disclosed monolithic computing architecture). Therefore, the amortization of the access circuitry is maximized when the subarray size is large, resulting in a larger area for integrating CPU logic. For example, for a subarray containing ~2K x ~2K memory cells, assuming a 16nm technology node for resistive memory, one embodiment utilizes approximately 26% of the area beneath the subarray for access circuitry (e.g., including the access decoder 330 plus the sense amplifier 340), leaving 74% of the area for non-memory circuitry 350. The different amortization of the substrate area is achieved through the access circuitry and the processing circuitry when using different process technologies (e.g., 14nm, 12nm, 7nm, etc., or even larger process technologies in some embodiments: 22nm, 28nm, etc.). Generally, by implementing logic circuitry under a set of memory subarrays, all within a single IC die (e.g., utilizing a fine mesh integration of logic and access circuitry), the distance between the processor core and main memory can be minimized, and a large number of wires (e.g., hundreds of thousands or millions of wires, as available in modern VLSI manufacturing, but potentially including even larger numbers available in future semiconductor manufacturing technologies) can be provided to interconnect the processor core and main memory. The high degree of interconnection between the processing cores (e.g., 64 or more processing cores) and independently accessible memory banks (e.g., 8K or more independent subarrays per 2D cross-structure) facilitates very high processor-to-main-memory interconnection and thus extremely high memory access parallelism. The physical proximity between the non-memory circuitry 350 and the resistive memory subarray 320 can significantly reduce power consumption associated with main memory access requests.

[0067] One difference between the disclosed resistive switching memory and, for example, DRAM is that resistive switching memory has a longer read latency (and write latency). For example, read latency on the order of hundreds of nanoseconds has been observed in some resistive memory technologies. To achieve similar or greater main memory throughput as available in DRAM systems, high parallelism is provided—a very large number of memory access requests can be issued per clock cycle (or a set of clock cycles) that can be executed concurrently by a corresponding large number of memory banks—to achieve high throughput despite the longer latency. Furthermore, very large data paths (e.g., 256 bits or more) can be represented by large interconnects between the processing cores and memory banks. In some implementations, the disclosed computing architecture can achieve 23.4 GTEPS with 16K-way memory parallelism, compared to 2.5 gigaflops per second (GTEPS) of a DRAM system with a total data throughput of 320 GB / s. Moreover, better access granularity (e.g., 8 bytes, 4 bytes, 1 byte, etc.) can facilitate higher usable data throughput compared to DRAM, which retrieves data in minimum 128-byte blocks per memory access.

[0068] Table 1 provides example implementations of the disclosed monolithic computing architecture, but this disclosure is not limited to these implementations. One advantage of the disclosed monolithic computing architecture is the scalability of its components. For example, as the number of processor tiles 120 is increased, the core count increases and the number of memory controllers 125 also increases, thereby providing more access points to the ReMEM subarray 130. Typically, for a given chip design, the number of subarrays N... sa Keep it fixed. Therefore, increasing the number of processor tiles 120 also reduces the number of resistive memory subarrays controlled by each memory controller 125. As provided in Table 1, the number of resistive memory subarrays and resistive memory cells per processor tile 120 is given for increasing the number of processor tiles 120: from 64 to 1024 processor tiles 120 (e.g., for N...). sa =64K and L act =8 or one or more implementations; see above Figure 2 Similarly, increasing the number of processor tiles 120 increases the number of router devices 128, thereby providing greater network capacity for routing memory request packets between the cores and memory controllers 125. In other words, expanding the number of processor tiles 120 increases the parallelism of both the computing architecture and the memory controllers, while reducing the number of resistive memory banks per memory controller. The number of processor tiles 120 significantly increases / decreases system memory parallelism.

[0069] Number of processor tiles 64 128 256 512 1024 Subarray of each tile 1024 512 256 128 64 Storage in each tile 128 64 32 16 8

[0070] Table 1: For different numbers of processor tiles and for N sa =64K and L act In the implementation of 8, the number of subarrays and memory storage units per processor tile 120

[0071] Figure 4 A block diagram of an example monolithic subchip-level computing architecture 400 according to another embodiment of this disclosure is shown. Computing architecture 400 illustrates multiple memory controllers per processor core to facilitate high system memory parallelism of the disclosed computing architecture. Processor core 410 is communicatively connected to multiple memory controllers 420. Each memory controller 420 is similarly connected to a set of resistive memory subarrays 430 comprising multiple independent subarrays 440. Because processor core 410 is connected to numerous independent subarrays 440 via multiple memory controllers 420, processor core 410 can generate a large number of memory requests that can be executed concurrently on the independent subarrays 440. This allows processor core 410 to amortize the relatively long access latency (e.g., hundreds of nanoseconds) of the independent subarrays 440 across numerous memory requests, thereby achieving high overall throughput.

[0072] Given the access time, the general equation for the degree of parallelism required to support the required bandwidth is as follows:

[0073] Memory parallelism = bytes / second * seconds / access * access / byte The equation above gives the required bandwidth in the first term: bytes / second, the access latency in the second term: seconds / access, and the number of bytes transferred per access in the third term: access / byte. Consider a matrix multiplication problem performed on multiple cores. For a core running at 1 GHz, with a sustained rate of two 64-bit floating-point multiply-accumulate operations per cycle, the required bandwidth is 4 x 8 bytes / nanosecond = 32 GB / s. For a main memory access of 8 bytes per access (e.g., to facilitate reasonably high access granularity and good useful data throughput), given an access time of 200 nanoseconds, the minimum parallelism per core would be:

[0074] 32 bytes / ns * 200ns / access * access / 8 bytes = 800. The result 800 represents the number of concurrent memory requests that computing architecture 400 needs to process per core to maintain a data rate of 32GB / s with a given 200ns access time and 8 bytes accessed per access. As access time increases, the required parallelism increases proportionally. For example, a 500ns access time requires 2.5 times the parallelism, or 2000 concurrent memory requests per core. This parallelism exceeds the capacity of conventional main memory (e.g., DRAM) by several orders of magnitude.

[0075] It should be understood that the above requirements do not mandate 800 or 2000 memory channels per core, but rather that the memory system must be able to manage the aforementioned number of synchronous requests that overlap in time. For example, each memory controller 420 can concurrently control multiple memory banks, each memory bank can be in a different state, thereby allowing each memory controller 420 to concurrently "pipeline" multiple memory requests.

[0076] refer to Figure 5 This describes an implementation of an example monolithic multiprocessor network-on-chip (NoC) architecture 500. The NoC architecture 500 provides command and data paths 510 that connect multiple processor cores, including processor core 1410 to processor core 1410. X 412, where X is a suitable number greater than 1 (e.g., 32, 64, 128, 256, 512, etc.). Processor cores will be collectively referred to as processor cores below. 1-X 410-412. Processor cores. 1-X Each of 410-412 is connected to a separate memory subsystem, and each memory subsystem includes multiple memory controllers. 1-X 420-422, multiple memory controllers are respectively connected to the corresponding memory subarray groups 4301......430 X Each memory subarray 4301......430 is connected to the memory controller. X Includes multiple independently accessible memory subarrays 4401-440 X Routing devices associated with each processor core (not depicted, but see above) Figure 1 ) Memory access requests can be issued to different memory subsystems via command and data path 510 when appropriate. For example, if a memory request issued by processor core 14101 includes the processor core... X A set of memory subarrays 412 430 X 440 independent subarrays within X If the data location is specified, the data location and memory request can be submitted by the routing device to the command and data path 510, and connected to the processor core. X The corresponding routing device of 412 receives the data. This is in service of data from independent subarray 440. XWhen a memory request for a data location is made, an acknowledgment or data is returned on command and data path 510 and received at processor core 1410. As will be understood by those skilled in the art from the context provided herein, the NoC architecture 500 can be adapted to a similar process that includes multiple memory requests for multiple physical data locations originating from multiple cores and targeting memory subsystems in multiple other cores (or some of the same cores).

[0077] In applications of NoC computing architectures where significant data sharing between threads and cores in a multi-core system is expected, substantial congestion can occur on the data and communication paths 510 that interconnect multiple cores. For example, congestion can arise within the routers that connect each core to the data and communication paths 510, as requests for non-local data must pass through and utilize routers connected to other cores. Figure 6 A monolithic multiprocessor on-chip network computing architecture 600 is illustrated according to an alternative or additional implementation that can minimize NoC congestion. The computing architecture 600 can manage both simpler applications that share a small number of memory requests among cores (and associated memory subsystems) and congestion situations involving significant sharing between cores and memory subsystems. The computing architecture 600 places memory controllers 410-427 as endpoints on data and communication paths 610, such that each memory controller 410-427 on the NoC has equal bandwidth. The computing architecture 600 creates a truly distributed main memory, where cores 410-412 act as clients of memory controllers 410-427, rather than their owners.

[0078] Figure 7 An example 2D arrangement 700 of processing cores and memory controllers for the disclosed NoC computing architecture is shown in another disclosed embodiment. The 2D arrangement 700 includes three memory controllers 420 per processor core 410, further facilitating high memory parallelism. Each processor core 410 can exchange commands and data between connected memory controllers 420, and each memory controller 420 can similarly send and receive data and commands with other connected memory controllers 420. The arrangement of the memory controllers 420 and processor cores 410 can be conceptual (depicting the interaction, but not the physical location of associated memory circuitry and logic circuitry), or it can reflect the physical arrangement of memory circuitry and logic circuitry on the substrates of the corresponding memory controllers 420 and processor cores 410.

[0079] Figure 8An alternative 2D arrangement 800 for the processing cores and memory controllers of the disclosed NoC computing architecture is depicted in other embodiments. The 2D arrangement 800 includes 4108 memory controllers 420 per processor core, thereby increasing memory parallelism on top of the memory parallelism provided by the 2D arrangement 700. Similar to... Figure 7 The arrangement of the memory controller 420 and processor core 410 for the 2D arrangement 800 can be conceptual or can be reflected in the physical arrangement of memory circuits and logic circuits on the substrate.

[0080] In some implementations, the computing architecture (e.g., the one described above) Figure 1 The processor tiles of computing architecture 100 can have a single core, a network router, and a memory controller per processor tile 120. This simplicity is attractive for minimizing design overhead, but it is inflexible because all hardware resources scale at the same rate with the number of processor tiles. Some alternative implementations form heterogeneous tiles instead. In these implementations, in addition to having separate processor tiles, separate memory controller tiles that integrate the memory controller with the router device can be implemented (e.g., in at least some implementations, combined with computing architecture 400 or NoC architecture 500). In these implementations, the number of memory controllers (and routers) can be... Figure 7 and Figure 8 The 2D layout of the 700 and 800 decouples the number of processor cores provided. Heterogeneous tiles can be designed independently for the size of each core and the number of access points into the resistive memory subarray.

[0081] Figure 9 A block diagram of an example NoC monolithic computing system 900 according to one or more embodiments of this disclosure is depicted. A single, independent IC chip 902 is depicted having multiple processing cores 910-912, each processing core having access to a cache and cache controllers 914-916. In the event of a cache miss, a request is made to main memory via an on-chip network architecture 920. In some embodiments, the request may be a complete cache block, a portion of a cache block in other embodiments (e.g., a minimum fetch size, such as 8 bytes or other suitable minimum fetch size), or multiple cache blocks. A memory controller associated with resistive main memory 930 may return data associated with the memory request.

[0082] In one or more embodiments, the NoC monolithic computing system 900 may include 64 processing cores 910-912, each with 8K independent resistive main memory banks 930 in two stacked 2D cross arrays, for a total memory parallelism of 16K memory requests. The access latency to the resistive main memory 930 is approximately 700 ns, and the minimum fetch size is 8 bytes (e.g., the minimum subarray fetch is 1 byte, and L...). act =8), the computing system 900 is estimated to achieve 23.4 GTEPS. This high performance, coupled with the non-volatile nature of the system memory, high-capacity system memory (e.g., 64 GB), and the elimination of off-chip memory access, is expected to significantly improve the state of existing processing systems.

[0083] Figure 10 Figure 1000 illustrates the memory parallelism of an example embedded resistive memory computing architecture according to one or more embodiments shown herein. Figure 1000, for a 64-core computing system, plots the different instruction sets used to achieve parallelism in a multi-core system along the horizontal axis and the number of maximum synchronous memory requests along the vertical axis.

[0084] Basic parallelism is demonstrated through the independence of multiple cores, where each core issues a single memory request separate from the others. For a numbered system: C cores / processor tiles, each core / processor tile can issue at most a single memory request per clock cycle, and C concurrent memory requests can be issued and executed simultaneously by such a system (sometimes referred to in the art as a scalar system). For a 64-core scalar system, there may be 64 concurrent memory requests. The next step is an example where separate process threads can execute independently and concurrently on different cores (superscalar), or cores are configured to switch between hardware backgrounds to issue multiple memory requests in an interleaved manner across threads (multithreading). This produces a multiplier n of process threads interleaved, requesting, and executing by C cores, reaching a maximum of n*C concurrent memory requests. Where, in a 64-core system, n=4, the number of concurrent memory requests increases to 256.

[0085] As a further improvement, multiple data instruction sets (e.g., Single Instruction Multiple Data (SIMD)) that can process multiple data elements concurrently can be implemented to further increase memory parallelism. For example, SIMD pipelined processing supports scatter-cluster, allowing each subword from a single scatter-cluster operation to generate a separate memory request for a different physical memory location. For y-way scatter-cluster, memory parallelism can be increased to y*n*C concurrent memory requests. Figure 10The diagram depicts an 8-way distributed-aggregated paradigm, combining 4-way multithreading and a 64-core system to achieve 2048 concurrent memory requests. This level of memory parallelism far exceeds that of conventional DRAM systems, but with a greater number of resistive memory subarrays per chip (e.g., ~64K) and a smaller L... act Values ​​(e.g., 8) allow for even greater memory parallelism (e.g., 8000 synchronization requests). In smaller L... act In implementations with values ​​such as 4, even greater memory parallelism is physically possible (e.g., 16,000 synchronization requests).

[0086] To further increase memory parallelism, some embodiments of this disclosure implement non-blocking SIMD scatter-cluster. For blocking instructions, when the core issues a long-delayed memory operation (e.g., in response to a cache miss that generates a main memory request), the core pauses while waiting for the result of the memory operation to return. On the other hand, non-blocking memory operations are those that the core can continue executing while the long-delayed store operation is still pending. As an example, a write operation can be combined with a data buffer to become non-blocking, which is configured to temporarily store the stored data before it is written to memory. In various embodiments, per-register-presence bits are provided in the register file to identify instructions dependent on non-blocking loads, and consecutive non-blocking instructions are organized to delay core pauses due to dependent instructions. Alternatively, a scoreboard structure can be organized in memory to consecutively identify and organize non-blocking instructions. If multiple non-blocking memory operations are encountered consecutively, both non-blocking loads and stores allow a single thread to issue multiple memory requests. Therefore, the amount of memory parallelism generated is limited by the allowed number of incomplete non-blocking runs.

[0087] Implementations of this disclosure combine non-blocking instruction techniques with SIMD scatter-cluster operations to further enhance memory parallelism. For example, buffering of write operations and tracing dependent read operations can be applied to SIMD pipelines and register files for integration with scatter-cluster operations. In an implementation, in an n-way multithreaded system, z-depth non-blocking instructions can be sequentially organized for a y-way SIMD scatter-cluster paradigm. This results in a total memory parallelism of z*y*n*C. In the above example of 8-way scatter-cluster, 4-way multithreaded 64-core, with z=4, the memory parallelism increases to 8K. Figure 10 In this context, for z=8, an 8-depth non-blocking instruction set is provided, resulting in 16K of memory parallelism.

[0088] Figure 11An example processor tile 1100 according to one or more embodiments of the present disclosure is shown, demonstrating monolithic integration of a CPU with resistive main memory. In one or more embodiments, the processor tile 1100 may be replaced with... Figure 1 The processor tile 120. Processor tile 1100 shows the location of resistive memory subarrays 1104A, 1104B, 1104C, and 1104D (collectively referred to as ReRAM subarrays 1104A-D) of a single cross-shaped ReRAM cluster 1102 relative to surrounding circuitry. The resistive memory modeled for the resistive memory subarrays 1104A-D is resistive random access memory (ReRAM) technology manufactured by Crossbar, Inc. (although various other types of resistive non-volatile memory are contemplated within the scope of this disclosure). Because a single resistive memory subarray is small compared to the size of processor tile 120, the peripheral access circuitry to each resistive memory subarray will be distributed across processor tile 1100, affecting the logic circuitry of the processor core containing processor tile 1100.

[0089] Processor tile 1100 represents an example solution for the circuit layout of the access circuitry for the various subarrays, as well as the logic circuitry containing the processor core. Processor tile 1100 illustrates a physical design integrating multiple ReRAM subarrays 1104A-D with a very small CPU core. The layout of processor tile 1100 was performed using the open-source NCSU FreePK 45nm process design kit and the Nangate open-source digital library for the 45nm process node. However, the layout of processor tile 1100 is merely exemplary and is not intended to limit the implementations disclosed herein. The CPU core is a Berkeley VSCALE, a single-problem, 3-stage sequential pipelined 32-bit integer RISC-V processor implementing computational logic. A single core is implemented in processor tile 120, but the data path is increased to 256 bits to facilitate a larger design (which may still be small compared to commercial high-performance CPU cores). Synopsys Design Compiler is used for the integration step of the tool process, and Cadence Encounter is used for the automatic layout and routing (APR) step of the process to produce the final GDSII layout.

[0090] Processor tile 1100 illustrates the integration of a VSCALE processor with ReRAM memory to create a processor-memory tile, as an example of the processor tile 120 provided above. Each ReRAM subarray 1104A-D includes peripheral access circuitry formed in an L-shape positioned along the two vertical edges of subarray 1104. For example, 1106C shows the L-shaped peripheral access circuitry location of ReRAM subarray 1104C, and 1106B shows the L-shaped peripheral access circuitry location of ReRAM subarray 1104B. Similar locations are provided for ReRAM subarrays 1104A and 1104B. Figure 11 The subarrays in the other cross-shaped ReRAM cluster 1102 provide the corresponding access circuitry.

[0091] The peripheral access circuits 1106B and 1106C are arranged to form the blocking regions of the CPU core, with these blocks adjacent to each other, creating continuous blocking regions. Note that the peripheral access circuits represent two types of blocking. The first is placement blocking, which prevents standard CPU core cells from being placed in these blocking regions. The second is routing blocking at specific metal layers to restrict routing. Figure 11 In the middle, metal layers 1-8 are blocked for routing, allowing the APR tool to use metal layers 9 and 10 to route through the blocked area.

[0092] The above-described diagrams have been described for various components of integrated circuit chips, systems-on-a-chip (SoCs), or networks-on-a-chip (NICs), including arrangements of memory arrays, memory circuits, logic circuits, and system components (e.g., memory controllers, cache controllers, router devices, etc.), as well as monolithic layer groups for forming some or all of these components. It should be understood that, in some suitable alternative aspects of this disclosure, the various diagrams may include the depicted arrangements of specified components / arrays / circuits / devices / layers, some of the specified components / arrays / circuits / devices / layers, or additional components / arrays / circuits / devices / layers. Sub-components may also be implemented as electrically connected to other sub-components, rather than being included within a parent component / layer. For example, memory controller 125, router 128, and SIMD instruction set 126 may be contained on separate heterogeneous tiles, rather than integrated as part of processor tile 120. Furthermore, components / arrays / circuits / devices, etc., depicted in one diagram should be understood to be operable in other diagrams, if applicable. For example, Figure 4 , Figure 5 and Figure 6 The processor core / memory controller organization described in any of the documents can be... Figure 1This is implemented as an alternative implementation within the architecture. Further variations, combinations, reductions, or additions of components not specifically described herein but which are understood by those skilled in the art, or which are reasonably understood by those skilled in the art from the context provided herein, are considered within the scope of this disclosure. Furthermore, it should be noted that one or more disclosed processes may be combined into a single process that provides aggregate functionality. Components of the disclosed architecture may also interact with one or more other components not specifically described herein but known to those skilled in the art.

[0093] Based on the example diagram above, refer to Figures 12-14 A flowchart will provide a better understanding of the process approach that can be implemented based on the disclosed subject matter. Although for the sake of simplicity of explanation... Figures 12-14 The methods are shown and described as a series of blocks, but it should be understood and appreciated that the claimed subject matter is not limited by the order of the blocks, as some blocks may occur in a different order or concurrently with other blocks depicted and described herein. Furthermore, not all blocks shown are necessarily required to implement the methods disclosed herein. Moreover, it should be further understood that some or all of the methods disclosed throughout this specification can be stored on an article of manufacture for transporting and transferring these methods to an electronic device. The term "article of manufacture" as used is intended to encompass a computer program accessible from any computer-readable device, a device in conjunction with a carrier, or a storage medium.

[0094] refer to Figure 12 This describes a method for manufacturing a monolithic IC chip, including a resistive system memory, in one or more embodiments. At 1202, method 1200 may include forming logic circuitry for a processor core, including cache memory and cache controller circuitry, on a substrate of the integrated circuit chip. In some embodiments, the logic circuitry may be formed in a continuous region of the substrate, beneath a back-end metal layer of the wafer layout design. However, in other embodiments, a at least partially discontinuous layout of the logic circuitry within discontinuous portions of the substrate is contemplated.

[0095] At 1204, method 1200 may include memory access circuitry for operation on a non-volatile resistive system memory, formed at least partially on the substrate and adjacent to logic circuitry. The memory access circuitry may include a sense amplifier, an address decoder, a multiplexer for coupling power to a subset of the memory subarray, etc. At 1206, method 1200 may additionally include circuitry for a system memory controller formed at least partially on the substrate.

[0096] At 1208, method 1200 may include providing electrical contacts to communicatively connect logic circuitry and memory access circuitry to a system memory controller. At 1210, method 1200 may include forming a non-volatile resistive memory array overlaying the substrate and the logic circuitry and memory access circuitry. The resistive memory array may be formed in a cross pattern between wires of a monolithic IC chip. Furthermore, the resistive memory array may be formed using CMOS logic processes. In one embodiment, a plurality of cross arrays are formed, at least partially stacked on top of each other to form a 3D memory array. The 3D memory array overlays the substrate and the logic circuitry, and at least partially overlays the memory access circuitry.

[0097] At 1212, method 1200 may include connecting memory access circuitry to a non-volatile resistive memory array to form a plurality of independently accessible subarrays. In an embodiment, the size of each subarray may include approximately 2,000 (2K) by approximately 2K memory cells. In at least one embodiment, the total number of independently accessible subarrays may be approximately 64K subarrays. Furthermore, the subarrays may be arranged as tiles, and each tile may be connected to a processor core (or, in other embodiments, each tile may be connected to multiple processor cores). In one embodiment, each processor tile provides 1024 subarrays. In another embodiment, each processor tile provides 512 subarrays. In yet another embodiment, each processor tile provides 128 subarrays. In still another embodiment, each processor tile provides 64 subarrays.

[0098] In alternative implementations, independently accessible subarrays can be connected to the memory controller and routing tiles independently of the processor tiles. In these implementations, a similar number of subarrays can be provided per memory / router tile as described above.

[0099] At 1214, method 1200 may include configuring the memory controller to independently perform memory operations on the respective subarrays in response to commands from the processor core or cache controller. The memory controller may be partitioned into separate memory bank controllers, which access a number of memory banks (L) on each memory access. act Number of subarrays. L is the number of subarrays activated by the memory controller. act It corresponds to a single memory bank and is used as the minimum extraction size for a monolithic IC chip memory request.

[0100] Reference Figure 13This document describes a flowchart of an example method for operating a processor in a multi-core chip including resistive system memory, in one or more embodiments. At 1302, method 1300 may include implementing process threads on the logic circuitry of the processor cores of the multi-core chip. At 1304, method 1300 may access cache memory to meet the storage needs of the process threads. At 1306, it is determined whether the cache access results in a cache hit. If a cache hit occurs, method 1300 may proceed to 1308. Otherwise, method 1300 proceeds to 1316.

[0101] At 1308, method 1300 may include retrieving the required data from the cache, and at 1310, executing the process instructions that require the cached data. At 1312, it is determined whether the process thread has completed. If the process thread has completed, method 1300 may proceed to reference numeral 1322 and terminate. Otherwise, method 1322 proceeds to reference numeral 1314, increments the process thread's instruction set, and returns to reference numeral 1302.

[0102] At 1316, method 1300 generates a system memory access request (e.g., a read) with less than 128 bytes of data. Multi-core chips facilitate fetching data smaller than a standard DRAM page of 128 bytes. Therefore, the access request can be a single cache block (e.g., 64 bytes), half a cache block (e.g., 32 bytes), or even less data: e.g., 16 bytes, 8 bytes, 4 bytes, 1 byte, etc.

[0103] At 1318, method 1300 may include issuing a memory request to the on-chip resistive memory system memory. At 1320, method 1300 may optionally include executing an additional process thread while the memory request is suspended. At 1322, the additional process thread may also optionally include generating and issuing one or more additional resistive memory access requests. In various embodiments, the additional memory access requests may include multi-threaded requests (issued as part of a separate hardware context or a separate process thread), separate memory addresses for scatter-aggregate memory instructions, or subsequent non-blocking memory access instructions. At 1324, method 1300 may include obtaining less than 128 bytes from system memory in response to the memory request at reference numeral 1318. From 1424, method 1300 may proceed to 1310 and complete the processing instructions at reference numeral 1306 for determining a cache miss. Various variations of method 1300 known in the art or known to those skilled in the art through the context provided herein are considered to be within the scope of this disclosure.

[0104] refer to Figure 14A flowchart of an example method 1400 for manufacturing a monolithic IC chip according to alternative or additional embodiments is provided. At 1402, method 1400 may include setting logic circuitry on a substrate of an integrated circuit, the logic circuitry including multiple processing cores and a cache memory / controller. CMOS process technology may be used to set the logic circuitry. At 1404, method 1400 may include setting separate subarray access circuitry for resistive system memory on the substrate. In some embodiments, the access circuitry may be adjacent to the logic circuitry and located near an associated back-end memory subarray, depending on the semiconductor design layout. In other embodiments, the access circuitry may be integrated into the logic circuitry in a fine-grained grid implementation. In other embodiments, combinations of the above may be implemented.

[0105] At 1406, method 1400 may include circuitry configuring a plurality of memory controllers for each processing core, and at 1408, method 1400 may include circuitry configuring at least one router device for each processing core. In at least one embodiment, as described herein, the memory controllers for each processing core and router device may be organized as controller tiles independent of processor tiles.

[0106] At 1410, method 1400 may include setting command and data paths that interconnect the processing core and the router device. At 1412, method 1400 may include forming a resistive memory structure overlaid on a substrate, the resistive memory structure comprising independent subarrays of resistive memory. In an embodiment, the resistive memory structure may be formed using a CMOS process (e.g., a back-end process). At 1414, method 1400 may provide electrical connections between the subarray group and corresponding memory controllers. In an embodiment, the memory subsystem is connected to individual controller tiles that are interconnected to other controller tiles and processor tiles via command and data paths. In such an embodiment, the memory controller tiles act as endpoints in a NoC architecture, and the processor tiles may operate as clients of the memory controller tiles.

[0107] Additionally, at 1416, method 1400 may include configuring the memory controller to be responsive to memory requests from multiple processing cores or cache controllers. Furthermore, at 1418, method 1400 may include configuring the processing cores and cache controllers to issue multiple concurrent memory requests to corresponding subarrays of the resistive system memory according to a multiple data instruction set. Examples of multiple data instruction sets may include a multi-threaded instruction set, a scatter-aggregate SIMD multi-threaded instruction set, or a non-blocking scatter-aggregate SIMD multi-threaded instruction set. In various embodiments, the memory controller is configured to distribute concurrent memory requests from multiple processing cores or cache controllers to various memory banks to execute multiple memory requests concurrently.

[0108] In various embodiments of this disclosure, the disclosed memory architecture can be used as a standalone or integrated embedded memory device having a CPU or microcomputer. For example, some embodiments can be implemented as part of a computer memory (e.g., random access memory, cache memory, read-only memory, storage memory, etc.). Other embodiments can be implemented as components of, for example, portable memory devices.

[0109] Figure 15 A block diagram of an example operating and control environment 1500 for a memory array 1502 for a memory cell array according to aspects of this subject matter disclosure is shown. In at least one aspect of this disclosure, the memory array 1502 may include a memory selected from a variety of memory cell technologies. In at least one embodiment, the memory array 1502 may include a dual-ended memory technology arranged in a compact two-dimensional or three-dimensional architecture. As disclosed herein, example architectures may include 1T1R memory arrays and 1TnR memory arrays (or 1TNR memory arrays). Suitable dual-ended memory technologies may include resistive switching memory, conductive bridged memory, phase-change memory, organic memory, magnetoresistive memory, etc., or the like or suitable combinations thereof. In some embodiments, the memory array 1502 may be a memory storage body comprising multiple independently accessible memory subarrays. In other embodiments, as described herein, the memory array 1502 may serve as an embedded main memory for a multi-core IC chip.

[0110] Column controller 1506 and sense amplifier 1508 may be formed adjacent to memory array 1502. Furthermore, column controller 1506 may be configured to activate (or identify to activate) a subset of bit lines of memory array 1502. Column controller 1506 may utilize control signals provided by reference and control signal generator 1518 to activate and operate on corresponding bit lines within the subset of bit lines, applying appropriate programming, erasing, or read voltages to those bit lines. Inactive bit lines may be maintained at a suppression voltage (also applied by reference and control signal generator 1518) to mitigate or avoid bit interference effects on these inactive bit lines.

[0111] Furthermore, the operating and control environment 1500 may include a row controller 1504. The row controller 1504 may be formed adjacent to and electrically connected to the word lines of the memory array 1502. Utilizing control signals from the reference and control signal generator 1518, the row controller 1504 can select specific rows of memory cells with appropriate selection voltages. Additionally, the row controller 1504 can facilitate programming, erasing, or reading operations by applying appropriate voltages to the selected word lines.

[0112] The sensing amplifier 1508 can read data from or write data to active memory cells of the memory array 1502, which are selected by column control 1506 and row control 1504. Data read from the memory array 1502 can be provided to the buffer 1512. Similarly, data to be written to the memory array 1502 can be received from the buffer 1512 and written to the active memory cells of the memory array 1502.

[0113] Clock source 1508 can provide corresponding clock pulses to facilitate the timing of read, write, and programming operations of row controller 1504 and column controller 1506. Clock source 1508 can also facilitate word line or bit line selection in response to external or internal commands received by operating and control environment 1500. Buffer 1512 can include command and address inputs, as well as bidirectional data inputs and outputs. Instructions are provided via command and address inputs, and data to be written to and read from memory array 1502 is transferred on bidirectional data inputs and outputs, facilitating communication to the processing core or cache controller, as described above. Figure 1 The connection of the processing core 122 or the high-speed buffer controller 124.

[0114] Buffer 1512 can be configured to receive write data, receive erase commands, receive status or maintenance commands, output read data, output status information, and receive address data and command data, as well as address data for corresponding commands. Address data can be transmitted to row controller 1504 and column controller 1506 via address register 1510. Furthermore, input data is transmitted to memory array 1502 via signal input lines between sense amplifier 1508 and input / output buffer 1512, and output data is received from memory array 1502 via signal output lines from sense amplifier 1508 to buffer 1512. Input data can be received from the processing core or cache controller, and output data can be transmitted to the processing core / cache controller via memory access circuitry.

[0115] Commands received from the processing core or cache controller can be provided to command interface 1516. Command interface 1516 can be configured to receive internal control signals from the processing core / cache controller and determine whether the data input to input / output buffer 1512 is write data, a command, or an address. Where applicable, input commands can be transmitted to an optional state machine 1520.

[0116] Optional state machine 1520 can be configured to manage the programming and reprogramming of memory array 1502 (and other memory banks of the multi-bank memory array). Instructions provided to state machine 1520 are implemented according to control logic configuration, enabling the state machine to manage read, write, erase, data input, data output, and other functions associated with memory cell array 1502. In some aspects, state machine 1520 can send and receive acknowledgments and negative acknowledgments regarding the successful reception or execution of various commands. In other embodiments, state machine 1520 can decode and execute state-related commands, decode and execute configuration commands, and so on.

[0117] To implement functions such as read, write, erase, input, and output, state machine 1520 can control clock source 1508 or reference and control signal generator 1518. Control of clock source 1508 can cause output pulses to be configured to prompt row controller 1504 and column controller 1506 to perform specific functions. Output pulses can be transmitted, for example, by column controller 1506 to selected bit lines, or, for example, by row controller 1504 to word lines. In some embodiments, state machine 1520 can be replaced by a memory controller as described herein for performing memory operations on memory array 1502. In alternative embodiments, state machine 1520 can act as a memory controller and be configured to implement the functions of the memory controller disclosed herein.

[0118] The aspects shown in this disclosure can also be practiced in a distributed computing environment, where certain tasks are performed by multiple monolithic IC chips linked via a communication network, each containing embedded resistive memory. In a distributed computing environment, program modules or stored information, instructions, etc., can reside in local or remote memory storage devices.

[0119] As used herein, the terms “component,” “system,” “architecture,” etc., are intended to refer to a computer or electronically related entity as hardware, a combination of hardware and software, software (e.g., running), or firmware. For example, a component can be one or more transistors, memory cells, an arrangement of transistors or memory cells, a gate array, a programmable gate array, an application-specific integrated circuit (ASIC), a controller, a processor, a process running on a processor, an object, an executable file, a program or application accessed or coupled to semiconductor memory, a computer, or the like, or a suitable combination thereof. The component may include erasable programming (e.g., process instructions at least partially stored in erasable memory) or hard programming (e.g., process instructions burned into non-erasable memory during manufacturing).

[0120] For example, processes executed from memory and processors can both be components. As another example, an architecture can include electronic hardware (e.g., parallel or series transistors), processing instructions, and an arrangement of processors that implements the processing instructions in a manner suitable for the electronic hardware arrangement. Furthermore, an architecture can include individual components (e.g., transistors, gate arrays, etc.) or arrangements of components (e.g., series or parallel arrangements of transistors, gate arrays connected to program circuitry, power lines, electrical grounds, input signal lines, and output signal lines, etc.). A system can include one or more components and one or more architectures. An example system can include a switching block architecture that includes cross-input / output lines and transmission gate transistors, as well as power supplies, signal generators, communication buses, controllers, I / O interfaces, address registers, etc. It is understood that some overlap in the definitions is anticipated, and an architecture or system can be a standalone component or a component of another architecture, system, etc.

[0121] In addition to the foregoing, the disclosed subject matter can be implemented as methods, apparatus, or articles of manufacture using typical manufacturing, programming, or engineering techniques to produce hardware, firmware, software, or any suitable combination thereof to control electronic devices to implement the disclosed subject matter. The terms “apparatus” and “article of manufacture” as used herein are intended to cover electronic devices, semiconductor devices, computers, or computer programs accessible from any computer-readable device, carrier, or medium. Computer-readable media can include hardware media or software media. Furthermore, media can include non-transitory media or transmission media. In one example, non-transitory media can include computer-readable hardware media. Specific examples of computer-readable hardware media may include, but are not limited to, magnetic storage devices (e.g., hard disks, floppy disks, magnetic stripes, etc.), optical disks (e.g., optical discs (CDs), digital versatile optical discs (DVDs), etc.), smart cards, flash memory devices (e.g., cards, sticks, key drives, etc.). Computer-readable transmission media can include carrier waves, etc. Of course, those skilled in the art will recognize that many modifications can be made to this configuration without departing from the scope or spirit of the disclosed subject matter.

[0122] The above description includes examples of the subject matter innovation. It is certainly impossible to describe every conceivable combination of components or methods for the purpose of describing the subject matter innovation, but those skilled in the art will recognize that many other combinations and arrangements of the subject matter innovation are possible. Therefore, the disclosed subject matter is intended to include all such changes, modifications, and variations that fall within the spirit and scope of this disclosure. Furthermore, where the terms “include,” “including,” “have,” or “having,” and variations thereof are used in the detailed description or claims, such terms are intended to be encompassed in a manner similar to the following: when used as a transitional word in a claim, the term “comprising” is interpreted as “comprising.”

[0123] Furthermore, the term "exemplary" as used herein means serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as being more preferred or advantageous than other aspects or designs. More precisely, the use of the term "exemplary" is intended to present concepts in a concrete manner. As used herein, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise stated or clear from the context, "X uses A or B" is intended to mean any naturally inclusive permutation. That is, if X uses A; X uses B; or X uses both A and B, then "X uses A or B" is satisfied in any of the foregoing cases. Furthermore, unless otherwise specified or explicitly designated by the context as singular, the articles "a" and "an" as used herein and in the appended claims should generally be interpreted as "one or more."

[0124] Furthermore, some parts of the detailed description have been presented based on algorithms or processing operations on data bits within the electronic memory. These process descriptions or representations are mechanisms used by those skilled in the art to effectively convey the substance of their work to others of equal skill. The processes described herein are generally considered to be a self-consistent sequence of actions leading to a desired result. These actions are those that require physical manipulation of physical quantities. Typically, though not always, these quantities take the form of electrical and / or magnetic signals that can be stored, transmitted, combined, compared, and / or otherwise manipulated.

[0125] It has proven convenient, primarily for common use, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc. However, it should be remembered that all these and similar terms are associated with appropriate physical quantities and are merely convenient labels applicable to those quantities. Unless otherwise specifically stated or apparent from the preceding discussion, it should be understood that throughout the disclosed subject matter, discussions using terms such as processing, calculating, copying, imitating, determining, or transmitting refer to the behavior and processes of processing systems, and / or similar consumer or industrial electronic devices or machines that manipulate or convert data or signals represented as physical (electrical or electronic) quantities in the circuits, registers, or memories of electronic devices, and other data or signals similarly represented as physical quantities in the memories or registers of machine or computer systems or other such information storage, transmission, and / or display devices.

[0126] Regarding the various functions performed by the aforementioned components, architectures, circuits, processes, etc., the terms used to describe these components (including references to "device") are, unless otherwise stated, intended to correspond to any component (e.g., a functional equivalent) that performs the specified function of the described component, even if structurally not equivalent to the structure disclosed herein, which performs that function in exemplary aspects of the embodiments shown herein. Furthermore, while a particular feature may be disclosed only for one of several implementations, that feature may be combined with one or more other features of other implementations, which may be desirable and advantageous for any given or particular application. It will also be appreciated that implementations include systems having computer-executable instructions for performing actions and / or events of various processes, as well as computer-readable media.

Claims

1. An integrated circuit device comprising: a plurality of processing cores formed on a substrate of the integrated circuit device; a resistive memory array structure formed over the substrate of the integrated circuit device, the resistive memory array structure comprising a plurality of resistive memory subarrays, each resistive memory subarray comprising non-volatile, bi-terminal, resistive switching memory cells; an access circuit formed at least partially on the substrate of the integrated circuit device, the access circuit providing independently operable access to respective resistive memory subarrays of the plurality of resistive memory subarrays; and a plurality of memory controllers comprising a first set of memory controllers communicatively coupled with a first processing core of the plurality of processing cores and operable to receive a first memory instruction from the first processing core and execute the first memory instruction on a first set of resistive memory subarrays of the plurality of resistive memory subarrays in response to the first memory instruction, and a second set of memory controllers communicatively coupled with a second processing core of the plurality of processing cores and operable to receive a second memory instruction from the second processing core and execute the memory instruction on a second set of resistive memory subarrays of the plurality of resistive memory subarrays in response to the second memory instruction, wherein the first memory instruction or the second memory instruction is a memory read returning less than 128 bytes of data; the plurality of memory controllers being capable of concurrently servicing a number of main memory requests from the plurality of processing cores at least equal to a number of the plurality of resistive memory subarrays.

2. The integrated circuit device of claim 1, wherein, the resistive memory array structure at least partially overlaid on the plurality of processing cores and further comprising a cache and a cache controller for servicing data demands of the first processing core or the second processing core, wherein the first memory instruction or the second memory instruction originates from the cache controller in response to a cache miss associated with servicing the data demands.

3. The integrated circuit device of claim 1, further comprising: a first router device associated with the first processing core and the first set of memory controllers; a second router device associated with the second processing core and the second set of memory controllers; and command and data paths interconnecting the first router device and the second router device, wherein at least one of: the first router device decodes a memory address comprised by the first memory instruction that is addressed within the second set of resistive memory subarrays of the plurality of resistive memory subarrays and forwards at least a portion of the first memory instruction associated with the memory address through the command and data paths to the second router device for execution by the second set of memory controllers; or the second router device decodes a second memory address included in the second memory instruction that is addressed within the first set of resistive memory subarrays of the plurality of resistive memory subarrays and forwards at least a portion of the second memory instruction associated with the second memory address to the first router device over the command and data path for execution by the first set of memory controllers.

4. The integrated circuit device of claim 1, wherein, The integrated circuit device is organized into a number of compute tiles on the substrate, wherein a compute tile of the number of compute tiles includes a processing core of the plurality of processing cores, includes the first set of memory controllers, and includes access circuitry dedicated to and operatively connected with the first set of resistive memory subarrays of the plurality of resistive memory subarrays, wherein a number of the first set of resistive memory subarrays of the plurality of resistive memory subarrays associated with the compute tile is selected from the group consisting of: about 64, about 128, about 256, about 512, and about 1024.

5. The integrated circuit device of claim 1, wherein, The plurality of processing cores is selected from the group consisting of: about 16 or more processing cores, about 32 or more processing cores, about 64 or more processing cores; about 128 or more processing cores, about 256 or more processing cores, about 512 or more processing cores, and about 1024 or more processing cores.

6. The integrated circuit device of claim 1, wherein, Each processing core of the plurality of processing cores is capable of issuing a single outstanding memory instruction, and the plurality of memory controllers is configured to service a number of concurrent memory instructions at least equal to a number of processing cores.

7. The integrated circuit device of claim 1, wherein, Each processing core of the plurality of processing cores is a multithreaded processing core configured to issue a second number, x, of outstanding memory instructions, and the plurality of memory controllers is configured to service a number of concurrent memory instructions equal to a number of the plurality of processing cores multiplied by x.

8. The integrated circuit device of claim 7, wherein, Each processing core of the plurality of processing cores includes an n-way scatter-gather single input multiple data (SIMD) progress instruction to facilitate each processing core of the plurality of processing cores issuing x*n outstanding memory instructions, wherein the plurality of memory controllers is configured to service a number of concurrent memory instructions equal to a number of the plurality of processing cores multiplied by x*n.

9. The integrated circuit device of claim 8, wherein, Each processing core includes a non-blocking scatter-gather SIMD progress instruction that aggregates memory instructions into blocking and non-blocking memory instructions, including up to z consecutive non-blocking scatter-gather memory instructions to facilitate each processing core of the plurality of processing cores issuing up to z*x*n outstanding memory instructions, wherein the plurality of memory controllers is configured to service a number of concurrent memory instructions equal to a number of the plurality of processing cores multiplied by z*x*n.

10. The integrated circuit device of claim 1, wherein, The access circuit is divided into a number of access circuit portions equal to a number of the plurality of resistive memory subarrays, each access circuit portion facilitating operative access by a single memory controller of the plurality of memory controllers to a single subarray of the plurality of resistive memory subarrays.

11. The integrated circuit device of claim 1, wherein, The memory read returns a number of bytes of data selected from the group consisting of: 1 byte, 2 bytes, 4 bytes, 8 bytes, 16 bytes, 32 bytes, and 64 bytes.

12. The integrated circuit device of claim 1, wherein: The first set of memory controllers comprises a first memory controller and a second memory controller; The first memory instruction comprises a first set of memory addresses located within a first memory bank of the first set of resistive memory subarrays controlled by the first memory controller and a second set of memory addresses located within a second memory bank of the second set of resistive memory subarrays controlled by the second memory controller; The first memory controller activates resistive memory subarrays associated with the first memory in response to the first memory instruction and retrieves data from data locations within at least one of the activated memory subarrays defined by the set of memory addresses, wherein the data locations comprise a first number of data, and the second memory controller activates resistive memory subarrays associated with the second memory bank in response to the first memory instruction and retrieves data from second data locations within at least one of the activated memory subarrays defined by the second set of memory addresses, wherein the second data locations comprise a second number of data, further wherein: the first number of data or the second number of data is selected from the group consisting of: 1 byte, 2 bytes, 4 bytes, and 8 bytes of data.

13. A method of fabricating an integrated circuit device, comprising: providing logic circuitry on a substrate of a chip, the logic circuitry including a plurality of processing cores and cache memory for the processing cores; providing access circuitry for independent subarrays of resistive system memory at least partially on the substrate of the chip; providing circuitry including a plurality of memory controllers for each of the plurality of processing cores at least partially on the substrate of the chip; forming non-volatile, two-terminal resistive memory devices including the independent subarrays of resistive system memory overlying the substrate and overlying at least a portion of the logic circuitry, the access circuitry, or the circuitry including the plurality of memory controllers; forming electrical connections between respective portions of the access circuitry on the substrate of the chip and each of the independent subarrays of resistive system memory overlying the substrate of the chip; forming electrical connections between circuitry including each memory controller and respective portions of the access circuitry; providing a communication pathway between the logic circuitry including the plurality of processing cores and circuitry including the plurality of memory controllers; and configuring a memory controller of the plurality of memory controllers to implement memory instructions on an associated independent subarray of the resistive system memory responsive to a host memory request for the cache memory originating from the logic circuitry; configuring the processing core or the cache memory of the processing core of the processing core to issue a plurality of concurrent memory requests to respective memory controllers of the plurality of memory controllers according to a multi-process instruction set selected from a group consisting of: an n-way multi-threaded process set, an n*x-way distributed-aggregated multi-threaded process set, and a z*n*x-way non-blocking distributed-aggregated multi-threaded process set, where n, x, and z are suitable positive integers.

14. The method of claim 13, further comprising: providing a plurality of router devices within the logic circuitry including the plurality of processing cores, and providing command and data paths that interconnect the router devices.

15. The method of claim 14, wherein, the command and data paths are configured to communicate memory commands between router devices of the plurality of router devices, and are configured to communicate data associated with the memory commands between the router devices.

16. An integrated circuit device comprising: a plurality of processor tiles, wherein a processor tile of the plurality of processor tiles includes a processing core, a cache memory and cache controller, a memory controller, and a multi-data memory instruction set, wherein the plurality of processor tiles are formed on a substrate of the integrated circuit device; a resistive memory array structure formed over the substrate of the integrated circuit device and at least partially overlying the plurality of processor tiles, the resistive memory array structure including a plurality of independently addressable subarrays formed of non-volatile bi-directional resistive switching memory, wherein a portion of the independently addressable subarrays are managed by the memory controller; access circuitry formed at least partially on the substrate of the integrated circuit device, the access circuitry interconnecting the memory controller with the portion of the independently addressable subarrays managed by the memory controller; and a command and data bus interconnecting respective ones of the plurality of processor tiles, wherein the resistive memory array structure acts as a system memory for the processing core of the processor tile; configuring the processing core or the cache memory of the processing core of the processing core to issue a plurality of concurrent memory requests to respective memory controllers of the plurality of memory controllers according to a multi-process instruction set selected from a group consisting of: an n-way multi-threaded process set, an n*x-way distributed-aggregated multi-threaded process set, and a z*n*x-way non-blocking distributed-aggregated multi-threaded process set, where n, x, and z are suitable positive integers.

17. The integrated circuit device of claim 16, wherein, The memory controller is responsive to a memory request issued by the cache controller resulting from a cache miss, retrieves data from the portion of the independently addressable subarray managed by the memory controller in response to the memory request, and submits the data to the cache controller or the processing tile in response to the memory request.

18. The integrated circuit device of claim 17, wherein, The memory request defines a data location having a size less than 128 bytes.

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