Chip interconnection package structure and method of packaging the same

Abstract

A chip interconnection packaging structure and a packaging method thereof, the packaging method comprising the following steps: forming a first circuit layer and a second circuit layer on opposite surfaces of a substrate and electrically connecting the first circuit layer and the second circuit layer; arranging a motherboard connecting bump along the periphery of a sub-plate unit on the first circuit layer; cutting along the periphery of the sub-plate unit to expose the side of the motherboard connecting bump; and arranging soldering material on the side of the motherboard connecting bump; and arranging a first chip and a second chip on the first circuit layer and the second circuit layer to form electrical connection between the first chip and the second chip. The chip interconnection packaging structure of the present application connects two chips through the circuit layer of a sub-plate, and the circuit layer of the sub-plate is directly connected with the side of a mother plate through the motherboard connecting bump, thereby saving the area of the sub-plate on the mother plate, reducing the path length of the interconnection between the chips, improving the communication quality and the space utilization efficiency.

Claims

1. A chip interconnect packaging method, characterized in that, Includes the following steps: Prepare a substrate having an upper surface and a lower surface; the substrate includes a sub-board unit having a plurality of through holes. A first circuit layer is formed on a first surface of the sub-board unit, and a second circuit layer is formed on a second surface of the sub-board unit. Through holes are formed in the through holes so that the first circuit layer is electrically connected to the second circuit layer through each of the through holes. A motherboard connecting bump is provided on the first circuit layer, and the motherboard connecting bump is provided along the periphery of the sub-board unit; A cutting procedure is performed along the periphery of the sub-plate unit to expose one side of each of the mother plate connecting protrusions; A welding layer is provided on the side of the connecting protrusion of the mother plate; A line layer addition procedure is performed on the first line layer and the second line layer to set a first added line structure on the first line layer and a second added line structure on the second line layer. A first solder resist layer is provided on the first augmented layer circuit structure, and a second solder resist layer is provided on the second augmented layer circuit structure. The first solder resist layer exposes a plurality of first chip pads of the first augmented layer circuit structure, and the second solder resist layer exposes a plurality of second chip pads of the second augmented layer circuit structure. A portion of the first solder resist layer and the first add-on circuit structure is removed along the periphery of the sub-board unit to expose a top surface of the motherboard connecting bump; wherein, during the step of setting a solder layer on the side of the motherboard connecting bump, the solder layer extends from the side of the motherboard connecting bump to the top surface of the motherboard connecting bump.

2. The chip interconnection packaging method as described in claim 1, characterized in that, Further steps include: A first chip is disposed on the first circuit layer of the sub-board unit, and a second chip is disposed on the second circuit layer of the sub-board unit, such that the first chip is electrically connected to the second chip through the first circuit layer, the second circuit layer and each of the vias.

3. The chip interconnection packaging method as described in claim 1, characterized in that, Includes the following steps: A sublayer is pre-formed on the upper and lower surfaces of the substrate; and after completing the step of setting the motherboard connection bump on the first circuit layer, the method further includes: Remove the portion of the seed layer that is not covered by the first and second line layers.

4. The chip interconnection packaging method as described in claim 1, characterized in that, in, The substrate comprises multiple sub-board units, and each sub-board unit is arranged periodically.

5. The chip interconnect packaging method as described in claim 4, characterized in that, in, The substrate further includes a plurality of dicing zones, each of which is disposed at intervals between the peripheries of each of the sub-board units; In the step of performing a cutting procedure along the periphery of the sub-plate unit to expose the sides of each of the mother plate connecting protrusions, all material in each of the cutting groove areas is removed so that the sides of the mother plate connecting protrusions are exposed toward the cutting groove areas.

6. The chip interconnect packaging method as described in claim 1, characterized in that, in, Before performing a cutting procedure along the periphery of the sub-plate unit to expose the sides of each of the mother plate connecting protrusions, the following steps are further included: A protective layer is respectively applied to the first circuit layer and the second circuit layer; and After completing the step of setting a welding layer on the side of the connecting protrusion on the mother plate, the following steps are further included: Remove the protective layer on the first line layer and the second line layer.

7. The chip interconnection packaging method as described in claim 2, characterized in that, After completing the step of setting a welding layer on the side of the connecting protrusion on the mother plate, the following steps are further included: Separate the sub-board unit from the other parts of the substrate to complete an independent sub-substrate; wherein, The first chip and the second chip are disposed on the sub-substrate.

8. The chip interconnect packaging method as described in claim 7, characterized in that, Further steps include: Prepare a mother substrate; the mother substrate includes multiple circuit layers and has a sub-substrate receiving groove; the sub-substrate receiving groove has a side wall, and one side contact of the multiple circuit layers protrudes from the side wall; The sub-substrate, together with the first chip and the second chip, is placed into the sub-substrate receiving groove, such that the side of the motherboard connecting bump faces the side wall of the chip receiving groove. The motherboard connecting bump is connected to the side contact of the mother substrate through the welding layer.

9. A chip interconnect packaging structure, characterized in that, Include: A sub-substrate includes a substrate, multiple circuit layers and a motherboard connecting bump, and has a first surface and a second surface opposite to the first surface; the motherboard connecting bump is disposed on one of the circuit layers and is disposed around the periphery of the sub-substrate, and one side of the motherboard connecting bump is exposed to the outside of the sub-substrate. A welding layer is disposed on the side of the connecting protrusion of the mother plate; wherein, The mother plate connecting protrusion has a top surface, and the welding material layer extends from the side of the mother plate connecting protrusion to the top surface of the mother plate connecting protrusion.

10. The chip interconnect packaging structure as described in claim 9, characterized in that, Further includes: A first chip is disposed on the first surface of the sub-substrate and electrically connected to the circuit layer of the first surface; A second chip is disposed on the second surface of the sub-substrate and electrically connected to the circuit layer of the second surface. The first chip and the second chip are electrically connected to each other through the plurality of circuit layers.

11. The chip interconnect packaging structure as described in claim 10, characterized in that, Further includes: A mother substrate includes multiple circuit layers and has a sub-substrate receiving groove; the sub-substrate receiving groove penetrates at least two circuit layers therethrough; the sub-substrate receiving groove has a side wall, and the multiple circuit structures include a side contact, the side contact protruding from the side wall. The sub-substrate, the first chip, and the second chip are disposed in the sub-substrate receiving groove. The side of the motherboard connecting bump faces the side wall of the sub-substrate receiving groove, and the motherboard connecting bump of the sub-substrate is connected to the side contact of the mother substrate by the solder layer on the side.

12. The chip interconnect packaging structure as described in claim 9, characterized in that, in, The side of the connecting protrusion of the mother plate is flush with a cut surface of the substrate.

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