Thickness detection device integrated at wafer level and method for preparing VCSEL unit

Abstract

Disclosed are a wafer-level integrated thickness detection device and a method for preparing a VCSEL unit, wherein the wafer-level integrated thickness detection device comprises: a first capacitor plate, wherein during the preparation of the VCSEL unit, the insulating layer is suitable for being formed on the first capacitor plate and the P-DBR layer with equal thickness; and a second capacitor plate superimposed on the insulating layer; wherein the thickness of the insulating layer is suitable for being determined based on the capacitance value between the first capacitor plate and the second capacitor plate, the relative dielectric constant of the insulating layer, and the length and width of the second capacitor plate. The thickness detection device can reduce the detection cost and quickly detect the thickness of the insulating layer formed on the laser emission path of the VCSEL laser to improve the detection efficiency.

Description

Technical Field

[0001] This application relates to the field of semiconductor lasers, and more specifically to a thickness detection device integrated at the wafer level, a thickness measurement method for VCSEL units, and a preparation method for VCSEL units. Background Art

[0002] A VCSEL (Vertical-Cavity Surface-Emitting Laser) is a semiconductor laser that forms a resonant cavity in the vertical direction of a substrate and emits laser light in the vertical direction.

[0003] The VCSEL laser has an insulating layer in its light-emitting path, and the insulating layer is used to modulate the emitted laser light so that the wavelength of the emitted laser light meets the design requirements. For example, in a VCSEL laser with front-side light emission, the insulating layer is provided above the P-DBR layer. The selection of the thickness and material of the insulating layer will affect the performance of the laser light emitted by the VCSEL laser. Therefore, during the preparation process, it is necessary to ensure that the thickness of the insulating layer meets the design requirements to ensure the light-emitting performance of the VCSEL laser.

[0004] In the existing VCSEL preparation process, there are some technical solutions for detecting this insulating layer. For example, the thickness of the insulating layer is detected by a Focused Ion Beam (FIB) and a Transmission Electron Microscope (TEM). However, the detection cost of this detection solution is expensive. The cost of detecting only individual regions (such as the central region and the edge region) of the VCSEL chip is usually as high as tens of thousands of yuan, and the cost of detecting each region of the VCSEL chip usually exceeds 100,000 yuan. Moreover, the detection time of this detection solution is relatively long, and it takes about 2 hours to detect a single sample (VCSEL chip).

[0005] Therefore, an optimized thickness detection solution is needed to reduce the detection cost and improve the detection efficiency. Summary of the Invention

[0006] An advantage of this application is to provide a thickness detection device integrated at the wafer level, a thickness measurement method for VCSEL units, and a preparation method for VCSEL units. Among them, compared with a focused ion beam and a transmission electron microscope, the preparation cost of the thickness detection device integrated at the wafer level is greatly reduced, and the detection process is relatively simple, so that the detection cost of detecting the thickness of the insulating layer formed in the laser light-emitting path of the VCSEL laser is reduced.

[0007] Another advantage of the present application is to provide a thickness detection device integrated at the wafer level, a thickness measurement method for VCSEL units, and a preparation method for VCSEL units. Among them, since the thickness detection device is integrated at the wafer level with a VCSEL unit (including at least one VCSEL laser), and the insulating layer can be formed with equal thickness on the first capacitor plate of the thickness detection device and the P-DBR layer of the VCSEL laser, the thickness detection device can relatively accurately measure the thickness of the insulating layer by using the relationship between its capacitance value and the thickness of the insulating layer.

[0008] To achieve the above-mentioned at least one advantage or other advantages and purposes, according to one aspect of the present application, there is provided a thickness detection device integrated at the wafer level, which includes:

[0009] A first capacitor plate, wherein during the preparation process of the VCSEL unit, the insulating layer is adapted to be formed with equal thickness on the first capacitor plate and the P-DBR layer; and,

[0010] A second capacitor plate stacked on the insulating layer;

[0011] Wherein, the thickness of the insulating layer is adapted to be determined based on the capacitance value between the first capacitor plate and the second capacitor plate, the relative dielectric constant of the insulating layer, and the length and width of the second capacitor plate.

[0012] In the thickness detection device integrated at the wafer level according to the present application, the upper surface of the second capacitor plate is higher than or flush with the upper surface of the P-DBR layer.

[0013] In the thickness detection device integrated at the wafer level according to the present application, the first capacitor plate includes a capacitor plate body and an electrical connection leg extending upward from the capacitor plate body, and the upper surface of the electrical connection leg is higher than or flush with the upper surface of the P-DBR layer.

[0014] According to another aspect of the present application, there is provided a thickness measurement method, which includes:

[0015] Measuring the capacitance value between the first capacitor plate and the second capacitor plate, wherein an insulating layer with the same thickness as the insulating layer formed on the P-DBR layer is provided between the first capacitor plate and the second capacitor plate; and

[0016] Based on the capacitance value, the relative dielectric constant of the insulating layer, the length and width of the second capacitor plate, calculating the thickness of the insulating layer formed on the P-DBR layer.

[0017] According to still another aspect of the present application, there is provided a preparation method for VCSEL units, which includes:

[0018] An epitaxial structure is provided, which includes, from bottom to top: a substrate layer, an N-DBR layer, an active region, and a P-DRB layer;

[0019] The epitaxial structure is etched to form at least two mesa structures and a receiving cavity extending downward to the N-DBR layer between the two mesa structures, and each mesa structure includes a part of the N-DBR layer, a part of the active region, and a part of the P-DBR layer;

[0020] A first capacitor plate is disposed in the receiving cavity, wherein the first capacitor plate is stacked on the N-DBR layer;

[0021] An insulating layer with an equal thickness is formed on the P-DBR layer and the first capacitor plate;

[0022] A second capacitor plate is stacked on the insulating layer formed on the first capacitor plate;

[0023] The capacitance value between the first capacitor plate and the second capacitor plate is measured, and the thickness of the insulating layer is calculated based on the capacitance value, the relative dielectric constant of the insulating layer, the length and width of the second capacitor plate;

[0024] After the final thickness of the insulating layer meets the preset requirements, a confinement layer is formed above the active region in each mesa structure, and the confinement layer has confinement holes corresponding to the active region;

[0025] The edge portion of the insulating layer is etched and a P-type ohmic contact resistance is formed at the etched position;

[0026] A positive electrode electrically connected to the P-type ohmic contact resistance is formed on the P-type ohmic contact resistance, and the positive electrode forms a light-emitting hole corresponding to the confinement hole; and

[0027] A negative electrode electrically connected to the N-DBR layer is formed to form a VCSEL chip semi-finished product including at least one VCSEL unit.

[0028] In the method for preparing a VCSEL unit according to the present application, after the final thickness of the insulating layer meets the preset requirements, the method further includes: forming another insulating layer with an equal thickness on the insulating layer and the first capacitor plate; stacking a third capacitor plate on the another insulating layer; and measuring the second capacitance value between the first capacitor plate and the third capacitor plate, and calculating the thickness of the another insulating layer based on the second capacitance value, the relative dielectric constant of the another insulating layer, the length and width of the third capacitor plate.

[0029] In the method for manufacturing a VCSEL unit according to the present application, the upper surface of the second capacitor plate and / or the third capacitor plate is higher than or flush with the upper surface of the P-DBR layer.

[0030] In the method for manufacturing a VCSEL unit according to the present application, the insulating layer and the other insulating layer are made of different materials.

[0031] In the method for manufacturing a VCSEL unit according to the present application, the insulating layer has a first refractive index, the other insulating layer has a second refractive index, the insulating layer has a first thickness, and the other insulating layer has a second thickness, wherein the product of the first refractive index and the first thickness plus the product of the second refractive index and the second thickness is equal to the wavelength value of the laser emitted by the VCSEL unit.

[0032] In the method for manufacturing a VCSEL unit according to the present application, the first capacitor plate includes a capacitor plate body and an electrical connection leg extending upward from the capacitor plate body, and the upper surface of the electrical connection leg is higher than or flush with the upper surface of the P-DBR layer.

[0033] In the method for manufacturing a VCSEL unit according to the present application, forming a confinement layer above the active region in each of the mesa structures includes: forming an oxidation confinement layer above the active region in each of the mesa structures through an oxidation process, wherein each of the oxidation confinement layers has an oxidation confinement hole corresponding to the active region.

[0034] In the method for manufacturing a VCSEL unit according to the present application, forming a negative electrode electrically connected to the N-DBR layer includes: forming the negative electrode on the lower surface of the substrate layer.

[0035] In the method for manufacturing a VCSEL unit according to the present application, etching an edge portion of the insulating layer and forming a P-type ohmic contact resistance at the etched position can be performed before the final thickness of the insulating layer meets a preset requirement.

[0036] In the method for manufacturing a VCSEL unit according to the present application, the method for manufacturing a VCSEL unit further includes: dividing the VCSEL chip semi-finished product to obtain at least two VCSEL chips, wherein each of the VCSEL chips includes at least one of the VCSEL units.

[0037] Through the understanding of the subsequent description and the drawings, further objects and advantages of the present application will be fully embodied.

[0038] These and other objects, features, and advantages of the present application will be fully embodied through the following detailed description, the drawings, and the claims. Description of the Drawings

[0039] These and / or other aspects and advantages of the present application will become more apparent and easier to understand from the following detailed description of the embodiments of the present invention in conjunction with the accompanying drawings, in which:

[0040] Figure 1 The figure shows a schematic diagram of a thickness detection device integrated at the wafer level according to an embodiment of the present application.

[0041] Figure 2 The figure shows a flowchart of a thickness measurement method for a VCSEL unit according to an embodiment of the present application.

[0042] Figure 3 The figure shows a flowchart of a preparation method for a VCSEL unit according to an embodiment of the present application.

[0043] Figure 4A The figure shows one of the schematic diagrams of the preparation process of a VCSEL unit according to an embodiment of the present application.

[0044] Figure 4B The figure shows another schematic diagram of the preparation process of a VCSEL unit according to an embodiment of the present application.

[0045] Figure 4C The figure shows a further schematic diagram of the preparation process of a VCSEL unit according to an embodiment of the present application.

[0046] Figure 4D The figure shows yet another schematic diagram of the preparation process of a VCSEL unit according to an embodiment of the present application.

[0047] Figure 4E The figure shows still another schematic diagram of the preparation process of a VCSEL unit according to an embodiment of the present application.

[0048] Figure 4F The figure shows another schematic diagram of the preparation process of a VCSEL unit according to an embodiment of the present application. Detailed Embodiments

[0049] The terms and words used in the following description and claims are not limited to the literal meanings, but are used by the inventors only to enable a clear and consistent understanding of the present application. Therefore, it will be apparent to those skilled in the art that the following description of the various embodiments of the present application is provided for illustrative purposes only and not for the purpose of limiting the present application as defined by the appended claims and their equivalents.

[0050] It can be understood that the term "a" should be construed as "at least one" or "one or more". That is, in one embodiment, the number of an element can be one, while in other embodiments, the number of the element can be multiple. The term "a" should not be construed as a limitation on the number.

[0051] Although ordinal numbers such as "first", "second", etc. will be used to describe various components, those components are not limited herein. The term is only used to distinguish one component from another. For example, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component without departing from the teachings of the inventive concept. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0052] The terms used herein are for the purpose of describing various embodiments only and are not intended to be limiting. As used herein, the singular forms are also intended to include the plural forms unless the context clearly indicates otherwise. Additionally, it will be understood that the terms "comprising" and / or "having" when used in this specification specify the presence of the stated features, numbers, steps, operations, components, elements, or combinations thereof, without precluding the presence or addition of one or more other features, numbers, steps, operations, components, elements, or combinations thereof.

[0053] Overview of the Application

[0054] As described above, the VCSEL laser has an insulating layer in its emission path, and the insulating layer is used to modulate the emitted laser so that the wavelength of the emitted laser meets the design requirements. For example, in a VCSEL laser with front emission, the insulating layer is provided above the P-DBR layer. The selection of the thickness and material of the insulating layer will affect the performance of the laser emitted by the VCSEL laser. Therefore, during the preparation process, it is necessary to ensure that the thickness of the insulating layer meets the design requirements to ensure the light emission performance of the VCSEL laser.

[0055] In the existing VCSEL manufacturing process, there are some technical solutions for detecting this insulating layer. For example, the thickness of the insulating layer is detected by a Focused Ion Beam (FIB) and a Transmission Electron Microscope (TEM). However, the detection cost of this detection solution is expensive. The cost of detecting only individual areas (such as the central area and the edge area) of the VCSEL chip is usually as high as tens of thousands of yuan, and the cost of detecting each area of the VCSEL chip usually requires more than one hundred thousand yuan for detection. Moreover, the detection time of this detection solution is relatively long, and it takes about 2 hours to detect a single sample (VCSEL chip).

[0056] Therefore, an optimized thickness detection solution is needed.

[0057] In view of the above technical problems, the technical concept of the present application is as follows: by integrating a thickness detection device and a VCSEL unit capable of detecting the thickness of the insulating layer at the wafer level, the detection cost can be reduced and the detection efficiency can be improved. Specifically, the detection cost is reduced and the detection efficiency is improved by simplifying the structure of the thickness detection device and the detection method.

[0058] Based on this, according to one aspect of the present application, a thickness detection device integrated at the wafer level is proposed, which includes: a first capacitor plate, wherein, during the preparation process of the VCSEL unit, the insulating layer is adapted to be formed on the first capacitor plate and the P-DBR layer with equal thickness; and a second capacitor plate stacked on the insulating layer; wherein, the thickness of the insulating layer is adapted to be determined based on the capacitance value between the first capacitor plate and the second capacitor plate, the relative permittivity of the insulating layer, and the length and width of the second capacitor plate.

[0059] According to another aspect of the present application, a thickness measurement method for a VCSEL unit is proposed, which includes: measuring the capacitance value between the first capacitor plate and the second capacitor plate, wherein an insulating layer with the same thickness as the insulating layer formed on the P-DBR layer is provided between the first capacitor plate and the second capacitor plate; and calculating the thickness of the insulating layer formed on the P-DBR layer based on the capacitance value, the relative permittivity of the insulating layer, and the length and width of the second capacitor plate.

[0060] According to another aspect of the present application, the present application provides a method for manufacturing a VCSEL unit, which includes: providing an epitaxial structure, the epitaxial structure including, from bottom to top: a substrate layer, an N-DBR layer, an active region, and a P-DRB layer; etching the epitaxial structure to form at least two mesa structures and a receiving cavity extending downward to the N-DBR layer between the two mesa structures, each mesa structure including a part of the N-DBR layer, a part of the active region, and a part of the P-DBR layer; disposing a first capacitor plate in the receiving cavity, wherein the first capacitor plate is stacked on the N-DBR layer; forming an insulating layer with equal thickness on the P-DBR layer and the first capacitor plate; stacking a second capacitor plate on the insulating layer formed on the first capacitor plate; measuring the capacitance value between the first capacitor plate and the second capacitor plate, and calculating the thickness of the insulating layer based on the capacitance value, the relative dielectric constant of the insulating layer, the length and width of the second capacitor plate; after the final thickness of the insulating layer meets the preset requirements, forming a confinement layer above the active region in each mesa structure, the confinement layer having a confinement hole corresponding to the active region; etching an edge portion of the insulating layer and forming a P-type ohmic contact resistance at the etched position; forming a positive electrode electrically connected to the P-type ohmic contact resistance on the P-type ohmic contact resistance, the positive electrode forming a light-emitting hole corresponding to the confinement hole; and forming a negative electrode electrically connected to the N-DBR layer to form a VCSEL chip semi-finished product including at least one VCSEL unit.

[0061] After introducing the basic principles of the present application, various non-limiting embodiments of the present application will be specifically introduced below with reference to the accompanying drawings.

[0062] Schematic Thickness Detection Device

[0063] As Figure 1 shown, a thickness detection device 100 integrated at the wafer level according to an embodiment of the present application is illustrated, wherein the thickness detection device 100 integrated at the wafer level is used to measure the thickness of the insulating layer 40 formed on the P-DBR layer 250 in the VCSEL unit 600. Here, the VCSEL unit 600 may represent a VCSEL light-emitting point (i.e., the VCSEL light-emitting unit includes a light-emitting body), or may represent a light-emitting region composed of multiple VCSEL light-emitting points (i.e., the VCSEL light-emitting unit includes two or more light-emitting bodies, and a light-emitting region formed by the two or more light-emitting bodies).

[0064] The VCSEL unit 600 mainly forms the resonant cavity through an N-type distributed Bragg reflector (N-DBR) and a P-type distributed Bragg reflector (P-DBR). After being excited, photons are reflected back and forth in the resonant cavity and continuously amplified to form a laser oscillation, thereby forming a laser. The formed laser can exit from the N-DBR layer 220 or the P-DBR layer 250.

[0065] In the actual industry, the VCSEL unit 600 has an insulating layer on its light-emitting path. The insulating layer is used to modulate the emitted laser so that the wavelength of the emitted laser meets the design requirements. For example, in the VCSEL unit 600 with front-side light emission, the insulating layer is provided above the P-DBR layer. The choice of the thickness and material of the insulating layer will affect the performance of the laser emitted by the VCSEL unit 600. Therefore, during the preparation process, it is necessary to ensure that the thickness of the insulating layer meets the design requirements to ensure the light-emitting performance of the VCSEL unit 600.

[0066] In the embodiment of the present application, the thickness detection device 100 can be integrated at the wafer level with the VCSEL unit 600. After the VCSEL wafer including at least one VCSEL unit 600 is formed, the thickness detection device 100 can detect the thickness of the insulating layer 40 formed on the laser emission path of the VCSEL unit 600. Moreover, the thickness detection device 100 can quickly detect the thickness of the insulating layer 40, and the detection time can be counted in seconds, that is, the detection duration is at the second level, and the detection efficiency of the thickness detection device 100 is relatively high.

[0067] After detecting the thickness of the insulating layer 40 of the current batch of VCSEL wafers, the thickness of the insulating layer 40 of the next batch of VCSEL wafers to be formed can be adjusted according to the detection results of the current samples to meet the performance requirements of the laser emitted by the VCSEL unit 600. For example, the thickness of the insulating layer 40 meets the following requirements: λ=n 1 *d 1 +n 2 *d 2 +……+n m *d m (where λ represents the preset wavelength of the laser emitted by the VCSEL unit 600, n 1 、n 2 、……、n m respectively represent the refractive indices of the first layer, the second layer, ……, the mth layer of the insulating layer 40, and d 1 、d 2 、……、d m respectively represent the thicknesses of the first layer, the second layer, ……, the mth layer of the insulating layer 40).

[0068] Specifically, the thickness detection device 100 can relatively accurately measure the thickness of the insulating layer 40 by utilizing the relationship between its capacitance value and the thickness of the insulating layer 40. As Figure 1 shown, the thickness detection device 100 integrated at the wafer level includes: a first capacitor plate 10 and a second capacitor plate 20. In particular, during the preparation process of the VCSEL unit 600, the insulating layer 40 is adapted to be formed with a uniform thickness on the first capacitor plate 10 and the P-DBR layer 250, and the second capacitor plate 20 is stacked on the insulating layer 40. The thickness of the insulating layer 40 can be calculated by the following formula, where the formula is:

[0069]

[0070] In the above formula, d represents the thickness of the insulating layer 40, ε 0 represents the vacuum permittivity, ε r represents the relative permittivity of the insulating layer 40, S represents the area of the portions of the first capacitor plate 10 and the second capacitor plate 20 that face each other, C represents the capacitance value between the first capacitor plate 10 and the second capacitor plate 20, where the relative permittivity of the insulating layer 40 is the ratio of the permittivity of the insulating layer 40 to the vacuum permittivity.

[0071] In the embodiments of the present application, the area of the portions of the first capacitor plate 10 and the second capacitor plate 20 that face each other is equal to the area of the second capacitor plate 20. Correspondingly, the thickness of the insulating layer 40 is adapted to be determined based on the capacitance value between the first capacitor plate 10 and the second capacitor plate 20, the relative permittivity of the insulating layer 40, and the length and width of the second capacitor plate 20.

[0072] In the embodiments of the present application, the number of the first capacitor plates 10 can be 1, 2, 3, or more, and this is not limited by the present application. The number of the second capacitor plates 20 is 1, 2, 3, or more, depending on the number of layers of the insulating layer 40. One layer of the insulating layer 40 can be provided between each second capacitor plate 20 and the capacitor plate.

[0073] Preferably, regardless of whether the number of the first capacitor plates 10 is 1, 2, 3, or more, the first capacitor plate 10 has an integral structure, and the number of the second capacitor plates 20 is consistent with the number of layers of the insulating layer 40. In this way, each layer of the insulating layer 40 is adapted to be measured by conducting the first capacitor plate 10 and the corresponding second capacitor plate 20.

[0074] Furthermore, the thickness detection device 100 can be formed on the VCSEL chip semi-finished product 500 (VCSEL wafer) during the formation of the VCSEL unit 600. For example, it can be formed in the accommodation cavity 401 of the VCSEL unit 600, or in the scribe lane 402 of the VCSEL chip semi-finished product 500. Taking the thickness detection device 100 formed in the accommodation cavity 401 of the VCSEL unit 600 as an example, as Figure 1 shown, in order to facilitate the electrical connection of the first capacitor plate 10 and the second capacitor plate 20 to other devices (such as capacitor testing equipment), in the embodiments of the present application, the first capacitor plate 10 is provided with an electrical connection leg 12 whose upper surface is higher than or flush with the upper end surface of the accommodation cavity 401, and the second capacitor plate 20 is arranged such that its upper surface is higher than or flush with the upper end surface of the accommodation cavity 401. In this way, when the electrical connection end of the capacitor testing equipment is electrically connected to the first capacitor plate 10 and the second capacitor plate 20 of the thickness detection device 100, the capacitance value between the first capacitor plate 10 and the second capacitor plate 20 can be easily measured without having to reach deep into the accommodation cavity 401.

[0075] The upper end surface of the accommodation cavity 401 is higher than or flush with the upper surface of the P-DBR layer 250 of the VCSEL unit 600. Then, the upper surface of the electrical connection leg 12 is higher than or flush with the upper surface of the P-DBR layer 250. Correspondingly, the first capacitor plate 10 includes a capacitor plate main body 11 and an electrical connection leg 12 extending upward from the capacitor plate main body 11, and the upper surface of the electrical connection leg 12 is higher than or flush with the upper surface of the P-DBR layer 250. The upper surface of the second capacitor plate 20 is higher than or flush with the upper surface of the P-DBR layer 250.

[0076] It is worth mentioning that compared with focused ion beam and transmission electron microscope, the structure of the thickness detection device 100 is relatively simple, the manufacturing cost is greatly reduced, and the detection cost is reduced accordingly. Moreover, the thickness detection device 100 is easy to operate, which can reduce the labor cost during the detection process to further reduce the detection cost.

[0077] It is also worth mentioning that in the above embodiments of the application, the thickness detection device 100 is introduced by taking the laser emission direction of the VCSEL unit 600 as emitting from the P-DBR layer 250 as an example. In practical applications, the thickness detection device 100 can also be applied to the VCSEL unit 600 whose laser emission direction is from the N-DBR layer 250.

[0078] In summary, the thickness detection device 100 based on the embodiments of the present application is described. The thickness detection device 100 is integrated into the VCSEL unit 600 at the wafer level, which can reduce the detection cost and quickly detect the thickness of the insulating layer 40 formed on the laser emission path of the VCSEL unit 600, so as to improve the detection efficiency of the thickness detection device 100.

[0079] Schematic Thickness Measurement Method

[0080] According to another aspect of the present application, a thickness measurement method for the VCSEL unit 600 is also provided. As Figure 1 shown, the thickness detection device 100 can detect the thickness of the insulating layer 40 on the P-DBR layer 250 of the VCSEL unit 600 through this thickness measurement method. Referring to the accompanying drawings of the specification Figure 2 , the thickness measurement method according to the embodiments of the present application is described. As Figure 2 shown, the thickness measurement method for the VCSEL unit 600 according to the embodiments of the present application includes: S110, measuring the capacitance value between the first capacitor plate 10 and the second capacitor plate 20, wherein an insulating layer 40 having the same thickness as the insulating layer 40 formed on the P-DBR layer 250 is provided between the first capacitor plate 10 and the second capacitor plate 20; and S120, calculating the thickness of the insulating layer 40 formed on the P-DBR layer 250 based on the capacitance value, the relative permittivity of the insulating layer 40, the length and width of the second capacitor plate 20.

[0081] In step S110, the capacitance value between the first capacitor plate 10 and the second capacitor plate 20 is measured. According to the calculation principle of capacitance, there is a functional relationship between the capacitance value between the first capacitor plate 10 and the second capacitor plate 20 and the thickness of the medium between the first capacitor plate 10 and the second capacitor plate 20. The thickness of the medium between the first capacitor plate 10 and the second capacitor plate 20 can be measured by measuring the capacitance value between the first capacitor plate 10 and the second capacitor plate 20.

[0082] An insulating layer 40 having the same thickness as the insulating layer 40 formed on the P-DBR layer 250 is provided between the first capacitor plate 10 and the second capacitor plate 20, that is, the thickness of the medium between the first capacitor plate 10 and the second capacitor plate 20 is equal to the insulating layer 40 having the same thickness as the insulating layer 40 formed on the P-DBR layer 250. Therefore, the thickness of the insulating layer 40 formed on the P-DBR layer 250 can be measured by measuring the capacitance value between the first capacitor plate 10 and the second capacitor plate 20.

[0083] Specifically, the capacitance value between the first capacitor plate 10 and the second capacitor plate 20 is measured by a capacitance testing device electrically connected to the thickness detection device 100. More specifically, the first electrical connection terminal of the capacitance testing device is electrically connected to the first capacitor plate 10, and the second connection terminal of the capacitance testing device is electrically connected to the second capacitor plate 20 to measure the capacitance value between the first capacitor plate 10 and the second capacitor plate 20.

[0084] In step S120, based on the capacitance value, the relative permittivity of the insulating layer 40, the length and width of the second capacitor plate 20, the thickness of the insulating layer 40 formed on the P-DBR layer 250 is calculated. Specifically, the thickness of the insulating layer 40 can be calculated by the following formula, where the formula is:

[0085]

[0086] In the above formula, d represents the thickness of the insulating layer 40, ε 0 represents the vacuum permittivity, ε r represents the relative permittivity of the insulating layer 40, S represents the area of the portion where the first capacitor plate 10 and the second capacitor plate 20 face each other, C represents the capacitance value between the first capacitor plate 10 and the second capacitor plate 20, where the relative permittivity of the insulating layer 40 is the ratio of the permittivity of the insulating layer 40 to the vacuum permittivity.

[0087] In the embodiment of the present application, the area of the portion where the first capacitor plate 10 and the second capacitor plate 20 face each other is equal to the area of the second capacitor plate 20. Further, the area of the second capacitor plate 20 can be calculated based on the length and width of the second capacitor plate 20.

[0088] In summary, the thickness measurement method for the VCSEL unit 600 based on the embodiment of the present application is clarified. The thickness measurement method for the VCSEL unit 600 is relatively simple and can reduce the detection cost.

[0089] Schematic Preparation Method of VCSEL Unit

[0090] According to another aspect of the present application, a manufacturing method of a VCSEL unit 600 is further provided, as Figure 3As shown, the manufacturing method of the VCSEL unit 600 is illustrated. The manufacturing method of the VCSEL unit 600 according to an embodiment of the present application includes: Step 1, providing an epitaxial structure, which includes, from bottom to top: a substrate layer, an N-DBR layer, an active region, and a P-DRB layer; Step 2, etching the epitaxial structure to form at least two mesa structures and forming a receiving cavity extending downward to the N-DBR layer between the two mesa structures, each mesa structure including a part of the N-DBR layer, a part of the active region, and a part of the P-DRB layer; Step 3, disposing a first capacitor plate in the receiving cavity, wherein the first capacitor plate is stacked on the N-DBR layer; Step 4, forming an insulating layer with equal thickness on the P-DRB layer and the first capacitor plate; Step 5, stacking a second capacitor plate on the insulating layer formed on the first capacitor plate; Step 6, measuring the capacitance value between the first capacitor plate and the second capacitor plate, and calculating the thickness of the insulating layer based on the capacitance value, the relative dielectric constant of the insulating layer, the length and width of the second capacitor plate; Step 7, after the final thickness of the insulating layer meets the preset requirements, forming a confinement layer above the active region in each mesa structure, the confinement layer having confinement holes corresponding to the active region; Step 8, etching an edge portion of the insulating layer and forming a P-type ohmic contact resistance at the etched position; Step 9, forming a positive electrode electrically connected to the P-type ohmic contact resistance on the P-type ohmic contact resistance, the positive electrode forming a light-emitting hole corresponding to the confinement hole; and, Step 10, forming a negative electrode electrically connected to the N-DBR layer to form a VCSEL chip semi-finished product including at least one VCSEL unit.

[0091] Figures 4A to 4F The figure illustrates a schematic diagram of the manufacturing process of the VCSEL unit 600. As Figure 4A shown, in Step 1, an epitaxial structure 200 is provided. Specifically, the substrate layer 210 is formed by a semiconductor growth process, and then the N-DBR layer 220, the active region 230, and the P-DRB layer 250 located above the substrate layer 210 are sequentially formed. The active region 230 is sandwiched between the N-DBR layer 220 and the P-DRB layer 250 to form a resonant cavity. After being excited, photons reflect back and forth in the resonant cavity and are continuously amplified repeatedly to form a laser oscillation, thereby forming a laser. By configuring and designing the N-DBR layer 220 and the P-DRB layer 250, the emission direction of the laser can be selectively controlled. For example, it can be emitted from the N-DBR layer 220, or from the P-DRB layer 250.

[0092] As Figure 4AAs shown, in step 2, the epitaxial structure 200 is etched to form at least two mesa structures 300 and a receiving cavity 401 is formed between the two mesa structures 300 and extends downward to the N-DBR layer 220. Specifically, first, an etchable layer is applied on the epitaxial structure 200. The material of the etchable layer can be a photoresist layer. Then, the etchable layer is exposed through the mask with a preset pattern to remove the corresponding part of the etchable layer based on the preset pattern. The remaining etchable layer forms a template with a preset shape and size, and the preset shape and size of the template are consistent with the shape and size of the mesa structure 300. Then, at least a part of the epitaxial structure 200 and the template are removed through an etching process to form the at least two mesa structures 300 and the receiving cavity 401 that extends downward to the N-DBR layer 220 between the two mesa structures 300. Each mesa structure 300 includes a part of the N-DBR layer 220, a part of the active region 230, and a part of the P-DBR layer 250.

[0093] That is, step 2 includes: applying an etchable layer on the epitaxial structure 200, shaping the etchable material into a template with a preset shape and size through a mask, where the preset shape and size of the template are consistent with the shape and size of the mesa structure 300; and removing at least a part of the epitaxial structure 200 and the template through an etching process to form the at least two mesa structures 300 and the receiving cavity 401 that extends downward to the N-DBR layer 220 between the two mesa structures 300.

[0094] Particularly, after forming the at least two mesa structures 300 and the receiving cavity 401 that extends downward to the N-DBR layer 220 between the two mesa structures 300, during the process of forming the insulating layer 40 on the P-BDR layer, a first capacitor plate 10 and a second capacitor plate 20 for detecting the thickness of the insulating layer 40 can be formed in the receiving cavity 401 to form a thickness detection device 100 for detecting the thickness of the insulating layer 40.

[0095] Correspondingly, as Figure 4BAs shown, in step 3, a first capacitor plate 10 is disposed within the receiving cavity 401. The first capacitor plate 10 is stacked on the N-DBR layer 220, that is, on the bottom of the receiving cavity 401. And preferably, the upper surfaces of the first capacitor plate 10 and the P-BDR layer are both flat and parallel to each other. Specifically, the first capacitor plate 10 can be deposited on the N-DBR layer 220 through a deposition process to dispose the first capacitor plate 10 within the receiving cavity 401. Of course, the first capacitor plate 10 can also be stacked on the N-DBR layer 220 by other means, such as an electroplating process.

[0096] It is worth mentioning that, in order to facilitate electrically connecting the first capacitor plate 10 to other devices (such as a capacitance testing device), the first capacitor plate 10 is provided with an electrical connection leg 12 whose upper surface is higher than or flush with the upper end surface of the receiving cavity 401. In this way, the electrical connection end of other devices can be easily electrically connected to the first capacitor plate 10 without having to extend deep into the receiving cavity 401. The upper end surface of the receiving cavity 401 is higher than or flush with the upper surface of the P-DBR layer 250, then the upper surface of the electrical connection leg 12 is higher than or flush with the upper surface of the P-DBR layer 250. Correspondingly, the first capacitor plate 10 includes a capacitor plate body 11 and an electrical connection leg 12 extending upward from the capacitor plate body 11, and the upper surface of the electrical connection leg 12 is higher than or flush with the upper surface of the P-DBR layer 250.

[0097] In step 4, an insulating layer 40 of equal thickness is formed on the P-DBR layer 250 and the first capacitor plate 10. Specifically, the insulating layer 40 of equal thickness can be formed on the P-DBR layer 250 and the first capacitor plate 10 through a deposition process. And the upper surface of the insulating layer 40 is parallel to the upper surface of the P-BDR layer and the upper surface of the first capacitor plate 10.

[0098] As Figure 4C shown, in step 5, a second capacitor plate 20 is stacked on the insulating layer 40 formed on the first capacitor plate 10 to form a thickness detection device 100. According to the calculation principle of capacitance, there is a functional relationship between the capacitance value between the first capacitor plate 10 and the second capacitor plate 20 and the thickness of the medium between the first capacitor plate 10 and the second capacitor plate 20. The thickness of the medium between the first capacitor plate 10 and the second capacitor plate 20 can be measured by measuring the capacitance value between the first capacitor plate 10 and the second capacitor plate 20.

[0099] In an embodiment of the present application, the insulating layer 40 formed on the first capacitor plate 10 is sandwiched between the first capacitor plate 10 and the second capacitor plate 20. That is, the insulating layer 40 formed on the first capacitor plate 10 serves as the dielectric between the first capacitor plate 10 and the second capacitor plate 20. Moreover, the insulating layer 40 formed on the P-DBR layer 250 has the same thickness as the insulating layer 40 formed on the first capacitor plate 10. Therefore, the thickness of the insulating layer 40 formed on the first capacitor plate 10 measured by measuring the capacitance value between the first capacitor plate 10 and the second capacitor plate 20 is the thickness of the insulating layer 40 on the P-DBR layer 250.

[0100] Correspondingly, in step 6, the capacitance value between the first capacitor plate 10 and the second capacitor plate 20 is measured, and the thickness of the insulating layer 40 is calculated based on the capacitance value, the relative permittivity of the insulating layer 40, the length and width of the second capacitor plate 20.

[0101] Specifically, the thickness of the insulating layer 40 can be calculated by the following formula, where the formula is:

[0102]

[0103] In the above formula, d represents the thickness of the insulating layer 40, ε 0 represents the vacuum permittivity, ε r represents the relative permittivity of the insulating layer 40, S represents the area of the portion of the first capacitor plate 10 and the second capacitor plate 20 facing each other, C represents the capacitance value between the first capacitor plate 10 and the second capacitor plate 20, where the relative permittivity of the insulating layer 40 is the ratio of the permittivity of the insulating layer 40 to the vacuum permittivity.

[0104] In an embodiment of the present application, the area of the portion of the first capacitor plate 10 and the second capacitor plate 20 facing each other is equal to the area of the second capacitor plate 20. Further, the area of the second capacitor plate 20 can be calculated based on the length and width of the second capacitor plate 20.

[0105] It is worth mentioning that, for the convenience of electrically connecting the second capacitor plate 20 to other devices (for example, capacitance testing devices), the upper surface of the second capacitor plate 20 is set to be higher than or flush with the upper end surface of the receiving cavity 401. As mentioned above, the upper end surface of the receiving cavity 401 is higher than or flush with the upper surface of the P-DBR layer 250. Then, the upper surface of the second capacitor plate 20 is higher than or flush with the upper surface of the P-DBR layer 250.

[0106] It is also worth mentioning that two or more insulating layers 40 may be formed on the P-DBR layer 250 and the first capacitor plate 10. Accordingly, as Figure 4C and 4D shown, after the final thickness of the insulating layer 40 meets the preset requirements, another insulating layer 50 with the same thickness may be formed on the insulating layer 40 formed on the P-DBR layer 250 and the first capacitor plate 10, that is, the thickness of the other insulating layer 50 formed on the insulating layer 40 is equal to the thickness of the other insulating layer 50 formed on the first capacitor plate 10; then, a third capacitor plate 30 is stacked on the other insulating layer 50 to form another thickness detection device 100; then, the second capacitance value between the first capacitor plate 10 and the third capacitor plate 30 is measured, and the thickness of the other insulating layer 50 is calculated based on the second capacitance value, the relative permittivity of the other insulating layer 50, the length and width of the third capacitor plate 30.

[0107] That is, after the final thickness of the insulating layer 40 meets the preset requirements, the method for measuring the thickness of the VCSEL unit 600 further includes: forming another insulating layer 50 with the same thickness on the insulating layer 40 and the first capacitor plate 10; stacking a third capacitor plate 30 on the other insulating layer 50; and measuring the second capacitance value between the first capacitor plate 10 and the third capacitor plate 30, and calculating the thickness of the other insulating layer 50 based on the second capacitance value, the relative permittivity of the other insulating layer 50, the length and width of the third capacitor plate 30.

[0108] It is worth mentioning that, in order to facilitate the electrical connection of the third capacitor plate 30 to other devices (for example, capacitance testing devices), the upper surface of the third capacitor plate 30 is set to be higher than or flush with the upper end surface of the receiving cavity 401. As described above, the upper end surface of the receiving cavity 401 is higher than or flush with the upper surface of the P-DBR layer 250, then, the upper surface of the third capacitor plate 30 is higher than or flush with the upper surface of the P-DBR layer 250.

[0109] It is also worth mentioning that the insulating layer 40 and the other insulating layer 50 may be made of different materials, the insulating layer 40 has a first refractive index, the other insulating layer 50 has a second refractive index, the insulating layer 40 has a first thickness, and the other insulating layer 50 has a second thickness, wherein, the product of the first refractive index and the first thickness plus the product of the second refractive index and the second thickness is equal to the wavelength value of the laser emitted by the VCSEL unit 600.

[0110] The insulating layer 40 and the other insulating layer 50 may also be made of the same material, which is not limited to this application. When the insulating layer 40 and the other insulating layer 50 are made of the same material, the first refractive index is equal to the second refractive index.

[0111] As Figure 4D and 4E As shown, in step 7, after the final thickness of the insulating layer 40 meets the preset requirements, a confinement layer 240 is formed above the active region 230 in each mesa structure 300. Specifically, the confinement layer 240 may be formed by an oxidation process. That is, forming a confinement layer 240 above the active region 230 in each mesa structure 300 includes: forming an oxidation confinement layer 240 above the active region 230 in each mesa structure 300 by an oxidation process, wherein each oxidation confinement layer 240 has an oxidation confinement hole 201 corresponding to the active region 230.

[0112] During the process of forming the confinement layer 240 by an oxidation process, first, in order to protect the first capacitor plate 10 and the second capacitor plate 20, a protective layer 800 covering the first capacitor plate 10 and the second capacitor plate 20 needs to be formed before oxidizing the mesa structure 300; then, the mesa structure 300 is oxidized. After the mesa structure 300 is oxidized, a part of the P-DBR layer 250 of the mesa structure 300 is oxidized to form an oxidation confinement layer 240 above the active region 230, wherein each oxidation confinement layer 240 has an oxidation confinement hole 201 corresponding to the active region 230; then, the first capacitor plate 10 and the second capacitor plate 20 are exposed.

[0113] It is worth mentioning that the confinement layer 240 may be formed by other processes. For example, an ion confinement layer 240 above the active region 230 may be formed by an ion implantation process, which is not limited to this application.

[0114] As Figure 4E As shown, in step 8, the edge portion of the insulating layer 40 is etched and a P-type ohmic contact resistance 60 is formed at the etched position. Specifically, referring to the etching process of etching the epitaxial structure 200 in step 2, the insulating layer 40 is etched, and the edge portion of the insulating layer 40 is etched such that a partial region of the upper surface of the P-DBR below the insulating layer 40 is exposed, and the P-type ohmic contact resistance 60 can be formed in this exposed partial region. The P-type ohmic contact resistance 60 formed at this position surrounds the outer periphery of the etched insulating layer 40.

[0115] As Figure 4FAs shown, in step 9, a positive electrode 70 electrically connected to the P-type ohmic contact resistance 60 is formed on the P-type ohmic contact resistance 60. In the embodiment of the present application, the VCSEL unit 600 is designed to emit laser light from the P-DBR layer 250. Correspondingly, the shape of the positive electrode 70 on the light-emitting side of the VCSEL unit 600 is designed to be annular, and the positive electrode 70 forms a light-emitting hole corresponding to the confinement hole 201, so that the laser light emitted from the P-DBR layer 250 can be emitted after passing through the light-emitting hole. Specifically, the positive electrode 70 can be formed on the P-type ohmic contact resistance 60 by an electroplating process to be electrically connected to the P-type ohmic contact resistance 60.

[0116] It is worth mentioning that the positions of the insulating layer 40 and the other insulating layer 50 correspond to the light-emitting hole and are located on the laser light-emitting path of the VCSEL unit, and can modulate the light, so that the wavelength of the emitted laser light meets the design requirements. Specifically, the insulating layer 40 has a first refractive index, the other insulating layer 50 has a second refractive index, the insulating layer 40 has a first thickness, and the other insulating layer 50 has a second thickness, where the product of the first refractive index and the first thickness plus the product of the second refractive index and the second thickness is equal to the wavelength value of the laser light emitted by the VCSEL unit.

[0117] In step 10, a negative electrode 80 electrically connected to the N-DBR layer 220 is formed to form a VCSEL chip semi-finished product 400 (VCSEL wafer) including at least one VCSEL unit 600. The VCSEL unit 600 can represent a VCSEL light-emitting point (that is, the VCSEL light-emitting unit includes a light-emitting body), or can represent a light-emitting area composed of multiple VCSEL light-emitting points (that is, the VCSEL light-emitting unit includes two or more light-emitting bodies, and a light-emitting area formed by the two or more light-emitting bodies), Figure 4F shows a partial schematic diagram of the VCSEL unit 600. The formation position of the negative electrode 80 is not limited by the present application. For example, the lower surface of the epitaxial structure 200, the side surface of the N-DBR layer 220. That is, step 10 includes: forming the negative electrode 80 on the lower surface of the epitaxial structure 200.

[0118] It is worth mentioning that there is no specific execution order requirement for steps 7 to 10. For example, etching the edge portion of the insulating layer 40 and forming the P-type ohmic contact resistance 60 at the etched position can be performed before the final thickness of the insulating layer 40 meets the preset requirements.

[0119] In the embodiment of the present application, at least two VCSEL chips 500 can be obtained by splitting the VCSEL chip semi-finished product 400, and each VCSEL chip 500 includes at least one VCSEL unit 600. That is, the method for manufacturing the VCSEL unit 600 further includes: splitting the VCSEL chip semi-finished product to obtain at least two VCSEL chips 500, wherein each VCSEL chip 500 includes at least one VCSEL unit 600. As Figure 4F shown, the VCSEL chip semi-finished product 400 has at least one splitting lane 402 and at least two partitions 403 spaced apart by the at least one splitting lane 402, and each partition 403 includes at least one VCSEL chip 500. During the process of splitting the VCSEL chip semi-finished product 400, the VCSEL chip semi-finished product 400 can be split along the splitting lane 402 to obtain a VCSEL chip 500 including at least one VCSEL unit 600.

[0120] It is also worth mentioning that in the above application embodiment, the thickness detection device 100 is introduced by taking the laser emission direction of the VCSEL unit 600 as emitting from the P-DBR layer 250 as an example. In the actual industry, the thickness detection device 100 can also be applied to the VCSEL unit 600 with the laser emission direction emitting from the N-DBR layer 250. For example, the VCSEL unit 600 emits light from the back (the lower side of the VCSEL unit 600), and the N-DBR layer 220 is located below the P-DBR layer 250, the insulating layer 40 is formed on the N-DBR layer 220, and the thickness detection device 100 is configured to detect the insulating layer 40 formed on the N-DBR layer 220. Another example is that the VCSEL unit 600 emits light from the front (the upper side of the VCSEL unit 600), and the P-DBR layer 250 is located below the N-DBR layer 220, the insulating layer 40 is formed on the P-DBR layer 220, and the thickness detection device 100 is configured to detect the insulating layer 40 formed on the P-DBR layer 220.

[0121] In summary, the method for manufacturing the VCSEL unit 600 based on the embodiment of the present application is clarified. In the method for manufacturing the VCSEL unit 600, the thickness detection device 100 for detecting the thickness of the insulating layer 40 and the thickness of the other insulating layer 50 is formed during the process of forming the VCSEL unit 600. The manufacturing process of the thickness detection device 100 is relatively simple and the cost is low.

[0122] The basic principles of the present application have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are merely examples and not limitations, and it cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present application. Additionally, the specific details disclosed above are only for illustrative and facilitating understanding purposes, rather than limitations. These details do not limit the present application to necessarily implementing with the above specific details.

Claims

1. A thickness detection device integrated at the wafer level, used to measure the thickness of the insulating layer formed on the P-DBR layer in the VCSEL unit, characterized in that: include: a first capacitor plate, wherein the insulating layer is adapted to be formed with equal thickness on the first capacitor plate and the P-DBR layer during the preparation of the VCSEL unit; and A second capacitor plate stacked on the insulating layer; The thickness of the insulating layer is suitable to be determined based on the capacitance between the first capacitor plate and the second capacitor plate, the relative dielectric constant of the insulating layer, and the length and width of the second capacitor plate.

2. The wafer-level integrated thickness detection device according to claim 1, wherein: The upper surface of the second capacitor plate is higher than or flush with the upper surface of the P-DBR layer.

3. The wafer-level integrated thickness detection device according to claim 1, wherein: The first capacitor plate includes a capacitor plate body and an electrical connection leg extending upward from the capacitor plate body, and an upper surface of the electrical connection leg is higher than or flush with an upper surface of the P-DBR layer.

4. A method for measuring the thickness of a VCSEL unit, characterized in that: include: Measuring a capacitance value between a first capacitor plate and a second capacitor plate, wherein an insulating layer having a thickness equal to that of an insulating layer formed on the P-DBR layer is provided between the first capacitor plate and the second capacitor plate; as well as The thickness of the insulating layer formed on the P-DBR layer is calculated based on the capacitance value, the relative dielectric constant of the insulating layer, and the length and width of the second capacitor plate.

5. A method for preparing a VCSEL unit, characterized in that: include: Providing an epitaxial structure, the epitaxial structure comprising from bottom to top: a substrate layer, an N-DBR layer, an active region and a P-DRB layer; Etching the epitaxial structure to form at least two mesa structures and forming a receiving cavity extending downward to the N-DBR layer between the two mesa structures, each of the mesa structures including a portion of the N-DBR layer, a portion of the active region and a portion of the P-DBR layer; A first capacitor plate is arranged in the receiving cavity, wherein the first capacitor plate is stacked on the N-DBR layer; forming an insulating layer of equal thickness on the P-DBR layer and the first capacitor plate; stacking a second capacitor plate on the insulating layer formed on the first capacitor plate; Measuring the capacitance between the first capacitor plate and the second capacitor plate, and calculating the thickness of the insulating layer based on the capacitance, the relative dielectric constant of the insulating layer, and the length and width of the second capacitor plate; After the final thickness of the insulating layer meets the preset requirements, forming a restriction layer above the active area in each of the mesa structures, wherein the restriction layer has a restriction hole corresponding to the active area; Etching the edge portion of the insulating layer and forming a P-type ohmic contact resistor at the etched position; forming a positive electrode electrically connected to the P-type ohmic contact resistor on the P-type ohmic contact resistor, the positive electrode forming a light exit hole corresponding to the limiting hole; and A negative electrode electrically connected to the N-DBR layer is formed to form a VCSEL chip semi-finished product including at least one VCSEL unit.

6. The method for preparing a VCSEL unit according to claim 5, wherein: After the final thickness of the insulating layer meets the preset requirements, the method further comprises: forming another insulating layer of equal thickness on the insulating layer and the first capacitor plate; stacking a third capacitor plate on the further insulating layer; and A second capacitance value between the first capacitor plate and the third capacitor plate is measured, and a thickness of the other insulating layer is calculated based on the second capacitance value, a relative dielectric constant of the other insulating layer, and a length and a width of the third capacitor plate.

7. The method for preparing a VCSEL unit according to claim 6, wherein: An upper surface of the second capacitor plate and / or the third capacitor plate is higher than or flush with an upper surface of the P-DBR layer.

8. The method for preparing a VCSEL unit according to claim 6, wherein: The insulating layer and the further insulating layer are made of different materials.

9. The method for preparing a VCSEL unit according to claim 8, wherein: The insulating layer has a first refractive index, the other insulating layer has a second refractive index, the insulating layer has a first thickness, and the other insulating layer has a second thickness, wherein the product of the first refractive index multiplied by the first thickness plus the product of the second refractive index and the second thickness is equal to the wavelength value of the laser emitted by the VCSEL unit.

10. The method for preparing a VCSEL unit according to claim 7, wherein: The first capacitor plate includes a capacitor plate body and an electrical connection leg extending upward from the capacitor plate body, and an upper surface of the electrical connection leg is higher than or flush with an upper surface of the P-DBR layer.

11. The method for preparing a VCSEL unit according to claim 5, wherein: Forming a confinement layer above the active region in each of the mesa structures, comprising: An oxidation restriction layer is formed above the active region in each of the mesa structures through an oxidation process, wherein each of the oxidation restriction layers has an oxidation restriction hole corresponding to the active region.

12. The method for preparing a VCSEL unit according to claim 5, wherein: Forming a negative electrode electrically connected to the N-DBR layer, comprising: The negative electrode is formed on the lower surface of the substrate layer.

13. The method for preparing a VCSEL unit according to claim 5, wherein: Etching the edge portion of the insulating layer and forming a P-type ohmic contact resistor at the etched position can be performed before the final thickness of the insulating layer meets a preset requirement.

14. The method for preparing a VCSEL unit according to claim 5, further comprising: The VCSEL chip semi-finished product is divided to obtain at least two VCSEL chips, wherein each of the VCSEL chips includes at least one VCSEL unit.

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