Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises the following steps: providing a substrate, the substrate has a first surface and a second surface arranged oppositely; forming a first dielectric layer on the first surface; forming a plurality of capacitor structures in the first dielectric layer, wherein the plurality of capacitor structures enclose an exclusion area; forming a through-silicon via structure on the second surface, one end of the through-silicon via structure penetrates through the substrate and the exclusion area along a first direction and is electrically connected with the plurality of capacitor structures. In the present disclosure, the plurality of capacitor structures are arranged around the through-silicon via structure, thereby effectively absorbing the diffusion stress generated when the through-silicon via structure is formed, protecting the through-silicon via structure, and further improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the continuous advancement of integrated circuit manufacturing, electronic products are trending towards miniaturization and high integration, leading to the emergence of stacked semiconductor structure packaging technology. Stacked semiconductor structure packaging technology, also known as three-dimensional packaging technology, refers to the vertical stacking of two or more semiconductor structures within the same package.

[0003] In three-dimensional packaging technology, through silicon via (TSV) technology is used to make corresponding through holes on each semiconductor structure. The through holes are filled with conductive material to form a TSV structure, which is used to achieve vertical conduction between stacked semiconductor structures.

[0004] However, in the process of forming a through-silicon via structure, the through-holes formed in the substrate are filled with conductive materials, such as copper, tungsten, and aluminum. Due to the large difference in thermal expansion coefficient between the conductive material and the substrate, severe stress effects may occur, resulting in cracks between the through-silicon via structure and the surrounding semiconductor structure, greatly reducing the performance of the semiconductor structure. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0006] The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure.

[0007] In a first aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, the method comprising:

[0008] Providing a substrate having a first surface and a second surface opposite to each other;

[0009] forming a first dielectric layer on the first surface;

[0010] forming a plurality of capacitor structures in the first dielectric member, wherein the plurality of capacitor structures enclose an exclusion zone;

[0011] A through silicon via (TSV) structure is formed on the second surface. Along a first direction, one end of the TSV structure passes through the substrate and the exclusion area and is electrically connected to the plurality of capacitor structures.

[0012] According to some embodiments of the present disclosure, before forming the first dielectric layer on the first surface, the method further includes:

[0013] Capacitor contact pads are formed on the first surface.

[0014] According to some embodiments of the present disclosure, forming a plurality of capacitor structures in the first dielectric layer includes:

[0015] forming a capacitor region in the first dielectric layer;

[0016] forming a capacitor hole in the capacitor region, wherein the capacitor hole exposes the capacitor contact pad;

[0017] The capacitor structure is formed in the capacitor hole.

[0018] According to some embodiments of the present disclosure, forming the capacitor structure in the capacitor hole includes:

[0019] forming a lower electrode in the capacitor hole;

[0020] Self-aligned etching is performed to remove the first dielectric layer forming the capacitor hole, exposing the lower electrode;

[0021] forming a high-K dielectric layer on the lower electrode and wrapping the lower electrode;

[0022] An upper electrode covering the high-K dielectric layer is formed on the capacitor contact pad.

[0023] According to some embodiments of the present disclosure, forming an upper electrode covering the high-K dielectric layer on the capacitor contact pad includes:

[0024] forming an interlayer dielectric layer on the capacitor contact pad, wherein the interlayer dielectric layer partially wraps the high-K dielectric layer, and a top surface of the interlayer dielectric layer is lower than a top surface of the lower electrode;

[0025] A conductive layer is formed on the interlayer dielectric layer, wherein a top surface of the conductive layer is higher than a top surface of the high-K dielectric layer, wherein the interlayer dielectric layer and the conductive layer form the upper electrode.

[0026] According to some embodiments of the present disclosure, the method for manufacturing the semiconductor structure further includes:

[0027] forming a second dielectric layer on the surface of the upper electrode, wherein the second dielectric layer is flush with the first dielectric layer;

[0028] forming a through hole in the second dielectric layer, wherein the bottom of the through hole exposes the upper electrode;

[0029] A conductive contact pad is formed in the through hole, and the conductive contact pad is connected to the upper electrode.

[0030] According to some embodiments of the present disclosure, forming a through silicon via structure on the second surface includes:

[0031] forming a first through hole on the second surface, wherein a projection area of ​​the first through hole on the substrate is located within a projection area of ​​the exclusion zone on the substrate;

[0032] A through silicon via structure is formed in the first through hole.

[0033] According to some embodiments of the present disclosure, forming a through silicon via structure in the first through hole includes:

[0034] A first barrier layer is formed on the sidewall of the first through hole, wherein the inner wall of the first barrier layer forms a second through hole.

[0035] forming a conductive plug in the second through hole;

[0036] The conductive plug and the first barrier layer form the through silicon via structure.

[0037] According to some embodiments of the present disclosure, forming a through silicon via structure in the first through hole includes:

[0038] forming a second barrier layer, a first conductive layer, and a third barrier layer stacked in sequence on the sidewalls of the first through hole, wherein the inner wall of the third barrier layer encloses a third through hole;

[0039] forming a conductive plug in the third through hole;

[0040] The conductive plug and the second barrier layer, the first conductive layer and the third barrier layer form the through silicon via structure.

[0041] According to some embodiments of the present disclosure, the method for manufacturing the semiconductor structure further includes:

[0042] Conductive connection lines are formed on the first dielectric layer and the second dielectric layer, and the conductive connection lines electrically connect the plurality of capacitor structures and the through silicon via structures.

[0043] According to some embodiments of the present disclosure, forming conductive connecting lines on the first dielectric layer and the second dielectric layer includes:

[0044] forming a first trench on the first dielectric layer and the second dielectric layer, wherein a bottom surface of the first trench exposes a top surface of the conductive contact pad and a top surface of the through silicon via structure;

[0045] A conductive connection line is formed in the first trench, and a top surface of the conductive connection line is flush with a top surface of the first dielectric layer.

[0046] According to some embodiments of the present disclosure, forming a first trench on the first dielectric layer and the second dielectric layer, wherein the bottom surface of the first trench exposes the top surface of the conductive contact pad, includes:

[0047] forming an annular groove on the first dielectric layer and the second dielectric layer, wherein the bottom of the annular groove exposes the top surface of the conductive contact pad;

[0048] A linear groove is formed on the first dielectric layer and the second dielectric layer, wherein both ends of the linear groove are connected to the annular groove, and the linear groove exposes the top surface of the through silicon via structure, wherein the annular groove and the linear groove form the first groove.

[0049] A second aspect of the embodiments of the present disclosure provides a semiconductor structure, including:

[0050] A substrate having a first surface and a second surface opposite to each other, wherein a first dielectric layer is provided on the first surface;

[0051] a plurality of capacitor structures, wherein the capacitor structures are arranged in the first dielectric layer, and the plurality of capacitor structures enclose an exclusion zone;

[0052] A through silicon via structure is provided on the second surface, and one end of the through silicon via structure passes through the substrate and the exclusion area and is electrically connected to the plurality of capacitor structures.

[0053] According to some embodiments of the present disclosure, the number of the capacitor structures is at least four, and the at least four capacitor structures are evenly distributed around the through silicon via structure.

[0054] According to some embodiments of the present disclosure, the through silicon via structure includes a conductive plug and a first barrier layer, wherein the lower section of the first barrier layer is located between the conductive plug and the substrate, and the upper section of the first barrier layer is located between the conductive plug and the first dielectric layer.

[0055] According to some embodiments of the present disclosure, the through silicon via structure includes a conductive plug and a third barrier layer, a first conductive layer, and a second barrier layer sequentially wrapped around the conductive plug, and the outer wall of the second barrier layer is connected to the first dielectric layer and the substrate.

[0056] According to some embodiments of the present disclosure, the conductive plug is made of copper or tungsten.

[0057] According to some embodiments of the present disclosure, the capacitor structure includes a lower electrode, a high-K dielectric layer and an upper electrode, multiple lower electrodes are arranged at intervals, and one end of the lower electrode is connected to the substrate through a capacitor contact pad, and the high-K dielectric layer is wrapped around the lower electrode; the upper electrode includes a conductive layer and an interlayer dielectric layer, the interlayer dielectric layer is arranged on the capacitor contact pad and wraps part of the high-K dielectric layer, the conductive layer is arranged on the interlayer dielectric layer, and the conductive layer is electrically connected to the silicon through-hole structure through multiple conductive contact pads.

[0058] According to some embodiments of the present disclosure, a conductive connecting line is further included, which includes a straight line segment and a ring segment, and both ends of the straight line segment are connected to the ring segment, wherein the ring segment is connected to the conductive contact pads in the plurality of capacitor structures, and some of the straight line segments are connected to the silicon through-hole structure.

[0059] According to some embodiments of the present disclosure, a conductive connecting line is further included, which includes a straight line segment and a ring segment, and both ends of the straight line segment are connected to the ring segment, wherein the ring segment is connected to the conductive contact pads in the plurality of capacitor structures, and some of the straight line segments are connected to the silicon through-hole structure.

[0060] In the manufacturing method and semiconductor structure of the semiconductor structure disclosed herein, before forming a through-silicon via structure, a plurality of capacitor structures are first formed on the first surface of the substrate, and the plurality of capacitor structures enclose an exclusion region. Then, a through-silicon via structure is formed on the second surface of the substrate, wherein one end of the through-silicon via structure passes through the substrate and the exclusion region and is electrically connected to the plurality of capacitor structures. The diffusion stress generated during the formation of the through-silicon via structure is effectively absorbed by the plurality of capacitor structures, thereby protecting the through-silicon via structure and improving the performance of the semiconductor structure.

[0061] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The accompanying drawings, which are incorporated into and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, not all embodiments. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0063] Figure 1 The figure is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0064] Figure 2is a schematic diagram showing a semiconductor structure according to an exemplary embodiment.

[0065] Figure 3 is a schematic diagram showing a semiconductor structure according to an exemplary embodiment.

[0066] Figure 4 FIG. 1 is a schematic diagram showing a conductive connection line in a semiconductor structure according to an exemplary embodiment.

[0067] Figure 5 is a schematic diagram of forming a capacitor contact pad in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0068] Figure 6 The figure is a schematic diagram of forming a lower electrode and a high-K dielectric layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0069] Figure 7 is a schematic diagram of forming an upper electrode in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0070] Figure 8 FIG. 1 is a schematic diagram of forming a second dielectric layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0071] Figure 9 is a schematic diagram illustrating forming a through hole in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0072] Figure 10 FIG. 1 is a schematic diagram showing forming a conductive contact pad in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0073] Figure 11 FIG. 4 is a schematic diagram of forming a first barrier layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0074] Figure 12 The figure is a schematic diagram of forming a through silicon via structure and a conductive connection line in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0075] Figure 13 The figure is a schematic diagram of forming a second barrier layer, a first conductive layer, and a third barrier layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0076] Figure 14 The figure is a schematic diagram of forming a through silicon via structure and a conductive connection line in a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0077] Reference numerals:

[0078] 10. substrate; 20. first dielectric layer;

[0079] 30. Capacitor structure; 40. Exclusion zone;

[0080] 50. Capacitor hole; 60. Capacitor contact pad;

[0081] 70. lower electrode; 80. high-K dielectric layer;

[0082] 90. upper electrode; 100. conductive contact pad;

[0083] 110, second dielectric layer; 120, conductive connecting line;

[0084] 130, first groove; 140, first through hole;

[0085] 150. Through silicon via structure; 160. First barrier layer;

[0086] 170, second through hole; 180, conductive plug;

[0087] 190, second barrier layer; 200, first conductive layer;

[0088] 210, third barrier layer; 220, third through hole;

[0089] 230: through hole; 910, interlayer dielectric layer;

[0090] 920, conductive layer; 1210, straight line segment;

[0091] 1220. Ring segment. DETAILED DESCRIPTION

[0092] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that, in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0093] In three-dimensional packaging technology, through silicon via (TSV) technology is used to make corresponding through holes on each semiconductor structure. The through holes are filled with conductive material to form a TSV structure, which is used to achieve vertical conduction between stacked semiconductor structures.

[0094] However, in the process of forming a through-silicon via structure, the through-holes formed in the substrate are filled with conductive materials, such as copper, tungsten, and aluminum. Due to the large difference in thermal expansion coefficient between the conductive material and the substrate, severe stress effects may occur, resulting in cracks between the through-silicon via structure and the surrounding semiconductor structure, greatly reducing the performance of the semiconductor structure.

[0095] The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure. In the method for manufacturing the semiconductor structure, before forming a through-silicon via (TSV) structure, a plurality of capacitor structures are first formed on a first surface of a substrate, and the plurality of capacitor structures enclose an exclusion region. Then, a TSV structure is formed on a second surface of the substrate, wherein one end of the TSV structure passes through the substrate and the exclusion region and is electrically connected to the plurality of capacitor structures. The plurality of capacitor structures effectively absorbs the diffusion stress generated during the formation of the TSV structure, thereby protecting the TSV structure and improving the performance of the semiconductor structure.

[0096] In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. Figure 1 As shown, Figure 1 A flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 1 to 14 The fabrication method of semiconductor structures is introduced.

[0097] This embodiment does not limit the semiconductor structure. The semiconductor structure will be described below using a dynamic random access memory (DRAM) as an example, but this embodiment is not limited thereto. The semiconductor structure in this embodiment may also be other structures.

[0098] like Figure 1 As shown, an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0099] Step S100: providing a substrate having a first surface and a second surface opposite to each other.

[0100] Step S200: forming a first dielectric layer on the first surface.

[0101] Step S300: forming a plurality of capacitor structures in a first dielectric layer, wherein the plurality of capacitor structures enclose an exclusion zone.

[0102] Step S400: forming a through silicon via structure on the second surface, wherein one end of the through silicon via structure passes through the substrate and the exclusion area along a first direction and is electrically connected to the plurality of capacitor structures.

[0103] For example, Figure 5As shown, in step S100, the substrate 10 serves as a supporting component of the dynamic random access memory, for supporting other components provided thereon. The substrate 10 can be made of a semiconductor material, and the semiconductor material can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.

[0104] In the direction perpendicular to the substrate 10, that is Figure 12 In the Y direction shown in FIG, which is the first direction in this embodiment, the substrate 10 has a first surface and a second surface that are oppositely arranged. The first surface can be understood as the upper surface of the substrate 10, and the second surface can be understood as the lower surface of the substrate 10.

[0105] In some embodiments, before forming the first dielectric layer 20 on the first surface, a capacitor contact pad 60 may be formed at the bottom of the capacitor hole 50 by an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process, wherein the top surface of the capacitor contact pad 60 is lower than the top surface of the capacitor hole 50. Figure 12 In the X direction shown in FIG, the width of the capacitor contact pad 60 may be the same as or different from the width of the capacitor hole 50. In one embodiment, the width of the capacitor contact pad 60 is smaller than the width of the capacitor hole 50.

[0106] In step S200, refer to Figure 5 and Figure 6 A first dielectric layer 20 can be formed on the first surface by atomic deposition, chemical vapor deposition, and physical vapor deposition processes. The first dielectric layer 20 covers the capacitor contact pad 60. The first dielectric layer 20 can prevent the substrate 10 from being electrically connected to other components formed in the first dielectric layer 20. The first dielectric layer 20 may include a silicon oxide layer.

[0107] In step S300, Figure 6 and Figure 7 As shown, a plurality of capacitor structures 30 are formed in the first dielectric layer 20, wherein the plurality of capacitor structures 30 enclose an exclusion area 40 (refer to Figure 2 and Figure 3 The area shown by the dotted box in FIG. 1 ). The projected shape of the capacitor structure 30 on the substrate 10 includes a square, a rectangle, a circle, a ring, etc. In some embodiments, the number of capacitor structures 30 is at least four, and the capacitor structure 30 includes but is not limited to a decoupling capacitor. At least four capacitor structures 30 can be arranged at the edge of the exclusion area 40 along a circular interval, or can be arranged at the edge of the exclusion area 40 along a square interval. By arranging multiple capacitor structures 30 in a ring structure, the diffusion stress generated when the through silicon via structure is formed in the subsequent through silicon via process can be effectively absorbed, cracks can be prevented between the through silicon via structure and the semiconductor structure around it, the through silicon via structure is protected, and the performance of the semiconductor structure is thereby improved.

[0108] The following method may be used to form the plurality of capacitor structures 30:

[0109] First, a capacitor region is formed in the first dielectric layer 20, and capacitor holes 50 are formed in the capacitor region. There are multiple capacitor holes 50, and the bottoms of the capacitor holes 50 expose capacitor contact pads 60. In some embodiments, at least four capacitor holes 50 can be formed in the capacitor region of the first dielectric layer 20, and the at least four capacitor holes 50 are evenly distributed in a ring array. A photoresist layer can be formed on the first dielectric layer 20, and a mask pattern can be formed on the photoresist layer by exposure or development etching. The photoresist layer with the mask pattern is used as a mask to remove the first dielectric layer 20 not blocked by the mask pattern, thereby forming a plurality of capacitor holes 50 evenly distributed in a ring array.

[0110] Next, multiple lower electrodes 70 are formed within the capacitor hole 50. The lower electrodes 70 extend along the depth direction of the capacitor hole 50, i.e., along the Y direction. The bottom ends of the lower electrodes 70 are connected to the capacitor contact pad 60, and the top ends of the lower electrodes 70 are disposed toward the open end of the capacitor hole 50. The multiple lower electrodes 70 are arranged in an array at intervals. The material of the lower electrodes 70 includes, but is not limited to, titanium nitride (TiN).

[0111] Then, the first dielectric layer 20 forming the capacitor hole 50 is removed by self-aligned etching to expose the lower electrode 70. The self-aligned etching can be performed by a wet etching process or a dry etching process.

[0112] After forming multiple lower electrodes 70, a high-K dielectric layer 80 is formed on the lower electrodes 70. The high-K dielectric layer 80 wraps around the outer periphery of the lower electrodes 70, and the bottom of the high-K dielectric layer 80 contacts the capacitor contact pad 60. The high-K dielectric layer 80 can increase the capacitance value of the capacitor per unit area, which is beneficial for improving carrier mobility and device performance. The material of the high-K dielectric layer 80 can be, for example, a stack formed by at least one of the group consisting of zirconium oxide (ZrOx), hafnium oxide (HfOx), titanium zirconium oxide (ZrTiOx), ruthenium oxide (RuOx), antimony oxide (SbOx), and aluminum oxide (AlOx). The high-K dielectric layer 80 can be prepared using an atomic layer deposition process to ensure the film quality and thickness uniformity of the high-K dielectric layer 80.

[0113] Then, an upper electrode 90 covering the high-K dielectric layer 80 is formed on the capacitor contact pad 60, and the top surface of the upper electrode 90 is lower than the top surface of the capacitor hole 50. In some embodiments, an interlayer dielectric layer 910 can be first deposited on the capacitor contact pad 60 by an atomic layer deposition process, a chemical vapor deposition process, and a physical vapor deposition process. The interlayer dielectric layer 910 wraps a portion of the high-K dielectric layer 80, and at the same time, the top surface of the interlayer dielectric layer 910 is lower than the top surface of the lower electrode 70. Then, a conductive layer 920 is deposited on the interlayer dielectric layer 910 by an atomic layer deposition process, a chemical vapor deposition process, and a physical vapor deposition process. The top surface of the conductive layer 920 is higher than the top surface of the high-K dielectric layer 80, but the top surface of the conductive layer 920 is lower than the top surface of the capacitor hole 50. Among them, the interlayer dielectric layer 910 and the conductive layer 920 form the upper electrode 90. It should be noted that the material of the interlayer dielectric layer 910 includes oxide or nitride, and the material of the conductive layer 920 includes titanium nitride or silicon germanium.

[0114] like Figure 9 As shown, after the upper electrode 90 is formed, a second dielectric layer 110 is formed on the surface of the upper electrode 90. The second dielectric layer 110 is flush with the first dielectric layer 20. Figure 9 A second dielectric layer 110 can be formed on the upper electrode 90 by atomic layer deposition, chemical vapor deposition, and physical vapor deposition. The material of the second dielectric layer 110 can be the same as or different from the material of the first dielectric layer 20. In some embodiments, the material of the second dielectric layer 110 is the same as that of the first dielectric layer 20, such as silicon oxide.

[0115] Then, a through hole 230 is formed in the second dielectric layer 110, and the bottom of the through hole 230 exposes the upper electrode 90. A photoresist layer can be formed on the second dielectric layer 110, and a mask pattern is formed on the photoresist layer by exposure or development etching. The photoresist layer with the mask pattern is used as a mask to remove the second dielectric layer 110 not blocked by the mask pattern, thereby forming the through hole 230, effectively improving the formation accuracy of the through hole 230.

[0116] like Figure 8As shown, in step S300, a conductive contact pad 100 is also formed in the through hole 230. It should be noted that a plurality of conductive contact pads 100 are formed in each through hole 230 to increase the conductivity between the subsequently formed conductive connection line 120 and the upper electrode 90. The conductive contact pad 100 can be formed on the upper electrode 90 by an atomic layer deposition process, a chemical vapor deposition process, and a physical vapor deposition process. The top surface of the conductive contact pad 100 is lower than the top surface of the capacitor hole 50. In some embodiments, the material of the conductive contact pad 100 can be the same as the material of the conductive layer 920. For example, the material of the conductive contact pad 100 can be titanium nitride or silicon germanium.

[0117] like Figure 10 As shown, in step S400, a photoresist layer can be formed on the second surface, and a mask pattern can be formed on the photoresist layer by exposure or development etching. The photoresist layer with the mask pattern is used as a mask to remove the substrate 10 that is not blocked by the mask pattern to form a first through hole 140. The projection area of ​​the first through hole 140 on the substrate 10 is located within the projection area of ​​the exclusion area 40 on the substrate 10. In one embodiment, the projection area of ​​the first through hole 140 on the substrate 10 is located in the central position area of ​​the projection area of ​​the exclusion area 40 on the substrate 10. At the same time, referring to Figure 12 In the Y-direction of the extension direction, the bottom end of the first through hole 140 extends toward the second surface until the bottom of the subsequently formed conductive connection line 120 is exposed.

[0118] Then, a through silicon via structure 150 is formed in the first through hole 140. In some embodiments, the through silicon via structure 150 may be formed by the following method:

[0119] First, refer to Figure 11 and Figure 12 As shown, a first barrier layer 160 is deposited on the inner wall of the first through hole 140 , and the inner wall of the first barrier layer 160 forms a second through hole 170 .

[0120] Then, a conductive plug 180 is formed in the second through-hole 170. The conductive plug 180 can be a copper pillar formed in the second through-hole 170 by electroplating, or a pair of tungsten pillars formed in the second through-hole 170 by atomic layer deposition, chemical vapor deposition, and physical vapor deposition. The first barrier layer 160 and the conductive plug 180 form the through-silicon via structure 150.

[0121] The conductive plug 180 is usually made of metal such as copper. Copper has a large thermal expansion coefficient. During the use of the semiconductor structure, the through-silicon via structure or other functional devices will generate a large amount of heat, causing the through-silicon via structure to expand due to the heat, resulting in stress deformation in the contact area between the substrate and the through-silicon via structure, affecting the performance of the semiconductor structure. Therefore, in this embodiment, a first barrier layer is formed on the second through hole, and multiple capacitor structures are formed on the periphery of the first barrier layer. The first barrier layer and the multiple capacitor structures are used to buffer the stress of the through-silicon via structure on the surrounding dielectric layer, thereby improving the performance of the semiconductor structure.

[0122] In other embodiments, reference Figure 13 and Figure 14 As shown, the through silicon via structure 150 may also be formed by the following method:

[0123] First, a second barrier layer 190, a first conductive layer 200, and a third barrier layer 210 are sequentially stacked on the inner wall of the first through hole 140. The second barrier layer 190 is connected to the inner wall of the first through hole 140, and the first conductive layer 200 is located between the second barrier layer 190 and the third barrier layer 210. At this time, the inner wall of the third barrier layer 210 encloses the third through hole 220.

[0124] Then, a conductive plug 180 is formed in the third through-hole 220. The conductive plug 180 can be a copper pillar formed in the third through-hole 220 by electroplating, or a tungsten pillar formed in the third through-hole 220 by atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The second barrier layer 190, the first conductive layer 200, the third barrier layer 210, and the conductive plug 180 form the through-silicon via structure 150.

[0125] The conductive plug 180 is usually made of metal such as copper. Copper has a large thermal expansion coefficient. During the use of the semiconductor structure, the through-silicon via structure or other functional devices will generate a large amount of heat, causing the through-silicon via structure to expand due to the heat, resulting in stress deformation in the contact area between the substrate and the through-silicon via structure, affecting the performance of the semiconductor structure. Therefore, in this embodiment, a second barrier layer, a first conductive layer, and a third barrier layer are formed on the first through-hole in a stacked manner, and multiple capacitor structures are formed on the periphery of the second barrier layer to buffer the stress of the through-silicon via structure on the surrounding dielectric layer, thereby improving the performance of the semiconductor structure.

[0126] Reference Figure 10 As shown, in some embodiments, the plurality of capacitor structures 30 and the through silicon via structure 150 are electrically connected via a conductive connection line 120 , wherein the top surface of the conductive connection line 120 is flush with the top surface of the first dielectric layer 20 .

[0127] It should be noted that the conductive connection line 120 is formed in the first dielectric layer 20 and the second dielectric layer 110 .

[0128] The conductive connection line 120 may be formed by the following method:

[0129] Reference Figure 2 and Figure 3 As shown, a first trench 130 is formed on the first dielectric layer 20 and the second dielectric layer 110, wherein the bottom surface of the first trench 130 exposes the top surface of the conductive capacitor contact pad 100. A photoresist layer can be formed on the first dielectric layer 20 and the second dielectric layer 110, and a mask pattern is formed on the photoresist layer by exposure or development etching. The photoresist layer with the mask pattern is used as a mask to remove the first dielectric layer 20 and the second dielectric layer 110 not blocked by the mask pattern, thereby forming the first trench 130, effectively improving the formation accuracy of the first trench 50.

[0130] In some embodiments, an annular trench can be first formed in the first dielectric layer 20 and the second dielectric layer 110. The bottom of the annular trench exposes the top surface of the conductive contact pad 100. It should be noted that the annular trench is used to form a conductive connection line 120 in an annular structure. The conductive connection line 120 in the annular structure is used to connect all the conductive contact pads 100 on the at least four capacitor structures 30 outside the exclusion zone 40. Then, a linear trench is formed in the first dielectric layer 20 and the second dielectric layer 110. The ends of the linear trench are connected to the annular trench. The linear conductive connection line 120 is formed in the linear trench. The linear conductive connection line 120 facilitates subsequent electrical connection to devices in other functional areas of the semiconductor structure. The annular trench and the linear trench form the second trench 130.

[0131] Finally, conductive connection lines 120 are formed in the annular trench and the linear trench. The conductive connection lines 120 electrically connect the through silicon via structure and the at least four capacitor structures 30 .

[0132] In the method for manufacturing a semiconductor structure of this embodiment, before forming a through-silicon via structure, multiple capacitor structures are first formed on the periphery of the exclusion area. The capacitor structures are used to effectively absorb the diffusion stress generated when forming the conductive plug in the through-silicon via structure, prevent cracks from forming between the through-silicon via structure and the surrounding semiconductor structure, protect the through-silicon via structure, and thereby improve the performance of the semiconductor structure.

[0133] like Figure 2 and Figure 3 As shown, an exemplary embodiment of the present disclosure provides a semiconductor structure, which includes a substrate 10 , a plurality of capacitor structures 30 , and a through-silicon via (TSV) structure 150 .

[0134] The substrate 10 has a first surface and a second surface opposite to each other, and a first dielectric layer 20 is provided on the first surface.

[0135] The capacitor structure 30 is arranged in the first dielectric layer 20, and multiple capacitor structures form an exclusion area 40. It should be noted that the projected shape of the capacitor structure 30 on the substrate 10 includes square, rectangular, circular and ring shapes. In some embodiments, the number of capacitor structures 30 is at least four, and the capacitor structure 30 includes but is not limited to decoupling capacitors. At least four capacitor structures 30 can be arranged at the edge of the exclusion area 40 along a circular interval, or can be arranged at the edge of the exclusion area 40 along a square interval. By arranging multiple capacitor structures 30 in a ring structure, the diffusion stress generated when the silicon via structure is formed in the subsequent silicon via process can be effectively absorbed, cracks can be prevented from occurring between the silicon via structure and the semiconductor structure around it, the silicon via structure can be protected, and the performance of the semiconductor structure can be improved.

[0136] The TSV structure 150 is disposed on the second surface, wherein a top end of the TSV structure 150 passes through the substrate 10 and the exclusion area 40 and is electrically connected to the plurality of capacitor structures 30 .

[0137] Among them, reference Figure 12 As shown, in some embodiments, the through silicon via structure 150 includes a conductive plug 180 and a first barrier layer 160 , wherein a lower section of the first barrier layer 160 is located between the conductive plug 180 and the substrate 10 , and an upper section of the first barrier layer 160 is located between the conductive plug 180 and the first dielectric layer 20 .

[0138] In other embodiments, referring to Figure 14 As shown, the TSV structure 150 includes a conductive plug 180 and a third barrier layer 210 , a first conductive layer 200 and a second barrier layer 190 sequentially wrapped around the conductive plug 180 . The outer wall of the second barrier layer 190 is connected to the first dielectric layer 20 and the substrate 10 .

[0139] In some embodiments, the conductive plug 180 is made of copper or tungsten and can be a copper pillar formed by electroplating, or a tungsten pillar formed by atomic layer deposition, chemical vapor deposition, or physical vapor deposition.

[0140] like Figure 7As shown, in some embodiments, the capacitor structure 30 includes a lower electrode 70, a high-K dielectric layer 80, and an upper electrode 90. A plurality of lower electrodes 70 are spaced apart, and one end of the lower electrode 70 is connected to the substrate 10 via a capacitor contact pad 60. The high-K dielectric layer 80 wraps around the lower electrode 70. The upper electrode 90 includes a conductive layer 920 and an interlayer dielectric layer 910. The interlayer dielectric layer 910 is disposed on the capacitor contact pad 60 and wraps around a portion of the high-K dielectric layer 80. The conductive layer 920 is disposed on the interlayer dielectric layer 910. The conductive layer 920 is electrically connected to the through-silicon via structure 150 via a plurality of conductive contact pads 100.

[0141] In some embodiments, the semiconductor structure further includes a conductive connection line 120. The conductive connection line 120 includes a straight segment 1210 and a ring segment 1220. The ends of the straight segment 1210 are connected to the ring segment 1220. The ring segment 1220 is connected to the conductive contact pads 100 in multiple capacitor structures 30, and is used to connect all the conductive contact pads 100 on at least four capacitor structures 30 outside the exclusion zone 40. A portion of the straight segment 1210 is connected to the through-silicon via structure 150, and the straight segment 1210 facilitates subsequent electrical connection to devices in other functional areas of the semiconductor structure. It should be noted that the projected shape of the ring segment 1220 on the substrate 10 includes, but is not limited to, a regular polygon and a circular ring.

[0142] In the semiconductor structure of this embodiment, multiple capacitor structures are formed on the periphery of the through-silicon via structure. The capacitor structures are used to effectively absorb the diffusion stress generated when the conductive plug is formed in the through-silicon via structure, thereby preventing cracks from forming between the through-silicon via structure and the semiconductor structure surrounding it, protecting the through-silicon via structure, and thereby improving the performance of the semiconductor structure.

[0143] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0144] In the description of this specification, reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0145] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.

[0146] In the description of the present disclosure, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present disclosure.

[0147] It is to be understood that the terms "first", "second", etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

[0148] In one or more of the accompanying drawings, identical elements are represented by similar reference numerals. For clarity, many parts in the accompanying drawings are not drawn to scale. In addition, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be described in a single figure. Many specific details of the present disclosure, such as device structure, materials, dimensions, processing techniques, and technologies, are described below to facilitate a clearer understanding of the present disclosure. However, as will be appreciated by those skilled in the art, the present disclosure may be practiced without following these specific details.

[0149] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The method for manufacturing the semiconductor structure comprises: Providing a substrate having a first surface and a second surface opposite to each other; forming a first dielectric layer on the first surface; forming a plurality of capacitor structures in the first dielectric member, wherein the plurality of capacitor structures enclose an exclusion zone; forming a through silicon via structure on the second surface, wherein one end of the through silicon via structure penetrates the substrate and the exclusion zone along the first direction and is electrically connected to the plurality of capacitor structures, wherein the capacitor structure includes a lower electrode, a high-K dielectric layer, and an upper electrode formed in sequence; Also includes: forming a second dielectric layer on the surface of the upper electrode, wherein the second dielectric layer is flush with the first dielectric layer; forming a through hole in the second dielectric layer, wherein the bottom of the through hole exposes the upper electrode; forming a conductive contact pad in the through hole, wherein the conductive contact pad is connected to the upper electrode; forming conductive connecting lines on the first dielectric layer and the second dielectric layer, wherein the conductive connecting lines electrically connect the plurality of capacitor structures and the through silicon via structures; The step of forming conductive connecting lines on the first dielectric layer and the second dielectric layer includes: forming a first trench on the first dielectric layer and the second dielectric layer, wherein a bottom surface of the first trench exposes a top surface of the conductive contact pad and a top surface of the through silicon via structure; forming a conductive connecting line in the first trench, wherein a top surface of the conductive connecting line is flush with a top surface of the first dielectric layer; Wherein, a first trench is formed on the first dielectric layer and the second dielectric layer, wherein the bottom surface of the first trench exposes the top surface of the conductive contact pad, comprising: forming an annular groove on the first dielectric layer and the second dielectric layer, wherein the bottom of the annular groove exposes the top surface of the conductive contact pad; A linear groove is formed on the first dielectric layer and the second dielectric layer, wherein both ends of the linear groove are connected to the annular groove, and the linear groove exposes the top surface of the through silicon via structure, wherein the annular groove and the linear groove form the first groove.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: Before forming the first dielectric layer on the first surface, the method further includes: Capacitor contact pads are formed on the first surface.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: Forming a plurality of capacitor structures in the first dielectric layer includes: forming a capacitor region in the first dielectric layer; forming a capacitor hole in the capacitor region, wherein the capacitor hole exposes the capacitor contact pad; The capacitor structure is formed in the capacitor hole.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein: The forming of the capacitor structure in the capacitor hole includes: forming a lower electrode in the capacitor hole; Self-aligned etching is performed to remove the first dielectric layer forming the capacitor hole, exposing the lower electrode; forming a high-K dielectric layer on the lower electrode and wrapping the lower electrode; An upper electrode covering the high-K dielectric layer is formed on the capacitor contact pad.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein: The step of forming an upper electrode covering the high-K dielectric layer on the capacitor contact pad includes: forming an interlayer dielectric layer on the capacitor contact pad, wherein the interlayer dielectric layer partially wraps the high-K dielectric layer, and a top surface of the interlayer dielectric layer is lower than a top surface of the lower electrode; A conductive layer is formed on the interlayer dielectric layer, wherein a top surface of the conductive layer is higher than a top surface of the high-K dielectric layer, wherein the interlayer dielectric layer and the conductive layer form the upper electrode.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein: The step of forming a through silicon via structure on the second surface comprises: forming a first through hole on the second surface, wherein a projection area of ​​the first through hole on the substrate is located within a projection area of ​​the exclusion zone on the substrate; A through silicon via structure is formed in the first through hole.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: The step of forming a through silicon via structure in the first through hole includes: A first barrier layer is formed on the sidewall of the first through hole, wherein the inner wall of the first barrier layer forms a second through hole. forming a conductive plug in the second through hole; The conductive plug and the first barrier layer form the through silicon via structure.

8. The method for manufacturing a semiconductor structure according to claim 6, wherein: The step of forming a through silicon via structure in the first through hole includes: forming a second barrier layer, a first conductive layer, and a third barrier layer stacked in sequence on the sidewalls of the first through hole, wherein the inner wall of the third barrier layer encloses a third through hole; forming a conductive plug in the third through hole; The conductive plug and the second barrier layer, the first conductive layer and the third barrier layer form the through silicon via structure.

9. A semiconductor structure, characterized in that The semiconductor structure comprises: A substrate having a first surface and a second surface opposite to each other, wherein a first dielectric layer is provided on the first surface; a plurality of capacitor structures, wherein the capacitor structures are arranged in the first dielectric layer, and the plurality of capacitor structures enclose an exclusion zone; a through silicon via structure, wherein the through silicon via structure is disposed on the second surface, and one end of the through silicon via structure passes through the substrate and the exclusion area and is electrically connected to the plurality of capacitor structures; The capacitor structure includes a lower electrode, a high-K dielectric layer, and an upper electrode. The multiple lower electrodes are arranged at intervals, and one end of the lower electrode is connected to the substrate through a capacitor contact pad. The high-K dielectric layer is wrapped around the lower electrode. The upper electrode includes a conductive layer and an interlayer dielectric layer. The interlayer dielectric layer is arranged on the capacitor contact pad and wraps a portion of the high-K dielectric layer. The conductive layer is arranged on the interlayer dielectric layer. The conductive layer is electrically connected to the through-silicon via structure through multiple conductive contact pads. The semiconductor structure also includes a conductive connecting line, which includes a straight line segment and a ring segment, and both ends of the straight line segment are connected to the ring segment, wherein the ring segment is connected to the conductive contact pads in the plurality of capacitor structures, and some of the straight line segments are connected to the through-silicon via structure.

10. The semiconductor structure according to claim 9, wherein: The number of the capacitor structures is at least four, and the at least four capacitor structures are evenly distributed around the through silicon via structure.

11. The semiconductor structure according to claim 9, wherein: The through silicon via structure includes a conductive plug and a first barrier layer, wherein a lower section of the first barrier layer is located between the conductive plug and the substrate, and an upper section of the first barrier layer is located between the conductive plug and the first dielectric layer.

12. The semiconductor structure according to claim 9, wherein: The through silicon via structure includes a conductive plug and a third barrier layer, a first conductive layer, and a second barrier layer sequentially wrapped around the conductive plug. The outer wall of the second barrier layer is connected to the first dielectric layer and the substrate.

13. The semiconductor structure according to any one of claims 11 or 12, characterized in that: The conductive plug is made of copper or tungsten.

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