Semiconductor structure, method for manufacturing semiconductor structure, and memory

Abstract

The present application provides a method for manufacturing a semiconductor structure, a semiconductor structure and a memory, wherein the semiconductor structure comprises: a substrate, a conductive contact hole formed on the substrate, a metal sulfide layer formed in the conductive contact hole and covering the bottom wall of the conductive contact hole; a semi-metal layer formed on the surface of the metal sulfide layer; a barrier layer covering the surface of the semi-metal layer and the sidewalls of the conductive contact hole; and a conductive contact structure arranged in a receiving hole formed by the barrier layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure, a method for manufacturing a semiconductor structure, and a memory. Background Art

[0002] With the development of the semiconductor industry, due to the continuous reduction of line width, when metal contacts semiconductor, the Schottky barrier and metal-induced gap state cause the contact resistance to be too large, and the current size cannot meet the device working requirements.

[0003] Therefore, how to reduce the contact resistance becomes an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a semiconductor structure, a method for manufacturing a semiconductor structure, and a memory, which can at least solve the above-mentioned problems.

[0005] To solve the above problems, according to a first aspect of an embodiment of the present application, a semiconductor structure is provided, comprising: a substrate, a conductive contact hole being formed on the substrate;

[0006] a metal sulfide layer formed in the conductive contact hole and covering a bottom wall of the conductive contact hole;

[0007] a semi-metal layer formed on the exposed surface of the metal sulfide layer;

[0008] a barrier layer, the barrier layer covering a surface of the semi-metal layer and a sidewall of the conductive contact hole;

[0009] The conductive contact structure is arranged in the accommodating hole formed by the barrier layer.

[0010] In some embodiments, the base includes a substrate and a first dielectric layer formed on the substrate, and the conductive contact hole is formed to penetrate the first dielectric layer and extend into the substrate;

[0011] The conductive contact hole includes a first conductive hole formed in the substrate and a second conductive hole formed in the first dielectric layer, and a radial dimension of the first conductive hole is larger than a radial dimension of the second conductive hole.

[0012] In some embodiments, the material of the metal sulfide layer is molybdenum sulfide or tungsten sulfide, and the material of the semi-metal layer includes a Group VA semi-metal element.

[0013] In some embodiments, the barrier layer covers the surface of the semi-metal layer and the sidewalls of the conductive contact hole, and covers the upper surface of the substrate;

[0014] The conductive contact structure is formed to fill the receiving hole and cover the upper surface of the barrier layer.

[0015] In some embodiments, the present invention further comprises:

[0016] The radial dimension of the metal sulfide layer is larger than the radial dimension of the conductive contact structure; and the upper surface of the metal sulfide layer has a groove-shaped morphology.

[0017] According to a second aspect of an embodiment of the present application, a method for manufacturing a semiconductor structure is provided, comprising:

[0018] providing a substrate, and forming a conductive contact hole on the substrate;

[0019] forming a metal sulfide layer in the conductive contact hole to cover the bottom wall of the conductive contact hole;

[0020] forming a semi-metallic layer covering the exposed surface of the metal sulfide layer;

[0021] forming a barrier layer on the substrate, wherein the barrier layer covers the surface of the semi-metal layer and the sidewalls of the conductive contact hole;

[0022] The receiving hole formed by the barrier layer is filled with conductive material to form a conductive contact structure.

[0023] In some embodiments, forming a conductive contact hole on the substrate includes:

[0024] The substrate is processed by an etching process to form the conductive contact hole on the substrate.

[0025] In some embodiments, the base includes a substrate and a first dielectric layer formed on the substrate, and the conductive contact hole penetrates the first dielectric layer and extends into the substrate to expose the surface of the substrate;

[0026] The conductive contact hole includes a first conductive hole formed in the substrate and a second conductive hole formed in the first dielectric layer, and a radial dimension of the first conductive hole is larger than a radial dimension of the second conductive hole.

[0027] In some embodiments, forming a metal sulfide layer in the conductive contact hole and covering the bottom wall of the conductive contact hole includes:

[0028] forming a metal sulfide layer on the substrate, wherein the metal sulfide layer covers the upper surface of the substrate and the inner wall of the conductive contact hole;

[0029] A removal process is performed to retain the metal sulfide layer covering the surface of the substrate.

[0030] In some embodiments, after forming the metal sulfide layer on the substrate, the method further includes:

[0031] A first sacrificial layer is formed covering the metal sulfide layer.

[0032] In some embodiments, the performing of the removal process to retain the metal sulfide layer covering the surface of the substrate includes:

[0033] The first sacrificial layer and the metal sulfide layer formed on the first dielectric layer are removed to retain the metal sulfide layer formed on the surface of the substrate.

[0034] In some embodiments, removing the first sacrificial layer and the metal sulfide layer formed on the first dielectric layer to retain the metal sulfide layer formed on the surface of the substrate includes:

[0035] forming a patterned first mask layer on a surface of the first sacrificial layer, wherein the first mask layer defines a first etching window;

[0036] Performing back etching according to the first etching window to etch away the metal sulfide layer and the first sacrificial layer in the second conductive hole until they are flush with the upper surface of the substrate;

[0037] The metal sulfide layer, the first sacrificial layer and the first mask layer on the first dielectric layer, and the first sacrificial layer located in the first conductive hole are removed.

[0038] In some embodiments, forming a semi-metal layer covering the exposed surface of the metal sulfide layer comprises:

[0039] forming a semi-metal layer on the substrate, wherein the semi-metal layer covers the upper surface of the substrate, the inner wall of the conductive contact hole and the surface of the metal sulfide layer;

[0040] forming a second sacrificial layer covering the semi-metal layer;

[0041] The second sacrificial layer and the semi-metal layer formed on the first dielectric layer are removed.

[0042] In some embodiments, removing the second sacrificial layer and the semi-metal layer formed on the first dielectric layer includes:

[0043] forming a patterned second mask layer on a surface of the second sacrificial layer, wherein the second mask layer defines a second etching window;

[0044] Performing back etching according to the second etching window to etch away the semi-metal layer and the second sacrificial layer in the second conductive hole until they are flush with the upper surface of the substrate;

[0045] The semi-metal layer, the second sacrificial layer, the second mask layer on the first dielectric layer, and the second sacrificial layer on the semi-metal layer are removed.

[0046] In some embodiments, after removing the first sacrificial layer located in the first conductive hole, the method further includes: removing the metal sulfide layer to form a groove-shaped morphology on the upper surface of the metal sulfide layer.

[0047] According to a third aspect of an embodiment of the present application, a memory is provided, comprising the semiconductor structure described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0049] Figure 1 and Figure 3-12 is a structural diagram of a semiconductor structure according to an exemplary embodiment;

[0050] Figure 2 The flowchart of a method for manufacturing a semiconductor structure is shown according to an exemplary embodiment.

[0051] Reference numerals:

[0052] 10. Base; 11. Substrate; 12. First dielectric layer; 13. Conductive contact hole; 131. First conductive hole; 132. Second conductive hole; 20. Metal sulfide layer; 21. First deposition hole; 30. Semi-metal layer; 31. Second deposition hole; 40. Barrier layer; 41. Accommodation hole; 50. Conductive contact structure; 60. First sacrificial layer; 70. First mask layer; 71. First etching window; 80. Second sacrificial layer; 90. Second mask layer; 91. Second etching window. DETAILED DESCRIPTION

[0053] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0055] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0056] With the development of the semiconductor industry, due to the continuous reduction of line width, when metal contacts semiconductor, the Schottky barrier and metal-induced gap state cause the contact resistance to be too large, and the current size cannot meet the device working requirements.

[0057] Therefore, how to reduce the contact resistance becomes an urgent problem to be solved by those skilled in the art.

[0058] The present application embodiment provides a semiconductor structure, referring to Figure 1 The semiconductor structure includes a substrate 10, a metal sulfide layer 20, a semi-metal layer 30, a barrier layer 40, and a conductive contact structure 50. A conductive contact hole 13 is formed on the substrate 10. The metal sulfide layer 20 is formed in the conductive contact hole 13 and covers the bottom wall of the conductive contact hole 13. The semi-metal layer 30 is formed on the exposed surface of the metal sulfide layer 20. The barrier layer 40 covers the surface of the semi-metal layer 30 and the sidewalls of the conductive contact hole 13. The conductive contact structure 50 is disposed in the receiving hole formed by the barrier layer 40.

[0059] In the embodiment of the present application, the Fermi level of the semi-metal layer 30 is higher than the conduction band minimum of the metal sulfide layer 20. The pz orbital of the semi-metal layer 30 resonates with the pz and dz2 orbitals of the metal sulfide layer 20. The distribution of the inductive electric dipole at the contact interface between the semi-metal layer 30 and the metal sulfide layer 20 falls within the van der Waals gap. The metal-induced interstitial state electrons of the metal sulfide layer 20 are saturated, resulting in saturation of the interstitial states of the metal sulfide layer 20. The contact interface between the semi-metal layer 30 and the metal sulfide layer 20 achieves a zero Schottky barrier, and an ohmic contact is formed between the semi-metal layer 30 and the metal sulfide layer 20. Therefore, the excellent ohmic contact between the semi-metal layer 30 and the metal sulfide layer 20 can reduce the contact resistance of the semiconductor structure and reduce RC delay.

[0060] In some embodiments, the substrate 10 may be etched using an etching process to form a conductive contact hole 13 on the substrate 10 (for details, see Figure 3 In some embodiments, the conductive contact hole 13 may be formed on the substrate 10 by using a dry etching process.

[0061] In some embodiments, the base 10 includes a substrate 11 and a first dielectric layer 12 formed on the substrate 11. The conductive contact hole 13 penetrates the first dielectric layer 12 and extends into the substrate 11. The substrate 11 can be any substrate 11 known in the art as needed, and the structure and material of the substrate 11 can be adaptively adjusted as needed. For example, the material of the substrate 11 can be one or any combination of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, silicon on insulator (SOI), or germanium on insulator (GOI).

[0062] The conductive contact hole 13 includes a first conductive hole 131 formed in the substrate 11 and a second conductive hole 132 formed in the first dielectric layer 12 (see Figure 3 ), the first conductive hole 131 and the second conductive hole 132 are connected, and the radial size of the first conductive hole 131 is larger than the radial size of the second conductive hole 132. Figure 1 The metal sulfide layer 20 is disposed in the first conductive hole 131. The metal sulfide layer 20 is formed to cover the bottom wall and side walls of the first conductive hole 131. The semi-metal layer 30 is disposed on the upper surface of the metal sulfide layer 20. Figure 1 The semi-metal layer 30 is disposed between the metal sulfide layer 20 and the barrier layer 40 , and a portion of the metal sulfide layer 20 is in contact with the lower surface of the first dielectric layer 12 .

[0063] In the embodiment of the present application, the radial dimension of the first conductive via 131 is configured to be larger than the radial dimension of the second conductive via 132 to increase the contact area between the semi-metal layer 30 and the metal sulfide 20, thereby further reducing the contact resistance.

[0064] In some embodiments, the metal sulfide layer 20 is made of molybdenum sulfide or tungsten sulfide, and the semi-metal layer 30 is made of a Group VA semi-metal element, wherein the semi-metal layer 30 is made of Bi, Sb, or As.

[0065] In some embodiments, the metal sulfide layer 20 is made of molybdenum sulfide, and the semi-metal layer 30 is made of bismuth (Bi).

[0066] In the embodiments of the present application, the Fermi level of bismuth is higher than the conduction band minimum of molybdenum disulfide, the pz orbital of bismuth resonates with the pz and dz2 orbitals of molybdenum disulfide, the distribution of the inductive electric dipoles at the contact interface between bismuth and molybdenum disulfide falls into the van der Waals gap, the metal-induced gap state electrons of molybdenum disulfide are saturated, resulting in the saturation of the gap state of molybdenum disulfide, the contact interface between bismuth and molybdenum disulfide achieves zero Schottky barrier, and the contact interface between bismuth and molybdenum disulfide forms an ohmic contact.

[0067] In some embodiments, the material of the barrier layer 40 includes but is not limited to titanium nitride.

[0068] In some embodiments, the material of the conductive contact structure includes but is not limited to tungsten.

[0069] In some embodiments, the barrier layer 40 is formed to cover the surface of the semi-metal layer 30 and the sidewalls of the conductive contact hole 13. Figure 12 In the embodiment, the barrier layer 40 is formed on the inner wall of the second conductive hole 132 and the surface of the semi-metal layer 30 away from the metal sulfide layer 20. Figure 12 The barrier layer 40 is formed to extend from the opening of the conductive contact hole 13 toward the outer edge of the substrate 10 to cover the upper surface of the substrate 10. It is understood that the opening of the conductive contact hole 13 is specifically the opening of the second conductive hole 132 formed at the upper surface of the first dielectric layer 12. The barrier layer 40 is formed at this opening to extend toward the outer edge of the substrate 10 to cover the upper surface of the first dielectric layer 12.

[0070] In some embodiments, the conductive contact structure 50 is formed to fill the accommodating hole 41 (the accommodating hole is specifically Figure 11 ), and is formed to extend from the opening of the accommodating hole 41 toward the outer edge of the substrate 10 to cover the upper surface of the barrier layer 40. It can be understood that the opening of the accommodating hole 41 is located at the upper surface of the first dielectric layer 12, and the conductive contact structure 50 is formed at the opening to extend toward the outer edge of the substrate 10 to cover the upper surface of the barrier layer 40.

[0071] In some embodiments, reference Figure 7 The radial dimension of the metal sulfide layer 20 is larger than the radial dimension of the conductive contact structure. In the embodiment of the present application, the metal sulfide layer 20 can be removed to form a groove-shaped morphology on the upper surface of the metal sulfide layer 20.

[0072] In the embodiment of the present application, the upper surface of the metal sulfide layer 20 is processed into a groove-shaped morphology to increase the contact area between the semi-metal layer 30 and the barrier layer 40 or the conductive contact structure 50, thereby further reducing the contact resistance.

[0073] refer to Figure 1 and Figure 2According to a second aspect of an embodiment of the present application, a method for manufacturing a semiconductor structure is provided, comprising:

[0074] S101, providing a substrate 10, and forming a conductive contact hole 13 on the substrate 10;

[0075] S103, forming a metal sulfide layer 20 in the conductive contact hole 13 to cover the bottom wall of the conductive contact hole 13;

[0076] S105, forming a semi-metal layer 30 covering the exposed surface of the metal sulfide layer 20;

[0077] S107 , forming a barrier layer 40 on the substrate 10 , wherein the barrier layer 40 covers the surface of the semi-metal layer 30 and the sidewalls of the conductive contact hole 13 ;

[0078] S109 , filling the receiving hole formed by the barrier layer 40 with a conductive material to form a conductive contact structure 50 .

[0079] In the embodiment of the present application, the Fermi level of the semi-metal layer 30 is higher than the conduction band minimum of the metal sulfide layer 20. The pz orbital of the semi-metal layer 30 resonates with the pz and dz2 orbitals of the metal sulfide layer 20. The distribution of the inductive electric dipole at the interface between the semi-metal layer 30 and the metal sulfide layer 20 falls within the van der Waals gap. The metal-induced interstitial state electrons of the metal sulfide layer 20 are saturated, resulting in saturation of the interstitial states of the metal sulfide layer 20. The interface between the semi-metal layer 30 and the metal sulfide layer 20 achieves a zero Schottky barrier, and an ohmic contact is formed between the semi-metal layer 30 and the metal sulfide layer 20. Therefore, the good ohmic contact between the semi-metal layer 30 and the metal sulfide layer 20 can reduce the overall resistance of the semiconductor structure.

[0080] In some embodiments, step S101 of forming the conductive contact hole 13 on the substrate 10 includes:

[0081] The substrate 10 is processed by an etching process to form a conductive contact hole 13 on the substrate 10. In some embodiments, the conductive contact hole 13 can be formed on the substrate 10 by a dry etching process. Figure 3 , Figure 3 The conductive contact hole 13 formed on the substrate is schematically shown.

[0082] In some embodiments, the base 10 includes a substrate 11 and a first dielectric layer 12 formed on the substrate 11. The conductive contact hole 13 is formed to penetrate the first dielectric layer 12 and extend into the substrate 11 to expose the surface of the substrate 11. The substrate 11 can be any substrate 11 in the prior art as needed, and the structure and material of the substrate 11 can be adaptively adjusted as needed. For example, the material of the substrate 11 can be one or any combination of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, silicon on insulator (SOI), or germanium on insulator (GOI).

[0083] Among them, continue to refer to Figure 3 The conductive contact hole 13 includes a first conductive hole 131 formed in the substrate 11 and a second conductive hole 132 formed in the first dielectric layer 12. The first conductive hole 131 and the second conductive hole 132 are connected. The radial dimension of the first conductive hole 131 is larger than the radial dimension of the second conductive hole 132. Figure 1 The metal sulfide layer 20 is disposed in the first conductive hole 131. The metal sulfide layer 20 is formed to cover the bottom wall and side walls of the first conductive hole 131. The semi-metal layer 30 is disposed on the upper surface of the metal sulfide layer 20. Figure 1 The semi-metal layer 30 is disposed between the metal sulfide layer 20 and the barrier layer 40 , and the metal sulfide layer 20 is in contact with the lower surface of the first dielectric layer 12 .

[0084] In the embodiment of the present application, the radial dimension of the first conductive via 131 is configured to be larger than the radial dimension of the second conductive via 132 to increase the contact area between the semi-metal layer 30 and the metal sulfide 20, thereby further reducing the contact resistance.

[0085] In some embodiments, step S103 of forming the metal sulfide layer 20 in the conductive contact hole 13 to cover the bottom wall of the conductive contact hole 13 includes:

[0086] S1031, forming a metal sulfide layer 20 on the substrate 10, wherein the metal sulfide layer 20 covers the upper surface of the substrate 10 and the inner wall of the conductive contact hole 13;

[0087] A metal sulfide layer 20 is formed on the substrate 10 by a deposition process. Figure 4 The metal sulfide layer 20 covers the inner wall of the conductive contact hole 13 and the upper surface of the first dielectric layer 12, and defines a first deposition hole 21. Figure 4 It can be seen that the conductive contact hole 13 includes a first conductive hole 131 and a second conductive hole 132 that are connected. It can be understood that the metal sulfide layer 20 covers the bottom wall and side walls of the first conductive hole 131 and the peripheral wall of the second conductive hole 132 respectively.

[0088] S1033 , performing a removal process to retain the metal sulfide layer 20 covering the surface of the substrate 11 .

[0089] refer to Figure 7 The metal sulfide layer 20 formed on the first dielectric layer 12 is removed by a removal process to obtain the metal sulfide layer 20 covering the surface of the substrate 11 .

[0090] In some embodiments, after forming the metal sulfide layer 20 on the substrate 10 in step S1031, the step further includes:

[0091] S1035 , forming a first sacrificial layer 60 covering the metal sulfide layer 20 .

[0092] refer to Figure 5 A first sacrificial layer 60 is formed on the substrate 10 using a deposition process. The first sacrificial layer 60 is formed to cover the inner wall of the first deposition hole 21 and extends from the opening of the first deposition hole 21 toward the outer edge of the substrate 10 to cover the upper surface of the metal sulfide layer 20. The material of the first sacrificial layer 60 includes, but is not limited to, oxide.

[0093] In the embodiment of the present application, during the semiconductor manufacturing process, a first sacrificial layer 60 covering the metal sulfide layer 20 is formed to avoid damage to the metal sulfide layer 20 during the process of etching back the metal sulfide layer 20 .

[0094] In some embodiments, the removal process in step S1033 to retain the metal sulfide layer 20 covering the surface of the substrate 11 includes:

[0095] S1034, remove the first sacrificial layer 60 and the metal sulfide layer 20 formed on the first dielectric layer 12 to retain the metal sulfide layer 20 formed on the surface of the substrate 11, refer to Figure 7 , Figure 7 A metal sulfide layer 20 formed on a substrate is schematically shown.

[0096] In some embodiments, the step S1034 of removing the first sacrificial layer 60 and the metal sulfide layer 20 formed on the first dielectric layer 12 and retaining the metal sulfide layer 20 formed on the surface of the substrate 11 includes:

[0097] S10341, forming a patterned first mask layer 70 on the surface of the first sacrificial layer 60, wherein the first mask layer 70 defines a first etching window 71;

[0098] The mask layer may be etched to form a patterned first mask layer 70. Figure 6The patterned first mask layer 70 is formed with a first etching window 71, which is adapted to the size of the conductive contact hole 13. First etching windows 71 of different sizes can be formed on the first mask layer 70 as needed to adapt to conductive contact holes 13 of different sizes.

[0099] S10342, performing back etching according to the first etching window 71 to etch away the metal sulfide layer 20 and the first sacrificial layer 60 in the second conductive hole 132 until they are flush with the upper surface of the substrate;

[0100] Taking the upper surface of the substrate 11 as the stop interface, it can be understood that the upper surface of the substrate 11 is the surface connected to the lower surface of the first dielectric layer 12. The metal sulfide layer 20 and the first sacrificial layer 60 in the second conductive hole 132 are etched away by an etch-back process.

[0101] S10343 , removing the metal sulfide layer 20 , the first sacrificial layer 60 and the first mask layer 70 on the first dielectric layer 12 , and the first sacrificial layer 60 on the metal sulfide layer 20 of the substrate 11 .

[0102] The metal sulfide layer 20, the first sacrificial layer 60 and the first mask layer 70 on the first dielectric layer 12 and the first sacrificial layer 60 on the metal sulfide layer 20 of the substrate 11 are removed by a removal process, including but not limited to wet cleaning. Figure 7 , Figure 7 This is the morphology of the semiconductor after the removal process.

[0103] In some embodiments, step S105 of forming the semi-metal layer 30 covering the exposed surface of the metal sulfide layer 20 includes:

[0104] S1051, forming a semi-metal layer 30 on the substrate 10, the semi-metal layer 30 covering the upper surface of the substrate 10, the inner wall of the conductive contact hole 13 and the surface of the metal sulfide layer 20;

[0105] A semi-metal layer 30 is formed on the substrate 10 by a deposition process. Figure 8 The semi-metal layer 30 covers the inner wall of the second conductive hole 132 , the exposed surface of the metal sulfide layer 20 , and the upper surface of the first dielectric layer 12 , and defines a second deposition hole 31 .

[0106] S1053 , forming a second sacrificial layer 80 covering the semi-metal layer 30 ;

[0107] A second sacrificial layer 80 is formed on the substrate 10 by a deposition process. Figure 8 The second sacrificial layer 80 is formed to fill the second deposition hole 31 and cover the upper surface of the half-metal layer 30 .

[0108] S1055, remove the second sacrificial layer 80 and the semi-metal layer 30 formed on the first dielectric layer 12. Figure 10 After removing the second sacrificial layer 80 and the semi-metal layer 30 formed on the first dielectric layer 12 , the semi-metal layer 30 is formed on the surface of the metal sulfide layer 20 .

[0109] In some embodiments, the step S1055 of removing the second sacrificial layer 80 and the semi-metal layer 30 formed on the first dielectric layer 12 includes:

[0110] S10551, forming a patterned second mask layer 90 on the surface of the second sacrificial layer 80, wherein the second mask layer 90 defines a second etching window 91;

[0111] The mask layer may be etched to form a patterned second mask layer 90. Figure 9 The patterned second mask layer 90 is formed with a second etching window 91, and the size of the second etching window 91 is adapted to the size of the conductive contact hole 13. Second etching windows 91 of different sizes can be formed on the second mask layer 90 as needed to adapt to conductive contact holes 13 of different sizes.

[0112] S10552, using the substrate 11 as a stop layer, performing back etching according to the second etching window 91 to etch away the semi-metal layer 30 and the second sacrificial layer 80 in the second conductive hole 132;

[0113] Taking the upper surface of the substrate 11 as the stop interface, it can be understood that the upper surface of the substrate 11 is the surface connected to the lower surface of the first dielectric layer 12. The semi-metal layer 30 and the second sacrificial layer 80 in the second conductive hole 132 are etched away by an etch-back process.

[0114] S10553 , removing the semi-metal layer 30 , the second sacrificial layer 80 and the second mask layer 90 on the first dielectric layer 12 , and the second sacrificial layer 80 on the semi-metal layer 30 .

[0115] The semi-metal layer 30, the second sacrificial layer 80 and the second mask layer 90 on the first dielectric layer 12 and the second sacrificial layer 80 on the semi-metal layer 30 of the substrate 11 are removed by a removal process including but not limited to wet cleaning. Figure 10 , Figure 10 This is the morphology of the semiconductor after the removal process.

[0116] In some embodiments, step S107 of forming a barrier layer 40 on the substrate 10 , where the barrier layer 40 covers the surface of the semi-metal layer 30 and the sidewalls of the conductive contact hole 13 , includes:

[0117] A barrier layer 40 is formed on the substrate 10 by a deposition process. The barrier layer 40 is made of titanium nitride. Figure 1 The barrier layer 40 covers the inner wall of the second conductive via 132 and the exposed surface of the semi-metal layer 30 .

[0118] In some embodiments, step S109 of filling the receiving hole 41 formed by the barrier layer 40 with a conductive material to form the conductive contact structure 50 includes:

[0119] Using deposition process in the accommodation hole 41 (accommodation hole in Figure 11 (shown in FIG) is filled with a conductive material, the conductive material being made of tungsten. Figure 1 ,Depend on Figure 1 It can be seen that the receiving hole 41 is completely filled with the conductive material.

[0120] In some embodiments, the barrier layer 40 is formed to cover the surface of the semi-metal layer 30 and the sidewalls of the conductive contact hole 13, and is formed to extend from the opening of the conductive contact hole 13 to the outer edge of the substrate 10 to cover the upper surface of the substrate 10. It is understood that, referring to Figure 11 The upper surface of the substrate 10 is the upper surface of the first dielectric layer 12 .

[0121] refer to Figure 11 , Figure 11 As can be seen in FIG, after the barrier layer 40 is formed in the conductive contact hole 13 , the barrier layer 40 is further deposited on the upper surface of the first dielectric layer 12 . The formed barrier layer 40 covers the upper surface of the first dielectric layer 12 .

[0122] In some embodiments, the conductive contact structure 50 is formed to fill the receiving hole 41 and to extend from the opening of the receiving hole 41 toward the outer edge of the substrate 10 to cover the upper surface of the barrier layer 40 .

[0123] refer to Figure 12 , Figure 12 As can be seen in FIG, after the conductive contact structure 50 is formed in the receiving hole 41 , a conductive material is continuously deposited on the upper surface of the barrier layer 40 , so that the formed conductive contact structure 50 covers the upper surface of the barrier layer 40 .

[0124] In some embodiments, after removing the first sacrificial layer 60 located in the first conductive via 131 , the method further includes: removing the metal sulfide layer 20 to form a groove-shaped morphology on the upper surface of the metal sulfide layer 20 .

[0125] refer to Figure 7 By removing the exposed surface of the metal sulfide layer 20 , a groove-shaped morphology is formed on the upper surface of the metal sulfide layer 20 .

[0126] In the embodiment of the present application, a groove-shaped morphology is formed on the upper surface of the metal sulfide layer 20 to increase the contact area between the semi-metal layer 30 and the barrier layer 40 or the conductive contact structure 50, thereby further reducing the contact resistance.

[0127] According to a third aspect of an embodiment of the present application, a memory is provided, comprising the above-mentioned semiconductor structure.

[0128] It is understood that the semiconductor structure manufactured according to the above embodiments can be applied to the manufacture of a variety of integrated circuits (ICs). The IC according to the present application is, for example, a memory circuit, such as a random access memory (RAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a static RAM (SRAM), or a read-only memory (ROM), etc. The IC according to the present application can also be a logic device, such as a programmable logic array (PLA), an application-specific integrated circuit (ASIC), a merged DRAM logic integrated circuit (buried DRAM), a radio frequency circuit, or any other circuit device. The IC chip according to the present application can be used in, for example, consumer electronic products, such as personal computers, portable computers, game consoles, cellular phones, personal digital assistants, video cameras, digital cameras, mobile phones, and other electronic products.

[0129] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. The schematic descriptions of these terms throughout this specification do not necessarily refer to the same embodiment or example.

[0130] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0131] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate, wherein a conductive contact hole is formed on the substrate; a metal sulfide layer formed in the conductive contact hole and covering a bottom wall of the conductive contact hole; a semi-metal layer, wherein the semi-metal layer is formed on the surface of the metal sulfide layer; a barrier layer, the barrier layer covering a surface of the semi-metal layer and a sidewall of the conductive contact hole; The conductive contact structure is arranged in the accommodating hole formed by the barrier layer.

2. The semiconductor structure according to claim 1, wherein The base comprises a substrate and a first dielectric layer formed on the substrate, and the conductive contact hole penetrates the first dielectric layer and extends into the substrate; The conductive contact hole includes a first conductive hole formed in the substrate and a second conductive hole formed in the first dielectric layer, and a radial dimension of the first conductive hole is larger than a radial dimension of the second conductive hole.

3. The semiconductor structure according to claim 1, wherein: The material of the metal sulfide layer is molybdenum sulfide or tungsten sulfide, and the material of the semi-metal layer includes a Group VA semi-metal element.

4. The semiconductor structure according to claim 1, wherein: The barrier layer covers the surface of the semi-metal layer and the sidewalls of the conductive contact hole, and covers the upper surface of the substrate; the conductive contact structure fills the accommodating hole and covers the upper surface of the barrier layer.

5. The semiconductor structure according to claim 1, wherein Also includes: The radial dimension of the metal sulfide layer is greater than the radial dimension of the conductive contact structure; The upper surface of the metal sulfide layer has a groove-shaped morphology.

6. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate, and forming a conductive contact hole on the substrate; forming a metal sulfide layer in the conductive contact hole to cover the bottom wall of the conductive contact hole; forming a semi-metallic layer covering the exposed surface of the metal sulfide layer; forming a barrier layer on the substrate, wherein the barrier layer covers the surface of the semi-metal layer and the sidewalls of the conductive contact hole; The receiving hole formed by the barrier layer is filled with a conductive material to form a conductive contact structure.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: The forming of a conductive contact hole on the substrate comprises: The substrate is processed by an etching process to form the conductive contact hole on the substrate.

8. The method for manufacturing a semiconductor structure according to claim 6, wherein: The base includes a substrate and a first dielectric layer formed on the substrate, and the conductive contact hole penetrates the first dielectric layer and extends into the substrate to expose the surface of the substrate; The conductive contact hole includes a first conductive hole formed in the substrate and a second conductive hole formed in the first dielectric layer, and a radial dimension of the first conductive hole is larger than a radial dimension of the second conductive hole.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein: The step of forming a metal sulfide layer in the conductive contact hole and covering the bottom wall of the conductive contact hole comprises: forming a metal sulfide layer on the substrate, wherein the metal sulfide layer covers the upper surface of the substrate and the inner wall of the conductive contact hole; A removal process is performed to retain the metal sulfide layer covering the surface of the substrate.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein: After forming the metal sulfide layer on the substrate, the method further comprises: A first sacrificial layer is formed covering the metal sulfide layer.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein: The performing of the removal process to retain the metal sulfide layer covering the surface of the substrate includes: The first sacrificial layer and the metal sulfide layer formed on the first dielectric layer are removed to retain the metal sulfide layer formed on the surface of the substrate.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein: The removing of the first sacrificial layer and the metal sulfide layer formed on the first dielectric layer to retain the metal sulfide layer formed on the surface of the substrate includes: forming a patterned first mask layer on a surface of the first sacrificial layer, wherein the first mask layer defines a first etching window; Performing back etching according to the first etching window to etch away the metal sulfide layer and the first sacrificial layer in the second conductive hole until they are flush with the upper surface of the substrate; The metal sulfide layer, the first sacrificial layer and the first mask layer on the first dielectric layer, and the first sacrificial layer located in the first conductive hole are removed.

13. The method for manufacturing a semiconductor structure according to claim 11, wherein: The forming of a semi-metal layer covering the exposed surface of the metal sulfide layer comprises: forming a semi-metal layer on the substrate, wherein the semi-metal layer covers the upper surface of the substrate, the inner wall of the conductive contact hole and the surface of the metal sulfide layer; forming a second sacrificial layer covering the semi-metal layer; The second sacrificial layer and the semi-metal layer formed on the first dielectric layer are removed.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein: The removing of the second sacrificial layer and the semi-metal layer formed on the first dielectric layer comprises: forming a patterned second mask layer on a surface of the second sacrificial layer, wherein the second mask layer defines a second etching window; Performing back etching according to the second etching window to etch away the semi-metal layer and the second sacrificial layer in the second conductive hole until they are flush with the upper surface of the substrate; The semi-metal layer, the second sacrificial layer, the second mask layer on the first dielectric layer, and the second sacrificial layer on the semi-metal layer are removed.

15. The method for manufacturing a semiconductor structure according to claim 12, wherein: After removing the first sacrificial layer located in the first conductive hole, the method further includes: The metal sulfide layer is subjected to a removal treatment to form a groove-shaped morphology on the upper surface of the metal sulfide layer.

16. A memory, characterized in that: The semiconductor structure comprises the semiconductor structure according to any one of claims 1 to 5.

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