A packaging structure and a method of manufacturing the same

Abstract

The application relates to the technical field of chip packaging, in particular to a packaging structure and a preparation method thereof. The packaging structure comprises a substrate, a solder resist layer and a cover substrate. The solder resist layer has at least two windowed areas exposing the substrate, and the at least two windowed areas are not connected. A bump pad is arranged on the substrate and located in the windowed area, so that the windowed area is reduced, the area of the solder resist layer is increased, the contact area between the solder resist layer and the filling glue is increased, the thermal expansion coefficient between the solder resist layer and the filling glue is improved compared with the thermal expansion coefficient between copper and the filling glue, and the delamination phenomenon between the substrate and the filling glue is effectively avoided.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a packaging structure and its fabrication method. Background Technology

[0002] Flip-chip packaging is an advanced chip interconnect technology characterized by high density, high performance, and thinness. Flip-chip interconnect technology mainly uses solder ball bumps or copper pillar bumps for interconnection. As electronic products become smaller, there is a need to achieve more I / O and higher bandwidth on smaller chips, as well as to take better heat dissipation measures.

[0003] Among them, the gap between copper pillar bumps is smaller than that between solder ball bumps. However, if each bump has a separate solder mask window, the spacing between the windows cannot meet the process requirements.

[0004] For example, such as Figure 1 As shown, bump pad 101 corresponds to solder mask window 102, and bump pad 103 corresponds to solder mask window 104. Since the distance between bump pads 101 and 103 is 65μm, and based on flip-chip manufacturing experience, the solder mask window must be at least 29μm larger than the bump pad on one side. Therefore, the distance between adjacent solder mask windows 102 and 104 is only 7μm. This distance does not meet the spacing rules for solder mask windows in substrate manufacturing. Therefore, the prior art proposes a solder mask windowing method 105 that extends 100μm outward from the chip edge, opening windows in the entire area within the extended boundary.

[0005] However, using the above-mentioned window opening method 105 will cause delamination between the substrate and the filler. This is because the coefficients of thermal expansion of the large area of ​​copper exposed at the window opening are mismatched with those of the filler, resulting in high interfacial stress and thus causing delamination.

[0006] Therefore, how to improve this stratification phenomenon is a technical problem that urgently needs to be solved. Summary of the Invention

[0007] In view of the above problems, the present invention is proposed to provide a packaging structure and a method for preparing the same to overcome or at least partially solve the above problems.

[0008] In a first aspect, the present invention provides a packaging structure, comprising:

[0009] substrate;

[0010] A solder resist layer covering the substrate, the solder resist layer having at least two open areas exposing the substrate, the at least two open areas being non-connected;

[0011] The bump pads are disposed on the substrate and located within the window area.

[0012] Furthermore, the distance between the boundary of each window area and the boundary of the bump pad within the window area is greater than a preset value, and the boundary of the bump pad is the position of the bump pad near the window area.

[0013] Furthermore, the gap between adjacent bump pads within each window area is within a preset range.

[0014] Furthermore, within each of the stated window areas, the bump pads are aligned in both the row and column directions.

[0015] Furthermore, within each window area, the bump pads are aligned in the row direction and staggered in the column direction.

[0016] Furthermore, within a portion of the windowed area, the bump pads are aligned in both the row and column directions;

[0017] In the remaining windowed area, the bump pads are aligned in the row direction and staggered in the column direction.

[0018] Furthermore, the solder resist layer has a first window area, a second window area, and a third window area that expose the substrate;

[0019] The first window opening area, the second window opening area, and the third window opening area are not connected.

[0020] The bump pads are disposed on the substrate and are located in the first window area, the second window area, and the third window area.

[0021] Secondly, the present invention also provides a chip, comprising:

[0022] A packaging structure, wherein the packaging structure comprises the packaging structure according to any one of claims 1 to 7;

[0023] The first chip includes connection bumps, which are connected to the pad bumps in a one-to-one correspondence.

[0024] Thirdly, the present invention also provides a method for preparing a packaging structure, comprising:

[0025] A substrate is provided, wherein the substrate has bump pads and is covered with a solder resist layer;

[0026] At least two windowed areas are formed at the location of the solder mask corresponding to the bump pad to expose the bump pad, wherein at least two of the windowed areas are not connected.

[0027] Furthermore, the distance between the boundary of each window area and the boundary of the bump pad within the window area is greater than a preset value, and the boundary of the bump pad is the position of the bump pad near the window area.

[0028] The gap between adjacent bump pads within each window area is within a preset range.

[0029] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0030] This invention provides a packaging structure, including: a substrate, a solder resist layer, and a cover substrate. The solder resist layer has at least two open areas that expose the substrate, and the at least two open areas are not connected. A bump pad is disposed on the substrate and located within the open area, thereby reducing the open area and increasing the area of ​​the solder resist layer. This increases the contact area between the solder resist layer and the filler adhesive, and the coefficient of thermal expansion between the solder resist layer and the filler adhesive is improved compared to the coefficient of thermal expansion between copper and the filler adhesive, thereby effectively avoiding delamination between the substrate and the filler adhesive. Attached Figure Description

[0031] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0032] Figure 1 This diagram illustrates a structural schematic of a windowed solder resist layer in the prior art.

[0033] Figure 2 A schematic diagram of the packaging structure in an embodiment of the present invention is shown;

[0034] Figure 3 A schematic diagram of a window area with constraints is shown in an embodiment of the present invention;

[0035] Figure 4a , Figure 4b A schematic diagram of the windowed area formed by the bump pads arranged in the first manner in an embodiment of the present invention is shown.

[0036] Figure 5a , Figure 5b A schematic diagram of the window area formed by the bump pads arranged in the second manner in an embodiment of the present invention is shown.

[0037] Figure 6 A schematic diagram of the window area formed by the bump pads arranged in a third manner in an embodiment of the present invention is shown.

[0038] Figure 7 A schematic diagram of a structure with three windowed areas is shown in an embodiment of the present invention;

[0039] Figure 8 A schematic diagram of the chip structure in an embodiment of the present invention is shown;

[0040] Figure 9 A schematic flowchart of the preparation method of the packaging structure in an embodiment of the present invention is shown. Detailed Implementation

[0041] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0042] Example 1

[0043] Embodiments of the present invention provide a packaging structure, such as Figure 2 As shown, it includes:

[0044] substrate 201;

[0045] A solder resist layer 202 covers the substrate 201. The solder resist layer 202 has at least two open areas 203 that expose the substrate 201. The at least two open areas 203 are not connected to each other.

[0046] The bump pad 204 is disposed on the substrate 201 and located within the window area 203.

[0047] Substrate 201 is a basic material for manufacturing PCBs. Generally, the substrate is a copper-clad laminate. Substrate materials are fundamental materials for manufacturing semiconductor components and printed circuit boards, such as silicon, gallium arsenide, and silicon epitaxial nuclei (Gartenolite) used in the semiconductor industry. Ceramic substrates, made primarily from high-purity alumina (bauxite) through high-pressure molding, high-temperature firing, and then cutting and polishing, are the basic materials for manufacturing thick-film and thin-film circuits. Copper-clad laminates (or simply laminates) are the substrate materials for manufacturing printed circuit boards. Besides supporting various components, they also enable electrical connections or insulation between them.

[0048] Solder mask 202 refers to the portion of the substrate covered with green solder mask. Solder mask material must be applied using a liquid wet process or a dry film lamination. Dry film solder mask is supplied in thicknesses of 0.07–0.1 mm and is suitable for some surface mount products; however, this material is not recommended for close-pitch applications. Low-profile liquid photosensitive solder mask is typically specified for surface mount applications, providing precise feature dimensions and gaps.

[0049] The bump pad 204 is a bump used to connect the flip chip, thereby enabling the connection between the flip chip and the substrate 201.

[0050] The at least two windowed areas 203 in this invention are achieved by opening windows in separate areas. On the one hand, compared with the method of opening windows around each bump pad in related technologies, it is not affected by the small gap between bump pads and the difficulty of opening windows. On the other hand, the method of opening windows in separate areas does not reduce the area of ​​the solder mask layer as in another related technology, which causes the substrate and filler to delaminate when the flip chip is packaged later, thus reducing chip performance.

[0051] The following are the restrictions on the window area:

[0052] In one optional implementation, the distance between the boundary of each window area 203 and the boundary of the bump pad 204 within the window area 203 is greater than a preset value, and the boundary of the bump pad 204 is the position of the bump pad 204 near the window area 203.

[0053] like Figure 3 As shown, the preset value is 30μm, which means that the distance between the boundary of each window area 203 and the boundary of the bump pad 204 within the window area 203 is greater than 30μm.

[0054] Specifically, the distance between the upper boundary of each window region 203 and the upper boundary of the bump pad 204 within the window region 203 is greater than 30 μm; the distance between the lower boundary of each window region 203 and the lower boundary of the bump pad 204 within the window region 203 is greater than 30 μm; the distance between the left boundary of each window region 203 and the lower boundary of the bump pad 204 within the window region 203 is greater than 30 μm; and the distance between the right boundary of each window region 203 and the right boundary of the bump pad 204 within the window region 203 is greater than 30 μm.

[0055] The resulting window area 203 can be a regular shape, or it can be an irregular shape.

[0056] The method for defining the window area 203 is as follows: the gap between adjacent bump pads 204 is divided into a window area that meets the preset range.

[0057] Specifically, the gap between adjacent bump pads 204 within each window area 203 is within a preset range, which is greater than or equal to 70 μm and less than or equal to 100 μm. For example... Figure 3 As shown.

[0058] Let's first introduce the arrangement of the 204 bump pads within the windowed area. The bump pads within the windowed area are arranged in an array, including multiple rows and columns:

[0059] The first method involves aligning the bump pads 204 in both the row and column directions within each window area. Individual bump pads 204 can be arranged horizontally or vertically, such as... Figure 4a , Figure 4b As shown.

[0060] For the first arrangement, the corresponding window area 203 can be a regular shape. That is, the top, bottom, left, and right boundaries of the window area form a rectangle.

[0061] The second method involves aligning the bump pads 204 in the row direction and staggering them in the column direction within each window area. For example, the window area includes two rows of bump pads 204, and the center line of the bump pads 204 in the second row is aligned with the center line of the bump pads 204 in the adjacent column direction of the first row. Specifically... Figure 5a As shown. The number of bump pads 204 in the first row is equal to the number of bump pads 204 in the second row. Therefore, after the row alignment and column misalignment settings, the bump pads 204 in the second row can be moved forward or backward as a whole compared to the bump pads 204 in the first row, which is not limited here.

[0062] For the second arrangement, the corresponding window area 203 can be irregular in shape. Since the shape formed by the boundary of the bump pad 204 is irregular, the window area formed around the boundary of the bump pad 204 is also irregular in shape, specifically as follows... Figure 5a As shown, a broken line is formed in the left and right boundaries of the bump pad 204, and the boundary of the window area 203 formed around this broken line is also a broken line, that is, an irregular boundary, thus forming an irregularly shaped window area.

[0063] Of course, for this second arrangement, the irregularly shaped window area 203 can be expanded outward to form a regularly shaped window area 203, as shown in the following example. Figure 5b As shown. Specifically, it will be as follows: Figure 5a The recessed part of the boundary of the window area formed in the middle is expanded outward so that the recessed boundary is flush with the non-recessed boundary, so as to form a window area 203 with a regular shape.

[0064] The third method involves aligning the bump pads 204 in both the row and column directions within a portion of the windowed area; in the remaining windowed area, the bump pads 204 are aligned in the row direction but staggered in the column direction. Figure 6 As shown.

[0065] For the third arrangement, the window areas 203 of the bump pads 204, which are aligned in both the row and column directions, have a regular shape, such as... Figure 6 The second window area in the diagram; for the bump pads 204, the window area 203, which is aligned in the row direction and staggered in the column direction, can be a regular shape, such as... Figure 6 The third window area in the middle; or an irregular shape, specifically as follows: Figure 6 The first windowed area in the middle.

[0066] In any of the above arrangement methods, the bump pads in each window area are arranged horizontally or vertically.

[0067] like Figure 7 As shown, the solder mask layer 202 has a first window area, a second window area, and a third window area that expose the substrate 201; the first window area A, the second window area B, and the third window area C are not connected. The bump pads 204 are disposed on the substrate 201 and are located within the first window area, the second window area, and the third window area.

[0068] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0069] This invention provides a packaging structure, including: a substrate, a solder resist layer, and a cover substrate. The solder resist layer has at least two open areas that expose the substrate, and the at least two open areas are not connected. A bump pad is disposed on the substrate and located within the open area, thereby reducing the open area and increasing the area of ​​the solder resist layer. This increases the contact area between the solder resist layer and the filler adhesive, and the coefficient of thermal expansion between the solder resist layer and the filler adhesive is improved compared to the coefficient of thermal expansion between copper and the filler adhesive, thereby effectively avoiding delamination between the substrate and the filler adhesive.

[0070] Example 2

[0071] Based on the same inventive concept, the present invention also provides a chip, such as... Figure 8 As shown, it includes:

[0072] The packaging structure 801 includes the packaging structure in Embodiment 1;

[0073] The first chip 802 includes connection bumps, which are connected to pad bumps in a one-to-one correspondence.

[0074] This also includes: filler adhesive surrounding the connection bumps between the package structure 801 and the first chip 802.

[0075] The first chip is specifically a flip chip. A flip chip is a leadless structure containing circuit units for electrical and mechanical connection to a substrate circuit via an appropriate number of connection bumps located on the chip surface.

[0076] When connecting the first chip 802 (flip chip) to the substrate 801, the large amount of solder resist layer retained on the packaging structure 801 results in a larger contact area between the solder resist layer and the filler, effectively improving the adhesion between the filler and the substrate, reducing the interfacial stress between the filler and the substrate, and effectively improving the delamination phenomenon between the filler and the substrate.

[0077] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:

[0078] This invention provides a chip, comprising: a packaging structure, including any of the packaging structures described in Embodiment 1; a first chip including connection bumps, which are connected one-to-one with solder pad bumps. Due to the reduction in the window area on the packaging structure and the increase in the area of ​​the solder resist layer, there is a filler adhesive between the first chip and the substrate of the packaging structure, and around the connection bumps. The coefficient of thermal expansion between the solder resist layer of the substrate and the filler adhesive is improved compared to the coefficient of thermal expansion between copper and the filler adhesive, thereby effectively avoiding delamination between the substrate and the filler adhesive and improving chip performance.

[0079] Example 3

[0080] Based on the same inventive concept, embodiments of the present invention also provide a method for preparing a packaging structure, such as... Figure 9 As shown, it includes:

[0081] S901 provides a substrate having bump pads and a solder resist layer.

[0082] S902, at least two windowed areas are formed on the solder mask layer at the positions corresponding to the bump pads to expose the bump pads, wherein at least two windowed areas are not connected to each other.

[0083] In one optional implementation, the distance between the boundary of each window area and the boundary of the bump pad within the window area is greater than a preset value, and the boundary of the bump pad is the position of the bump pad near the window area.

[0084] The preset value is 30μm, meaning that the distance between the boundary of each window area and the boundary of the bump pad within the window area is greater than 30μm.

[0085] In one alternative implementation, the gap between adjacent bump pads within each window area is within a preset range.

[0086] The preset range is greater than or equal to 70μm and less than or equal to 100μm.

[0087] After obtaining the aforementioned windowed area, the connection bumps of the flip chip are encapsulated through the bump pads on the substrate. Filler adhesive is then filled between the flip chip and the substrate, resulting in a larger contact area between the filler adhesive and the solder resist layer on the substrate. The coefficient of thermal expansion between the solder resist layer on the substrate and the filler adhesive is improved compared to that between copper and the filler adhesive, thereby effectively preventing delamination between the substrate and the filler adhesive and improving the performance of the packaged chip.

[0088] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0089] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A packaging structure, characterized in that, include: substrate; A solder resist layer covering the substrate, the solder resist layer having at least two open areas exposing the substrate, the at least two open areas being non-connected; A bump pad is disposed on the substrate and located within the window area; The distance between the boundary of each window area and the boundary of the bump pad within the window area is greater than a preset value of 30 μm. The boundary of the bump pad is the position of the bump pad near the window area. The gap between adjacent bump pads in each window area is within a preset range, which is greater than or equal to 70 μm and less than or equal to 100 μm. Within each window area, the bump pads are aligned in the row direction and staggered in the column direction; Within a portion of the windowed area, the bump pads are aligned in both the row and column directions; In the remaining windowed area, the bump pads are aligned in the row direction and staggered in the column direction.

2. The packaging structure according to claim 1, characterized in that, Within each window area, the bump pads are aligned in both the row and column directions.

3. The packaging structure according to any one of claims 1 to 2, characterized in that, The solder resist layer has a first window area, a second window area, and a third window area that expose the substrate. The first window opening area, the second window opening area, and the third window opening area are not connected. The bump pads are disposed on the substrate and are located in the first window area, the second window area, and the third window area.

4. A chip, characterized in that, include: The packaging structure includes the packaging structure according to any one of claims 1 to 3; The first chip includes connection bumps, each of which is connected to a corresponding bump pad.

5. A method for preparing a packaging structure, characterized in that, include: A substrate is provided, wherein the substrate has bump pads and is covered with a solder resist layer; At least two windowed areas are formed at the location of the solder mask corresponding to the bump pad to expose the bump pad, wherein at least two of the windowed areas are not connected.

6. The method according to claim 5, characterized in that, The distance between the boundary of each window area and the boundary of the bump pad within the window area is greater than a preset value, and the boundary of the bump pad is the position of the bump pad close to the window area. The gap between adjacent bump pads within each window area is within a preset range.

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