power device

Abstract

The embodiment of the present application discloses a power device. The power device comprises a first control electrode, a second control electrode, a first electrode and a second electrode; wherein the first electrode and the second electrode have a semiconductor structure therebetween; and the second control electrode is used for switching on or off the state between the first electrode and the second electrode under the action of voltage on the first control electrode.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and to, but is not limited to, a power device. Background Technology

[0002] Throughout the entire lifecycle of a semiconductor power device—from manufacturing, packaging, and transportation, and even within the finished device itself—it constantly faces the impact of electrostatic discharge (ESD). When the static charge accumulated in a semiconductor power device flows into the device's interior through its electrodes, the resulting instantaneous current or voltage can damage or even cause the device to fail.

[0003] Therefore, how to protect semiconductor power devices from ESD has become an urgent problem to be solved. Summary of the Invention

[0004] In view of this, embodiments of this application provide a power device.

[0005] This application provides a power device, including:

[0006] A first control electrode, a second control electrode, a first electrode, and a second electrode; wherein the first electrode and the second electrode are connected by a semiconductor material; the second control electrode is used to switch the conduction or cutoff state between the first electrode and the second electrode under the action of a voltage on the first control electrode;

[0007] A driving resistor is connected between the first control electrode and the second control electrode;

[0008] An electrostatic discharge protection component is connected between the first control electrode and the first electrode, and is used to conduct and release the electrostatic charge when an electrostatic charge appears on the first control electrode.

[0009] In some embodiments, the electrostatic discharge (ESD) protection assembly includes: a first ESD protection unit and a second ESD protection unit connected in series;

[0010] The second control electrode is also connected between the first electrostatic protection unit and the second electrostatic protection unit.

[0011] In some embodiments, the electrostatic discharge protection component includes alternating P-type semiconductor regions and N-type semiconductor regions.

[0012] In some embodiments, the first electrostatic discharge protection unit is composed of X groups of alternating P-type semiconductor regions and N-type semiconductor regions; the second electrostatic discharge protection unit is composed of Y groups of alternating P-type semiconductor regions and N-type semiconductor regions.

[0013] In some embodiments, the power device further includes: a semiconductor substrate;

[0014] An oxide layer is applied to the semiconductor substrate.

[0015] A polycrystalline silicon layer covers the oxide layer; the polycrystalline silicon layer includes a first doped region and a second doped region; the first doped region is used to form the electrostatic protection component; the second doped region is used to form the driving resistor.

[0016] In some embodiments, a conductive layer is covered on the polycrystalline silicon layer;

[0017] The first control electrode, the second control electrode, and the first electrode are respectively located in different conductive regions of the conductive layer; there are isolation grooves between the different conductive regions.

[0018] In some embodiments, an isolation layer is further provided between the conductive layer and the polysilicon layer;

[0019] The isolation layer includes: multiple isolated areas;

[0020] The isolation region is located within the isolation groove between the different conductive regions.

[0021] In some embodiments, the second control electrode in the conductive layer further includes a first contact structure and a second contact structure that are interconnected.

[0022] The first contact structure is used to connect the electrostatic protection component;

[0023] The second contact structure is used to connect the driving resistor.

[0024] In some embodiments, the connection point between the first contact structure and the electrostatic protection component is located at the junction area of ​​the first electrostatic protection unit and the second electrostatic protection unit.

[0025] In some embodiments, the second contact structure is connected to the surface of the first end of the second doped region; the first control electrode is connected to the surface of the second end of the second doped region.

[0026] The technical solution provided in this application has the following beneficial effects: The power device in this application has a first control electrode and a second control electrode, and a driving resistor is set between the first control electrode and the second control electrode. An electrostatic protection component is set between the first control electrode and the first electrode. In this way, the power device can integrate both the driving resistor and the electrostatic protection component, which improves the integration of the power device and enhances the effect of electrostatic protection. Attached Figure Description

[0027] Figure 1 An equivalent circuit diagram of a power device provided in an embodiment of this application;

[0028] Figure 2 An equivalent circuit diagram of another power device provided in the embodiments of this application;

[0029] Figure 3 A cross-sectional view of an electrostatic protection structure provided in an embodiment of this application;

[0030] Figure 4 A partial cross-sectional view of a power device provided in an embodiment of this application;

[0031] Figure 5 This is an equivalent circuit diagram of an electrostatic protection structure.

[0032] Figure 6 A top view of a power device provided in an embodiment of this application;

[0033] Figure 7 An equivalent circuit diagram of another power device provided in an embodiment of this application;

[0034] Figure 8 An equivalent circuit diagram of another power device provided in the embodiments of this application. Detailed Implementation

[0035] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0037] This application provides a power device 100, such as... Figure 1 As shown, it includes:

[0038] A first control electrode 101, a second control electrode 102, a first electrode 201, and a second electrode 301; wherein the first electrode 201 and the second electrode 301 are connected by a semiconductor material; the second control electrode 102 is used to switch the conduction or cutoff state between the first electrode 201 and the second electrode 301 under the action of the voltage on the first control electrode 101.

[0039] A driving resistor 401 is connected between the first control electrode 101 and the second control electrode 102;

[0040] An electrostatic discharge protection component 402 is connected between the first control electrode 101 and the first electrode 201, and is used to conduct and release the electrostatic charge when an electrostatic charge appears on the first control electrode 101.

[0041] The power devices provided in this application include, but are not limited to, IGBT (Insulated Gate Bipolar Transistor) devices and MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) devices.

[0042] If the power device is an IGBT device, the second control electrode can be used to connect the gate of the IGBT device, the first electrode can be used to connect the emitter or collector of the IGBT device.

[0043] If the power device is a MOS device, the second control electrode can be used to connect the gate of the MOS device, and the first electrode and the second electrode can be used to connect the source or drain of the MOS device.

[0044] A driving resistor exists between the first control electrode and the second control electrode. The voltage signal from the first control electrode reaches the second control electrode through the voltage divider of the driving resistor. The voltage of the second control electrode is used to control the conduction or cutoff of the power device: when the voltage of the second control electrode is higher than the gate turn-on voltage of the power device but lower than the maximum voltage that the gate oxide layer can withstand, the first and second electrodes are in a conducting state; when the voltage of the second control electrode is lower than the gate turn-on voltage of the power device, the first and second electrodes are not conducting, i.e., the power device is in a cutoff state.

[0045] Furthermore, if the voltage of the second control electrode is higher than the breakdown voltage of the gate oxide layer of the power device, the power device will be damaged. In other words, when static electricity is generated at the first control electrode of the power device, it is possible to damage the power device through the second control electrode.

[0046] Therefore, in this embodiment, there is a driving resistor between the first control electrode and the second control electrode.

[0047] In this way, the voltage on the control electrode of the power device, i.e. the first control electrode, will first pass through the voltage division of the driving resistor, thereby reducing the high voltage caused by static electricity from being directly applied to the second control electrode, which would cause the power device to break down, thus achieving the function of protecting the power device.

[0048] Furthermore, in this embodiment, an electrostatic discharge (ESD) protection component is provided between the first control electrode and the first electrode. This ESD protection component provides an ESD leakage path between the first control electrode and the first electrode. The ESD protection component is connected in parallel with the drive resistor and the power device.

[0049] Since the first control electrode is used to apply the signal from an external voltage source to the power device, it is susceptible to electrostatic discharge (ESD), which can generate high voltage. Therefore, ESD protection components and drive resistors can provide ESD protection.

[0050] In some embodiments, when an abnormal overvoltage occurs at the first control electrode, the abnormal voltage can be reduced by a positive voltage drop as it passes through the electrostatic protection component.

[0051] In some embodiments, when an abnormal overvoltage occurs at the first control electrode, the abnormal voltage can be released by breaking down the electrostatic protection component as it passes through the electrostatic protection component, thereby protecting the power device.

[0052] In some embodiments, when an abnormal overvoltage occurs at the first control electrode, the abnormal voltage can be clamped within a safe voltage range as it passes through the electrostatic protection component, thereby protecting the power device.

[0053] The power device provided in this embodiment has a first control electrode and a second control electrode, and a driving resistor is disposed between the first control electrode and the second control electrode. An electrostatic protection component is disposed between the first control electrode and the first electrode. The driving resistor is used to prevent the device from being damaged due to excessively fast switching speed. The electrostatic protection component is used to provide an electrostatic leakage path between the first control electrode and the first electrode.

[0054] In this way, the drive resistor and electrostatic protection components can be integrated into the power device, which improves the integration of the power device and enhances the effect of electrostatic protection.

[0055] In some embodiments, such as Figure 2 As shown, the electrostatic discharge protection assembly 402 includes: a first electrostatic discharge protection unit 403 and a second electrostatic discharge protection unit 404 connected in series.

[0056] The second control electrode is also connected between the first electrostatic protection unit and the second electrostatic protection unit.

[0057] In this way, the electrostatic discharge (ESD) protection component between the first control electrode and the first electrode can serve as an ESD discharge path. The electrostatic charge on the first control electrode can be discharged to the first electrode through the ESD protection component, thereby protecting the power device. The second ESD protection unit between the second control electrode and the first electrode can serve as another discharge path, discharging the electrostatic charge on the second control electrode to the first electrode, thereby improving the effectiveness of ESD protection.

[0058] In some embodiments, such as Figure 3 The electrostatic discharge protection component 402 shown includes alternating P-type semiconductor regions and N-type semiconductor regions.

[0059] By repeatedly doping a semiconductor material, alternating P-type and N-type semiconductor regions can be formed, which are used to form an electrostatic discharge (ESD) protection component. Specifically, P-type semiconductor regions are formed by doping P-type ions into the semiconductor material, and N-type semiconductor regions are formed by doping N-type ions. Adjacent P-type and N-type semiconductor regions can form a PN junction. The semiconductor material can be polycrystalline silicon or germanium, and the doping methods include, but are not limited to, thermal diffusion and ion implantation.

[0060] Figure 3 This is only a schematic diagram of one embodiment; the positions and number of P-type and N-type regions in the diagram can be changed.

[0061] In some embodiments, such as Figure 3 As shown, the first electrostatic discharge protection unit 403 is composed of alternating P-type semiconductor regions and N-type semiconductor regions; the second electrostatic discharge protection unit 404 is composed of alternating P-type semiconductor regions and N-type semiconductor regions.

[0062] The first electrostatic protection unit of the electrostatic protection component can be composed of at least one PN junction, which can play a voltage dividing role. The first electrostatic protection unit can also work with the driving resistor to achieve the effect of current sharing.

[0063] The second electrostatic protection unit of the electrostatic protection assembly may also consist of at least one PN junction. The second electrostatic protection assembly is used to clamp the voltage of the second control electrode between a voltage higher than the gate turn-on voltage of the power device and a voltage lower than the maximum voltage that the gate oxide layer can withstand.

[0064] In some embodiments, such as Figure 4 As shown, the power device 100 further includes: a semiconductor substrate 110;

[0065] An oxide layer 120 covers the semiconductor substrate 110;

[0066] A polysilicon layer 130 covers the oxide layer 120; the polysilicon layer 130 includes a first doped region 501 and a second doped region 502; the first doped region 501 is used to form the electrostatic protection component 403; the second doped region 502 is used to form the driving resistor 401.

[0067] In some embodiments, the first doped region 501 and the second doped region 502 may be isolated from each other by a dielectric layer 131.

[0068] The semiconductor substrate may include a P-type semiconductor material substrate, such as a silicon (Si) substrate or a germanium (Ge) substrate; an N-type semiconductor substrate, such as an indium phosphide (InP) substrate; a composite semiconductor material substrate, such as a germanium-silicon (SiGe) substrate; a silicon-on-insulator (SOI) substrate; and a germanium-on-insulator (GeOI) substrate. An oxide layer is formed on the semiconductor substrate through an oxidation process, including but not limited to wet oxidation and dry oxidation processes.

[0069] In some embodiments, a polycrystalline silicon layer may be formed on the oxide layer. The method of forming the polycrystalline silicon layer includes, but is not limited to, growth processes and deposition processes, wherein the deposition processes include, but are not limited to, dry diffusion, low-pressure chemical vapor deposition, and in-situ vapor reaction.

[0070] In some embodiments, a dielectric layer can be formed first on the oxide layer, followed by the deposition of a photoresist layer on the dielectric layer. A patterned mask is then aligned with the photoresist layer for exposure. Afterward, the non-polymerized photoresist layer is removed, thus forming openings for the first and second doped regions. Polycrystalline silicon is then formed within these openings using deposition or growth processes within the first and second doped regions. The first and second doped regions are separated by a dielectric layer, which can be made of boro-phospho-silicate glass (BPSG).

[0071] In some embodiments, a first doped region and a second doped region can be formed by doping in a polycrystalline silicon layer, wherein the first doped region and the second doped region are separated by the polycrystalline silicon layer. The doping method includes, but is not limited to, thermal diffusion and ion implantation processes. The doping ions can be N-type ions and P-type ions, wherein N-type ions mainly include elements such as phosphorus, arsenic, and antimony, and P-type ions mainly include elements such as boron and indium.

[0072] In some embodiments, the first doped region can be formed by: firstly depositing a photoresist layer on a polysilicon layer; then aligning a patterned mask with the photoresist layer for exposure to form multiple openings, the positions of which are aligned with all regions on the polysilicon requiring P-type ion implantation; then performing a first ion implantation, implanting P-type or N-type ions, thus forming all P-type or N-type ion regions within the first doped region; then covering the formed P-type ion implantation regions with a barrier layer; and then performing a second ion implantation on the remaining regions of the first doped region, implanting N-type ions (when the first implantation was P-type ions) or P-type ions (when the first implantation was N-type ions), thus forming all N-type ion regions within the first doped region; and finally, performing annealing after completing the P-type and N-type ion implantation in the first doped region, thereby forming a combination of multiple PN junctions and / or NP junctions, thus forming an electrostatic discharge (ESD) protection component.

[0073] For example, when the doped region is PNPNPN, two steps are required: photolithography, ion implantation, and removal of non-polymeric photoresist.

[0074] In some embodiments, the first doped region can be formed by: firstly depositing a photoresist layer on a polysilicon layer, then aligning and exposing the photoresist layer with a patterned mask, and then removing the non-polymerized photoresist layer, thus forming an opening in the photoresist layer and exposing the polysilicon layer below the photoresist layer. Then, the exposed polysilicon layer is subjected to a first ion implantation, and the implanted ions can be P-type ions or N-type ions. Finally, the polymerized photoresist layer is removed, thus completing the first ion implantation.

[0075] In the adjacent region after the first ion implantation, another opening is formed using photolithography for a second ion implantation. The second implantation can use either P-type or N-type ions. Then, the polymerized photoresist layer is removed. At this point, the second ion implantation is complete.

[0076] By repeatedly performing photolithography, ion implantation, and removal of the polymerized photoresist layer, the first doped region is formed.

[0077] For example, when the doped region is PNPNPN, six steps of photolithography-ion implantation-removal of nonpolymer photoresist are required.

[0078] In some embodiments, the second doped region may be formed by depositing a photoresist layer on a polysilicon layer, aligning a patterned mask with the photoresist layer for exposure, and then removing the non-polymerized photoresist layer, thus forming an opening on the photoresist layer and exposing the polysilicon layer below the photoresist layer. Then, the exposed polysilicon layer is subjected to a first ion implantation, and the implanted ions may be N-type ions or P-type ions. After the ion implantation is completed, the polymerized photoresist on the polysilicon layer is removed.

[0079] After implanting P-type and N-type ions into the second doped region, annealing is performed, forming a driving resistor within the second doped region. The resistance value of the driving resistor can be between 4 and 20 ohms, and the resistance R is related to parameters such as the type and concentration of implanted ions, the length of the second doped region, and the depth of the second doped region. These parameters can be adjusted to achieve the desired resistance value within the required range.

[0080] In some embodiments, after ion implantation is completed in both the first doped region and the second doped region, they can be annealed together once more.

[0081] By performing doping on a polycrystalline silicon layer through ion implantation or ion diffusion, different doped regions can be formed within selected areas. This facilitates the integration of different semiconductor structures, including electrostatic discharge (ESD) protection components such as diodes and drive resistors, into the device. On the one hand, the manufacturing process is simple and easy to implement; on the other hand, the resulting device has high integration density and occupies a small area.

[0082] In some embodiments, such as Figure 4 As shown, a conductive layer 160 is covered on the polycrystalline silicon layer 130;

[0083] The first control electrode 101, the second control electrode 102 and the first electrode 201 are respectively located in different conductive regions of the conductive layer 160; there is an isolation groove 150 between the different conductive regions.

[0084] A metal layer is deposited or grown on a polysilicon layer as a conductive layer. First, a photoresist layer is deposited on the metal. A patterned mask is aligned with the photoresist layer for exposure. Then, the non-polymerized photoresist layer is removed, thus forming multiple openings in the photoresist layer, exposing the metal layer beneath. The metal is then etched downwards using dry or wet etching processes. The etching stop position of the isolation trenches can be on the polysilicon layer, thus forming multiple isolation trenches. Finally, the polymerized photoresist layer is removed.

[0085] At this time, different conductive regions serve as the first control electrode, the second control electrode, and the first electrode, respectively, and are isolated by different isolation tanks.

[0086] This allows for the formation of multiple electrodes by creating a conductive layer and then dividing that layer into different regions. Furthermore, due to the excellent conductivity of metals, they can be used as conductive electrodes connected to the terminals of power devices, facilitating device control.

[0087] In some embodiments, such as Figure 4 As shown, an isolation layer 140 is also provided between the conductive layer 160 and the polysilicon layer 130;

[0088] The isolation layer 140 includes: multiple isolation regions 141, 142 and 143;

[0089] The isolation regions 141, 142 and 143 are located within the isolation groove 150 between the different conductive regions.

[0090] Before depositing or growing a metal dielectric layer on the polycrystalline silicon layer, an isolation layer can be deposited on the polycrystalline silicon layer. The deposition process for the isolation layer can be chemical vapor deposition or plasma-enhanced atomic layer deposition. The material of the deposited isolation layer can be borosilicate glass.

[0091] First, a layer of photoresist is deposited on the isolation layer. Then, a patterned mask is aligned with the photoresist layer for exposure. After that, the non-polymerized photoresist layer is removed, thus forming multiple openings on the photoresist layer, exposing the isolation layer underneath. The isolation layer is then etched downwards using a dry etching or wet etching process. At this point, the isolation layer is divided into different isolation regions, including an isolation region located on a first doped region that does not completely cover the first doped region, and an isolation region located on a second doped region that does not completely cover the second doped region.

[0092] A metal layer is deposited or grown on a polysilicon layer and an isolation layer to serve as a conductive layer. Isolation trenches are then formed in the conductive layer using photolithography and etching processes. Specifically, in the first doped region, the etching stop point of the isolation trench between the first and second control electrodes can be on the isolation layer, and the etching stop point of the isolation trench formed by photolithography between the second and first control electrodes can also be on the isolation layer. In the second doped region, the etching stop point of the isolation trench formed between the first and second control electrodes can also be on the isolation layer.

[0093] Therefore, the isolation trenches between the different conductive regions have different isolation regions. The isolation regions are used to improve the resistance to charge interference of the electrostatic discharge protection components or drive resistors formed in the underlying polysilicon layer.

[0094] In some embodiments, the second control electrode 102 in the conductive layer 160 further includes a first contact structure 103 and a second contact structure 104 that are interconnected.

[0095] The first contact structure 103 is used to connect the electrostatic protection component 402;

[0096] The second contact structure 104 is used to connect the driving resistor 401.

[0097] The second control electrode in the conductive layer also includes interconnected first and second contact structures. That is, the second control electrode can be an irregular shape with multiple extending contact structures. The first contact structure is part of the second control electrode and is used to connect to an electrostatic discharge (ESD) protection component, i.e., the portion of the polysilicon layer connected to the first contact structure is the ESD protection component on the polysilicon layer. The second contact structure is also part of the second control electrode, and the second contact structure covers a portion of the driving resistor and / or a portion of the isolation region; that is, the second contact structure connects to the driving resistor.

[0098] In some embodiments, the connection position between the first contact structure 103 and the electrostatic protection component 402 is in the junction area of ​​the first electrostatic protection unit 403 and the second electrostatic protection unit 404.

[0099] The first contact structure covers at least a portion of the electrostatic discharge (ESD) protection component in the polysilicon layer, and divides the ESD protection component into a first ESD protection unit and a second ESD protection unit connected in series. Specifically, the first contact structure is connected to the ESD protection component, with the connection point at the junction of the first and second ESD protection units.

[0100] In some embodiments, the second contact structure 104 is connected to the surface of the first end of the second doped region 502; the first control electrode 101 is connected to the surface of the second end of the second doped region 502.

[0101] The second doped region is used to form a driving resistor. The second contact structure covers a portion of the driving resistor and / or a portion of the isolation region, i.e., the second contact structure is connected to the first end of the driving resistor. The first control electrode covers a portion of the driving resistor and / or a portion of the isolation region, i.e., the first control electrode is connected to the second end of the driving resistor. An isolation groove is present between the first control electrode and the second contact structure, i.e., the first control electrode and the second contact structure are not connected. Embodiments of this application also include the following examples:

[0102] ESD phenomena often occur during device packaging, transportation, assembly and use. This will generate a high electric field at the gate of the device, causing the gate dielectric layer to break down under the high electric field, thus causing the device to fail.

[0103] Traditional ESD protection structures such as Figure 5 As shown, a Zener diode is connected to the gate and source to form a leakage channel.

[0104] Traditional ESD protection structures cannot be fabricated in devices simultaneously with integrated drive resistors due to manufacturing limitations.

[0105] The embodiments of this application improve the integration level and ESD protection capability of the device by simultaneously incorporating the ESD protection structure and the integrated drive resistor in the device.

[0106] The top view of the power device provided in the embodiments of this application is as follows: Figure 6 As shown, symmetrical polysilicon driving resistors 401 are designed between the first control electrode 101 and the second control electrode 102. The two driving resistors 401 are connected in parallel and are equivalent to driving resistors. A symmetrical electrostatic discharge (ESD) protection structure 402 is provided between the first control electrode 101, the second control electrode 102, and the first electrode 201. This structure is composed of multiple groups of PNPNP diodes. The clamping voltage of the ESD protection component should be greater than the normal power supply voltage, for example, 15V, and less than the breakdown voltage of the device's gate oxide layer, for example, 40V. Therefore, the clamping voltage can be designed to be 30V, and the diodes in the ESD protection component can be set as PNPNPNP structures.

[0107] The number of diode groups between the second control electrode and the emitter can be set differently according to requirements. The diodes are polysilicon diodes, consistent with polysilicon resistors, thus allowing ESD protection and drive resistor structures to be integrated into the device simultaneously.

[0108] In addition, the second control electrode is connected to the emitter, which ensures that the potential of the second control electrode can be output to the active region, thus ensuring the normal operation of the device.

[0109] Figure 6 The equivalent circuit diagram of the device in the dashed box 200 is as follows: Figure 2 As shown, Figure 6 A cross-sectional view of the dashed box 200 is shown below. Figure 4 As shown.

[0110] In one embodiment, the equivalent circuit diagram is as follows: Figure 7 As shown, the first electrostatic discharge protection unit consists of a forward diode, and the second electrostatic discharge protection unit consists of a forward diode and a reverse diode.

[0111] In one embodiment, the equivalent circuit diagram is as follows: Figure 8 As shown, the first electrostatic discharge protection unit consists of a forward diode and a reverse diode connected in series, and the second electrostatic discharge protection unit consists of a forward diode and a reverse diode.

[0112] The combination of the first electrostatic discharge (ESD) protection unit and the second ESD protection unit is not limited to this. It is sufficient that the voltage of the second control electrode is embedded by the ESD protection component at a voltage higher than the gate turn-on voltage of the power device and lower than the maximum voltage that the gate oxide layer can withstand.

[0113] Because the clamping voltage of the electrostatic discharge (ESD) protection component is greater than the normal power supply voltage, the clamping voltage of the ESD protection component should be less than the breakdown voltage of the device's gate oxide layer. Therefore, when the clamping voltage is 15V and the breakdown voltage of the device's gate oxide layer is 40V, the clamping voltage can be designed to be any value between 15V and 40V. When it is set to 30V, the diode in the ESD protection component can be set to a PNPNPNP structure.

[0114] It is understood that the embodiments of this application have at least the following advantages over related technologies in providing ESD protection for devices:

[0115] 1. The integrated drive resistor enables the device to achieve current sharing.

[0116] 2. Provides an electrostatic discharge channel for the first control electrode and the first electrode to improve ESD reliability;

[0117] 3. ESD protection components and drive resistors can be integrated in the same device, including but not limited to trench gate or planar gate devices, IGBT power devices and MOSFET power devices.

[0118] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0119] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0120] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A power device, characterized in that, The power device includes: A first control electrode, a second control electrode, a first electrode, and a second electrode; wherein the first electrode and the second electrode are connected by a semiconductor material; the second control electrode is used to switch the conduction or cutoff state between the first electrode and the second electrode under the action of a voltage on the first control electrode; A driving resistor is connected between the first control electrode and the second control electrode; An electrostatic discharge protection component is connected between the first control electrode and the first electrode, and is used to conduct and release the electrostatic charge when an electrostatic charge appears on the first control electrode; The electrostatic discharge protection assembly includes: a first electrostatic discharge protection unit and a second electrostatic discharge protection unit connected in series. The second control electrode is also connected between the first electrostatic protection unit and the second electrostatic protection unit; The second electrostatic discharge protection unit includes at least one forward-biased diode and one reverse-biased diode.

2. The power device according to claim 1, characterized in that, The electrostatic discharge protection component includes alternating P-type semiconductor regions and N-type semiconductor regions.

3. The power device according to claim 1, characterized in that, The first electrostatic discharge protection unit is composed of X groups of alternately arranged P-type semiconductor regions and N-type semiconductor regions, where X is greater than or equal to 1. The second electrostatic discharge protection unit consists of Y groups of alternating P-type semiconductor regions and N-type semiconductor regions, where Y is greater than or equal to 2.

4. The power device according to claim 1, characterized in that, The power device further includes: a semiconductor substrate; An oxide layer is applied to the semiconductor substrate. A polycrystalline silicon layer covers the oxide layer; the polycrystalline silicon layer includes a first doped region and a second doped region; the first doped region is used to form the electrostatic protection component; the second doped region is used to form the driving resistor.

5. The power device according to claim 4, characterized in that, A conductive layer is covered on the polycrystalline silicon layer; The first control electrode, the second control electrode, and the first electrode are respectively located in different conductive regions of the conductive layer; there are isolation grooves between the different conductive regions.

6. The power device according to claim 5, characterized in that, An isolation layer is also provided between the conductive layer and the polysilicon layer; The isolation layer includes: multiple isolated areas; The isolation region is located within the isolation groove between the different conductive regions.

7. The power device according to claim 5, characterized in that, The second control electrode in the conductive layer further includes a first contact structure and a second contact structure that are interconnected. The first contact structure is used to connect the electrostatic protection component; The second contact structure is used to connect the driving resistor.

8. The power device according to claim 7, characterized in that, The connection point between the first contact structure and the electrostatic protection component is located at the junction area of ​​the first electrostatic protection unit and the second electrostatic protection unit.

9. The power device according to claim 7, characterized in that, The second contact structure is connected to the surface of the first end of the second doped region; the first control electrode is connected to the surface of the second end of the second doped region.

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