A laser radar module using a chip stacking structure and a chip stacking method thereof

Abstract

The application relates to the technical field of chip packaging, in particular to a laser radar module applying a chip stacking structure and a chip stacking method thereof, wherein the module comprises: Vcsel chips and SPAD chips; the Vcsel chips are flip-chip attached on the SPAD chips, the Vcsel chips and the SPAD chips are respectively provided with a plurality of connecting pins on the attaching surfaces thereof, and the connecting pins of the Vcsel chips are connected with the connecting pins of the SPAD chips in correspondence. The scheme can reduce the structural size of a dToF module product.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of chip packaging, in particular to a laser radar module applying a chip stacking structure and a chip stacking method thereof. BACKGROUND

[0002] The dToF (direct time of flight) module is a module for directly measuring the time of flight and is widely applied to laser ranging technology and 3D imaging technology, and is widely applied to the fields of intelligent mobile terminals, robots, aerospace and automobiles.

[0003] The core components of the dToF module include a VCSEL (vertical cavity surface emitting laser), a SPAD (single photon avalanche diode) and a TDC (time-to-digital converter); the SPAD is a photoelectric detection avalanche diode with single photon detection capability and can generate an electric current as long as there is a weak light signal. The specific working principle of the dToF module is that the VCSEL emits a pulsed wave light signal to the scene, the SPAD receives the pulsed wave light signal reflected from a target object, and the TDC records the time of flight of each received pulsed wave light signal, that is, the time interval between the emission of the pulsed wave light signal and the reception of the pulsed wave light signal; the dToF emits and receives N times of pulsed wave light signals within a single frame measurement time, then performs histogram statistics on the recorded N times of flight times, obtains the flight time with the highest frequency of occurrence, and calculates the depth of the object to be measured.

[0004] In the prior art, the VCSEL chip and the SPAD chip of the dToF module are placed separately and are individually packaged, so that the structure size of the formed dToF module product is large. The main problem is that the SPAD chip and the VCSEL chip are not specially designed to be connected, and the Flip chip flip chip technology cannot be used to connect and conduct through the pins of the circuit. SUMMARY

[0005] One of the purposes of the application is to provide a laser radar module applying a chip stacking structure, which can reduce the structure size of the dToF module product.

[0006] The basic scheme provided by the application is as follows: a laser radar module applying a chip stacking structure, comprising: a Vcsel chip and a SPAD chip;

[0007] The Vcsel chip is flip-chip bonded on the SPAD chip, the Vcsel chip and the SPAD chip are respectively provided with a plurality of connecting pins on the bonding surfaces thereof, and the connecting pins of the Vcsel chip and the connecting pins of the SPAD chip are correspondingly connected.

[0008] Further, the Vcsel chip is flip-chip bonded on the SPAD chip in a flip chip (flip chip technology) form.

[0009] Further, the Vcsel chip is provided with a groove on its bonding surface with the SPAD chip, and a plurality of connecting pins of the Vcsel chip are arranged on the bottom surface of the groove, and a plurality of connecting pins are also arranged on the bonding surface outside the groove.

[0010] Further, the connecting pins of the Vcsel chip and the connecting pins of the SPAD chip are connected in correspondence through gold ball planting.

[0011] Further, an outgoing circuit is arranged on the bonding surface of the SPAD chip and the Vcsel chip, one end of the outgoing circuit is connected with the connecting pins of the SPAD chip, and the other end is provided with a connecting point for connecting with an external circuit.

[0012] Further, a mark point is further arranged on the bonding surface of the SPAD chip and the Vcsel chip for alignment positioning in machine recognition.

[0013] The principle and advantages of the present scheme are that: in the present scheme, the Vcsel chip and the SPAD chip of the dToF module adopt a stacked structure, the Vcsel chip is bonded on the SPAD chip through Flip chip flip-chip, and a plurality of connecting pins are arranged on the bonding surface of the Vcsel chip and the SPAD chip respectively, the connecting pins of the Vcsel chip and the connecting pins of the SPAD chip are connected in correspondence through gold ball planting, so that the Vcsel chip and the SPAD chip are connected and combined through PIN To PIN in a Flip chip packaging process, forming an integrated dToF module chip, the VCSEL chip and the SPAD chip do not need to be placed separately and packaged separately, which greatly reduces the product structure size of the dToF module, and the SPAD chip and the VCSEL chip are designed to have an application link, so that the pins of the line can be linked and conducted through the Flip chip flip-chip process.

[0014] A plurality of connecting pins of the SPAD chip are arranged on its bonding surface with the Vcsel chip, the Vcsel chip is provided with a groove on its bonding surface with the SPAD chip, a plurality of connecting pins of the Vcsel chip are arranged on the bottom surface of the groove, and a plurality of connecting pins are also arranged on the bonding surface outside the groove, so that the Vcsel chip is flip-chip bonded on the SPAD chip, and the connecting pins of the Vcsel chip and the connecting pins of the SPAD chip are in contact, and the gap between the Vcsel chip and the SPAD chip can be reduced due to the arrangement of the groove, so that the bonding is more compact, and the product structure size of the dToF module is further reduced.

[0015] In addition, mark points and lead-out circuits are arranged on the bonding surfaces of the SPAD chip and the Vcsel chip, wherein the mark points are used for alignment positioning during machine recognition, so that the machine can accurately position each chip during processing, thereby ensuring the accuracy of processing; one end of the lead-out circuit is connected with the connecting pins of the SPAD chip, and the other end is provided with a connecting point for connecting with an external circuit, so as to connect the integrated dToF module with other modules.

[0016] The second object of the present application is to provide a chip stacking method applying a chip stacking structure to reduce the structure size of a dToF module product.

[0017] The present application provides a basic scheme two: a chip stacking method applying a chip stacking structure, comprising the following contents:

[0018] S2, gold ball soldering is performed on the connecting pins of the SPAD chip.

[0019] S3, the VCSEL chip is flip-chip bonded on the SPAD chip, and the connecting pins of the Vcsel chip on the bonding surface are soldered and connected with the gold balls.

[0020] Further, it further comprises: S1, arranging the SPAD chip above the substrate.

[0021] Further, it further comprises: S4, bottom dispensing is performed on the SPAD chip.

[0022] Further, it further comprises: S5, integrally integrating the SPAD chip and the VCSEL chip to form a dToF module package.

[0023] The principle and advantages of the present scheme are that: the present scheme is used for processing a dToF module, specifically for processing the above-mentioned laser radar module applying a chip stacking structure, wherein the Vcsel chip and the SPAD chip are processed into a stacking structure, the Vcsel chip is flip-chip bonded on the SPAD chip, and the Vcsel chip and the SPAD chip are respectively provided with a plurality of connecting pins on their bonding surfaces, the connecting pins of the Vcsel chip and the connecting pins of the SPAD chip are connected by corresponding soldering through gold ball implantation, so that the Vcsel chip and the SPAD chip are connected by PIN To PIN, the SPAD chip and the VCSEL chip are integrally integrated to form a dToF module package, and a chip of the integrated dToF module is formed, the VCSEL chip and the SPAD chip do not need to be placed separately and packaged separately, which greatly reduces the structure size of the dToF module product. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is a structure schematic view of the laser radar module applying a chip stacking structure according to the present application;

[0025] Figure 2 A side view of a laser radar module embodiment of the application applying a chip stacking structure;

[0026] Figure 3 A front view of a SPAD chip in a laser radar module embodiment of the application applying a chip stacking structure;

[0027] Figure 4 A structure schematic diagram of a SPAD chip in a laser radar module embodiment of the application applying a chip stacking structure;

[0028] Figure 5 A front view of a VCSEL chip in a laser radar module embodiment of the application applying a chip stacking structure;

[0029] Figure 6 A structure schematic diagram of a VCSEL chip in a laser radar module embodiment of the application applying a chip stacking structure. DETAILED DESCRIPTION

[0030] The following will be further described in detail through specific embodiments:

[0031] The reference signs in the drawings of the specification include: SPAD chip 1, Vcsel chip 2, first connecting pin 101, mark point 102, lead-out circuit 103, connecting point 104, logic area 105, recess 201, second connecting pin 202.

[0032] In the description of the present application, unless otherwise explicitly specified and limited, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance; unless otherwise specified or described, the term "multiple" means two or more; the terms "connection", "fixation" and the like should be understood in a broad sense, for example, "connection" can be fixed connection, or detachable connection, or integrally connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium. For those skilled in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0033] In the description of the present application, it should be understood that the "up", "down", "left", "right" and the like described in the embodiments of the present application are described from the angle shown in the drawings, and should not be understood as limiting the embodiments of the present application. In addition, in the context, it should also be understood that when referring to one element connected to another element "on", "below", "left" or "right", it can not only be directly connected to another element "on", "below", "left" or "right", but also indirectly connected to another element "on", "below", "left" or "right" through an intermediate element.

[0034] Embodiment One

[0035] The embodiment is basically as shown in the accompanying drawings: a laser radar module applying a chip stacking structure, comprising a SPAD chip 1 and a Vcsel chip 2. Figure 1 The Vcsel chip 2 is flip-chip bonded on the SPAD chip 1, as shown in the accompanying drawings, the Vcsel chip 2 and the SPAD chip 1 are respectively provided with a plurality of connecting pins on their bonding surfaces, and the connecting pins of the Vcsel chip 2 are connected with the connecting pins of the SPAD chip 1 correspondingly.

[0036] Figure 2 Specifically, the Vcsel chip 2 is flip-chip bonded on the SPAD chip 1, as shown in the accompanying drawings, a plurality of connecting pins of the SPAD chip 1 are provided on the bonding surface thereof with the Vcsel chip 2, as first connecting pins 101, in this embodiment, the connecting pins are provided in a soldering manner; as shown in the accompanying drawings, the Vcsel chip 2 is provided with a groove 201 on the bonding surface thereof with the SPAD chip 1, a plurality of connecting pins of the Vcsel chip 2 are provided on the bottom surface of the groove 201, a plurality of connecting pins are also provided on the bonding surface outside the groove 201, and the top surfaces of the connecting pins in the groove 201 and the connecting pins outside the groove 201 are in the same plane, as second connecting pins 202, to ensure the stability of the bonding, and the provision of the groove 201 can reduce the gap between the Vcsel chip 2 and the SPAD chip 1, so that the bonding is more compact, further reducing the structure size of the dToF module product; the connecting pins of the Vcsel chip 2 and the connecting pins of the SPAD chip 1 are connected by corresponding soldering through gold ball planting, wherein the soldering is ultrasonic soldering.

[0037] In addition, mark points 102 and lead-out circuits 103 are provided on the bonding surfaces of the SPAD chip 1 and the Vcsel chip 2, wherein the mark points 102 are used for alignment positioning when machine recognition; one end of the lead-out circuit 103 is connected with the connecting pins of the SPAD chip 1, and the other end is provided with a connecting point 104 for connecting with an external circuit. A logic area 105 is also provided on the bonding surfaces of the SPAD chip 1 and the Vcsel chip 2. Figure 3 Figure 4 Figure 5 Figure 6

[0038]

[0039] ​​​​​​In this solution, the VCSEL chip 2 and SPAD chip 1 of the dToF module adopt a stacked structure. The VCSEL chip 2 is attached to the SPAD chip 1 via flip chip. Both the VCSEL chip 2 and the SPAD chip 1 have several connection pins on their bonding surfaces. The connection pins of the VCSEL chip 2 and the connection pins of the SPAD chip 1 are connected in a corresponding manner through gold-plated balls. This allows the VCSEL chip 2 and the SPAD chip 1 to be connected and combined via a PIN-to-PIN method using flip chip packaging technology, forming an integrated dToF module chip. The VCSEL chip 2 and the SPAD chip 1 do not need to be placed separately or packaged individually, which greatly reduces the structural size of the dToF module product.

[0040] Example 2

[0041] The basic implementation examples are as follows: Figure 1 As shown: A chip stacking method using a chip stacking structure for fabricating a lidar module with the aforementioned chip stacking structure, comprising the following:

[0042] S1. Place the SPAD chip 1 on the substrate; specifically, the SPAD chip 1 is placed horizontally on the substrate, and the connection point 104 of the SPAD chip 1 and the connection point of the substrate are connected by wires.

[0043] S2. Perform gold ball bonding on the connection pins of SPAD chip 1, that is, solder the gold balls to the top surface of the connection pins of SPAD chip 1.

[0044] S3 and VCSEL chip 2 are flip-chip bonded to SPAD chip 1. The connection pins of VCSEL chip 2 on the bonding surface are soldered to the gold ball for conduction. Ultrasonic welding is used for the soldering.

[0045] S4. Apply adhesive to the bottom of SPAD chip 1 to encapsulate and reinforce SPAD chip 1 and Vcsel chip 2.

[0046] S5. Integrate SPAD chip 1 and VCSEL chip 2 into a single DTOF module package.

[0047] The scheme can process an integrated dToF module, wherein the Vcsel chip 2 and the SPAD chip 1 are processed into a stacked structure, the Vcsel chip 2 is flip-chip bonded on the SPAD chip 1, and the Vcsel chip 2 and the SPAD chip 1 are respectively provided with a plurality of connecting pins on the bonding surfaces thereof, the connecting pins of the Vcsel chip 2 and the connecting pins of the SPAD chip 1 are correspondingly welded and connected in the form of gold ball planting, the Vcsel chip 2 and the SPAD chip 1 are connected in the PIN To PIN mode, the SPAD chip 1 and the VCSEL chip 2 are integrally integrated and packaged into a dToF module, forming an integrated dToF module chip, the VCSEL chip 2 and the SPAD chip 1 do not need to be placed separately and packaged separately, which greatly reduces the structure size of the dToF module product.

[0048] The above-mentioned is only an embodiment of the present application, and the common knowledge of specific structures and characteristics in the scheme is not described in detail, the ordinary skilled in the art knows all the ordinary technical knowledge in the field of the present application before the application date or the priority date, can know all the prior art in the field, and has the ability to apply the conventional experimental means before the date, the ordinary skilled in the art can improve and implement the present scheme under the guidance of the present application, some typical known structures or known methods should not be an obstacle for the ordinary skilled in the art to implement the present application. It should be pointed out that for those skilled in the art, without departing from the structure of the present application, a number of modifications and improvements can be made, which should also be considered as the protection scope of the present application, which will not affect the effect and practicality of the present application. The protection scope of the present application should be subject to the content of its claims, and the specific embodiments in the specification can be used to explain the content of the claims.

Claims

1. A laser radar module using a chip stacking structure, comprising: The Vcsel chip and the SPAD chip are characterized in that the Vcsel chip is flip-chip bonded on the SPAD chip, the Vcsel chip and the SPAD chip are respectively provided with a plurality of connecting pins on the bonding surfaces thereof, and the connecting pins of the Vcsel chip are connected with the connecting pins of the SPAD chip in correspondence; The Vcsel chip is provided with a groove on the bonding surface thereof with the SPAD chip, the connecting pins of the Vcsel chip are arranged on the bottom surface of the groove, and the bonding surface outside the groove is also provided with a plurality of connecting pins; The connecting pins of the Vcsel chip are connected with the connecting pins of the SPAD chip in correspondence through gold ball planting; The SPAD chip and the Vcsel chip are provided with a lead-out circuit on the bonding surface thereof, one end of the lead-out circuit is connected with the connecting pins of the SPAD chip, and the other end is provided with a connecting point for connection with an external circuit. 2.The LIDAR module using a chip stack structure according to claim 1, wherein, The Vcsel chip is flip-chip bonded on the SPAD chip. 3.The laser radar module using a chip stacking structure according to claim 1, characterized in that: The SPAD chip and the Vcsel chip are further provided with mark points on the bonding surface thereof for alignment positioning in machine recognition.

4. A chip stacking method for processing a laser radar module using a chip stacking structure according to any one of claims 1 to 3, characterized by, The method comprises the following steps: S1, arranging the SPAD chip above a substrate; S2, planting gold balls on the connecting pins of the SPAD chip; S3, flip-chip bonding the Vcsel chip on the SPAD chip, and welding the connecting pins of the Vcsel chip on the bonding surface in conduction with the gold balls; S4, bottom dispensing on the SPAD chip; S5, integrally integrating the SPAD chip and the Vcsel chip into a dToF module package.

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