Time-to-digital converter based on a multi-channel coarse-fine two-stage

Abstract

The application provides a time-to-digital converter based on two-stage coarse and fine, which comprises a phase-locked loop based multiphase clock generator, a fine time-to-digital converter (TDC), a coarse TDC, three registers and a readout circuit, wherein the multiphase clock generator is used to generate a plurality of internal reference clocks with specific phase difference, the fine TDC is used to improve the measurement precision of the whole TDC, the coarse TDC is used to improve the measurement range of the whole TDC, and the readout circuit is used to calibrate and combine the intermediate quantization values stored in the registers and obtain the final quantization binary code. The TDC of the application can achieve high measurement precision and large measurement range, and compared with the traditional TDC, the TDC of the application can achieve larger measurement precision, and effectively reduce the required power consumption and area under the same manufacturing process.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to a time-to-digital converter based on a multi-channel coarse-fine two-stage method. Background Technology

[0002] Time-to-digital converters (TDCs), as high-precision time measurement modules, are widely used in lidar ranging, flow meters, oscilloscopes, high-energy physics, medical imaging, and all-digital phase-locked loops. In recent years, with continuous exploration of TDCs, more and more novel TDC architectures have been proposed, including vernier delay chain TDCs, pipelined TDCs, successive approximation TDCs, coarse and fine two-stage TDCs, noise-shaping TDCs, and TDCs based on the principle of randomness. Among these, the coarse and fine two-stage TDC has been widely used in lidar ranging because it can simultaneously achieve high measurement accuracy and a large measurement range.

[0003] Figure 1 This paper demonstrates a conventional two-stage coarse-fine TDC based on a delay phase-locked loop (DLL) array. The fine TDC primarily consists of a delay PLL 1 array (DDL1) and a delay PLL 2 array (DLL2), while the coarse TDC comprises two clock counters and a 2-to-1 multiplexer, along with readout circuitry. This conventional two-stage coarse-fine TDC uses a DLL array to implement the quantization function of the fine TDC. Since each DLL channel requires an additional frequency and phase detector, charge pump, and loop filter, this results in both additional area loss and power loss. Furthermore… Figure 1 The existing coarse and fine two-stage TDC shown in the figure uses a voltage-controlled delay unit instead of a traditional delay unit as its basic quantization unit, which greatly reduces its quantization accuracy. This is because the delay time of the voltage-controlled delay unit is much longer than that of its corresponding traditional delay unit.

[0004] As mentioned above, most existing TDCs cannot simultaneously meet the requirements of high measurement accuracy and large measurement range, and therefore cannot meet the needs of high-precision lidar measurement systems. Existing coarse-to-fine two-stage TDCs, which can simultaneously possess high measurement resolution and a large measurement range, use a DLL array to implement the quantization function of the fine TDC. This not only leads to increased power consumption and area loss, but also reduces the theoretically achievable quantization accuracy. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a multi-channel, two-stage coarse-to-fine time-to-digital converter. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] The present invention provides a multi-channel coarse-fine two-stage time-to-digital converter, comprising: a multi-phase clock generator, a fine time-to-digital converter containing n identical sub-TDC channels, a coarse time-to-digital converter, three independent registers, referred to as register 1, register 2 and register 3 respectively, and a readout circuit.

[0007] The multiphase clock generator is used to generate multiple internal clocks with specific phase differences and to use the internal clocks as input excitation for the fine-time digital converter.

[0008] The fine-time digital converter is used to fine-quantize the time difference between the input signals Start and STOP through phase interpolation to obtain n m-bit binary bit streams, and encode the binary bit streams into a p-bit binary symbol. The binary symbol is then input as the fine-quantization result to register 1 or register 2. The converter also generates a counting clock signal and a logic control signal to the coarse-time digital converter.

[0009] Registers 1 and 2 are used to store the fine quantization results according to different external input signal arrival conditions, and register 3 is used to store the count value of the coarse time-to-digital converter.

[0010] The coarse time-to-digital converter is used to record the counting time when the multi-channel coarse-to-fine two-stage time-to-digital converter starts or stops counting the number of cycles of the counting clock signal according to the logic control signal and the input signal Start or STOP during the measurement of the input time difference, to obtain a counting result with a bit width of q, and to use the counting result with a bit width of q as the coarse quantization result, and to input the coarse quantization result into register 3;

[0011] The readout circuit is used to merge the coarse quantization result and the fine quantization result to obtain a quantized binary code with a bit width of k, and then output it.

[0012] Optionally, the multiphase clock generator is composed of a phase-locked loop (PLL), which includes one input terminal and n output terminals. The input terminal is used to input an external input signal EN, and each output terminal outputs an internal clock signal to the fine-time digital converter.

[0013] Optionally, the phase-locked loop (PLL) consists of a ring oscillator, a frequency divider 1, a frequency and phase detector, a charge pump, a loop filter, a voltage-controlled ring oscillator, and a frequency divider 2.

[0014] The input terminal of the ring oscillator serves as the input terminal of the multiphase clock generator, and its output terminal is connected to the input terminal of the frequency divider 1; the frequency divider 1 has one input terminal and one output terminal, and its output terminal is connected to the first input terminal of the frequency and phase detector.

[0015] The frequency and phase detector has two input terminals and two output terminals. Its first input terminal is connected to the output terminal of frequency divider 1, and its second input terminal is connected to the output terminal of frequency divider 2. Its first output terminal outputs a pulse signal UP to the first input terminal of the charge pump, and its second output terminal outputs a pulse signal DN to the second input terminal of the charge pump. The charge pump has two input terminals and one output terminal. Its first input terminal is connected to the first output terminal of the frequency and phase detector, and its second input terminal is connected to the second output terminal of the frequency and phase detector. Its output terminal is connected to the input terminal of the loop filter. The loop filter has one input terminal and one output terminal. Its input terminal is connected to the output terminal of the charge pump, and its output terminal is connected to the input terminal of the voltage-controlled ring oscillator; the voltage-controlled ring oscillator has one input terminal and n+1 output terminals; its input terminal is connected to the output terminal of the loop filter, and its first to nth output terminals output signals Clk1, Clk2, ..., Clkn respectively input to the corresponding input terminals of the fine-time digital converter; its n+1th output terminal is connected to the input terminal of the frequency divider 2; the frequency divider 2 has one input terminal and one output terminal, its input terminal is connected to the n+1th output terminal of the voltage-controlled ring oscillator, and its output terminal is connected to the second input terminal of the frequency and phase detector.

[0016] Optionally, the ring oscillator is used to provide an internal reference clock to the frequency divider 1; the frequency divider 1 is used to divide the internal reference signal generated by the ring oscillator and output the signal ref_clk to the frequency and phase detector.

[0017] The frequency and phase detector is used to detect the phase difference between the internal reference clock and the clock signal output by the frequency divider 2, and outputs a pulse signal of corresponding width at a certain output terminal according to the order of arrival of the two input clock signals.

[0018] The charge pump is used to charge and discharge the capacitors in the loop filter according to the pulse signal of the corresponding width.

[0019] The loop filter is used to filter out the output control voltage V through capacitor charging and discharging. ctrl The high-frequency components in the signal are then output to the input terminal of the voltage-controlled ring oscillator.

[0020] The voltage-controlled ring oscillator is composed of N voltage-controlled delay units connected end to end, used to generate multiple required internal clock signals;

[0021] The frequency divider 2 is used to divide the internal clock signal output from the (n+1)th output terminal of the voltage-controlled ring oscillator and feed the divided clock signal back to the second input terminal of the frequency and phase detector.

[0022] Optionally, the fine-time digital converter includes n identical sub-TDC channels and an encoder module; the first sub-TDC channel has two input terminals and three output terminals, and the second to nth sub-TDC channels have two input terminals and one output terminal. The first input terminal of all sub-TDC channels is connected to the corresponding output terminal of the corresponding multiphase clock generator, and the second input terminal is connected to the sampling signal; the first output terminal of the first sub-TDC channel outputs the logic control signal Q1. <0> The first input terminal of the coarse time-to-digital converter is connected to the first input terminal of the encoder; the output terminals of the second to nth sub-TDC channels are respectively connected to the second to nth input terminals of the encoder; and the output terminal of the encoder is connected to the input terminal of register 1.

[0023] Optionally, each sub-TDC channel consists of a delay chain TDC. The sub-TDC channel quantizes the transmission state of the corresponding input stimulus at the sampling time to determine the transmission state of the corresponding input stimulus in the corresponding delay chain TDC, and outputs an m-bit binary bit stream. The first input terminal of the sub-TDC channel is connected to the corresponding output terminal of the multiphase clock generator, and the second input terminal is connected to the sampling signal Sclk, which is the delayed signal of the external input signals Start and Stop. The output terminal of the sub-TDC channel is connected to the corresponding input terminal of the encoder.

[0024] Optionally, the first sub-TDC channel is used to refine the input Clk1 by using phase interpolation with other sub-TDC channels to obtain n m-bit binary bit streams, and input the binary bit streams into the encoder;

[0025] The encoder is used to encode a binary bit stream into p-bit binary symbols, and input the binary symbols as a fine quantization result into register 1 or register 2.

[0026] Specifically, when the input signal Start arrives, the fine quantization result of the fine-time digitizer is stored in register 1, and when the input signal STOP arrives, the fine quantization result of the fine-time digitizer is stored in register 2.

[0027] Optionally, the coarse-time digital converter includes control logic circuitry and a clock counter;

[0028] The control logic circuit includes three input terminals and two output terminals. The first input terminal receives the logic control signal Q1. <0> The second input terminal receives the external input signal Start, the third input terminal receives the external input signal Stop, the first output terminal outputs the enable signal en to the clock counter, and the second output terminal outputs the clk signal to the register 3. The clock counter includes two input terminals and one output terminal. The first input terminal of the clock counter is connected to the second output terminal of the first sub-TDC channel, and the second input terminal is connected to the first output terminal of the control logic circuit.

[0029] Optionally, the control logic circuit is configured to, based on the logic control signal Q1 <0> The logic level determines whether to immediately generate an enable signal to start the clock counter or delay enabling the clock counter when the measurement begins; and whether to immediately stop the clock counter or delay stopping the clock counter when the measurement ends.

[0030] The clock counter is used to record the number of cycles of the counting clock signal Cclk received during the enable period, generate a counting result with a bit width of q, and use the counting result with a bit width of q as a coarse quantization result, and input the coarse quantization result into register 3.

[0031] The beneficial effects of this invention are:

[0032] The present invention provides a multi-channel coarse-fine two-stage time-to-digital converter, which, compared with other types of TDC, achieves high measurement accuracy while also obtaining a sufficiently large measurement range.

[0033] The present invention provides a multi-channel coarse-fine two-stage time-to-digital converter, which, compared with the existing coarse-fine two-stage TDC, can not only achieve greater measurement accuracy under the same manufacturing process, but also effectively reduce the required power consumption and area.

[0034] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0035] Figure 1 This is an existing coarse-to-fine two-stage time-to-digital converter based on a delay phase-locked loop (DLL) array;

[0036] Figure 2 A schematic diagram of a multi-channel coarse-fine two-stage time-to-digital converter provided by the present invention;

[0037] Figure 3 The circuit structure diagram of the multiphase clock generator provided by the present invention;

[0038] Figure 4The schematic diagram of the sub-TDC channel circuit based on the delay chain structure provided by the present invention;

[0039] Figure 5 The schematic diagram of the first sub-TDC channel circuit provided by the present invention;

[0040] Figure 6 This is a rough TDC structure block diagram provided by the present invention;

[0041] Figure 7 This is an example of a 4-channel coarse-fine two-stage TDC provided by the present invention;

[0042] Figure 8 The fine TDC circuit structure based on 4 channels provided in the embodiment of the present invention;

[0043] Figure 9 This is a schematic diagram illustrating the working principle of fine TDC for fine quantization in an embodiment provided by the present invention.

[0044] Figure 10 The working principle of the encoder in the embodiment provided by the present invention;

[0045] Figure 11 This is a schematic diagram of the input time measurement in an embodiment of the present invention. Detailed Implementation

[0046] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0047] like Figure 2 As shown, the present invention provides a time-to-digital converter based on a multi-channel coarse-fine two-stage method, comprising:

[0048] A multiphase clock generator, comprising n identical sub-TDC channels, fine-time digital converters, coarse-time digital converters, three independent registers, referred to as register 1, register 2 and register 3, and a readout circuit;

[0049] The multiphase clock generator is used to generate multiple internal clocks with specific phase differences and to use the internal clocks as input excitation for the fine-time digital converter.

[0050] The multiphase clock generator is composed of a phase-locked loop (PLL), which includes one input terminal and n output terminals. The input terminal is used to input an external input signal EN, and each output terminal outputs an internal clock signal to the fine-time digital converter.

[0051] The fine-time digital converter is used to refine the time difference between the input signals Start and STOP through phase interpolation to obtain n m-bit binary bit streams, and encode the binary bit streams into a p-bit binary symbol. The binary symbol is then input as the fine-quantization result to register 1 or register 2. It also generates a counting clock signal and a logic control signal to the coarse-time digital converter.

[0052] Registers 1 and 2 are used to store the fine quantization results according to different external input signal arrival conditions, and register 3 is used to store the count value of the coarse time-to-digital converter;

[0053] The coarse time-to-digital converter is used to record the measurement period of the input time difference by the multi-channel coarse-to-fine two-stage time-to-digital converter. According to the logic control signal and the input signal Start or the input signal STOP, the counting time of the counting clock signal is controlled to start or stop counting, and a counting result with a bit width of q is obtained. The counting result with a bit width of q is used as the coarse quantization result and the coarse quantization result is input to register 3.

[0054] The readout circuit is used to merge the coarse quantization result and the fine quantization result to obtain a quantized binary code with a bit width of k, and then output it.

[0055] refer to Figure 3 The multiphase clock generator consists of a ring oscillator, a frequency divider 1, a frequency and phase detector, a charge pump, a loop filter, a voltage-controlled ring oscillator, and a frequency divider 2.

[0056] The input terminal of the ring oscillator serves as the input terminal of the multiphase clock generator, and its output terminal is connected to the input terminal of the frequency divider 1; the frequency divider 1 has one input terminal and one output terminal, and its output terminal is connected to the first input terminal of the frequency and phase detector.

[0057] The frequency and phase detector has two input terminals and two output terminals. Its first input terminal is connected to the output terminal of frequency divider 1, and its second input terminal is connected to the output terminal of frequency divider 2. Its first output terminal outputs a pulse signal UP to the first input terminal of the charge pump, and its second output terminal outputs a pulse signal DN to the second input terminal of the charge pump. The charge pump has two input terminals and one output terminal. Its first input terminal is connected to the first output terminal of the frequency and phase detector, and its second input terminal is connected to the second output terminal of the frequency and phase detector. Its output terminal is connected to the input terminal of the loop filter. The loop filter has one input terminal and one output terminal. Its input terminal is connected to the output terminal of the charge pump, and its output terminal is connected to the input terminal of the voltage-controlled ring oscillator; the voltage-controlled ring oscillator has one input terminal and n+1 output terminals; its input terminal is connected to the output terminal of the loop filter, and its first to nth output terminals output signals Clk1, Clk2, ..., Clkn respectively input to the corresponding input terminals of the fine-time digital converter; its n+1th output terminal is connected to the input terminal of the frequency divider 2; the frequency divider 2 has one input terminal and one output terminal, its input terminal is connected to the n+1th output terminal of the voltage-controlled ring oscillator, and its output terminal is connected to the second input terminal of the frequency and phase detector.

[0058] The ring oscillator is used to provide an internal reference clock to the frequency divider 1; the frequency divider 1 is used to divide the internal reference signal generated by the ring oscillator and output the signal ref_clk to the frequency and phase detector.

[0059] The frequency and phase detector is used to detect the phase difference between the internal reference clock and the clock signal output by the frequency divider 2, and outputs a pulse signal of corresponding width at a certain output terminal according to the order of arrival of the two input clock signals.

[0060] refer to Figure 3 The phase and frequency discriminator detects the phase difference between two input clock signals and outputs a pulse signal of corresponding width at a certain output terminal to control the charging or discharging of the charge pump, based on the order in which the two input clock signals arrive. It has two input terminals and two output terminals. Its first input terminal is connected to the output terminal of frequency divider 1, and its second input terminal is connected to the output terminal of frequency divider 2. Its first output terminal output signal UP is connected to the first input terminal of the charge pump, and its second output terminal output signal DN is connected to the second input terminal of the charge pump.

[0061] The charge pump is used to charge and discharge the capacitors in the loop filter according to the pulse signal of the corresponding width.

[0062] The loop filter is used to filter out the output control voltage V through capacitor charging and discharging. ctrl The high-frequency components in the signal are then output to the input terminal of the voltage-controlled ring oscillator.

[0063] The voltage-controlled ring oscillator is composed of N voltage-controlled delay units connected end to end, used to generate multiple required internal clock signals;

[0064] The frequency divider 2 is used to divide the internal clock signal output from the (n+1)th output terminal of the voltage-controlled ring oscillator and feed the divided clock signal back to the second input terminal of the frequency and phase detector.

[0065] refer to Figure 3 The fine-time digital converter includes n identical sub-TDC channels and an encoder module; the first sub-TDC channel has two input terminals and three output terminals, and the second to nth sub-TDC channels have two input terminals and one output terminal. The first input terminal of each sub-TDC channel is connected to the corresponding output terminal of the corresponding multiphase clock generator, and the second input terminal is connected to the sampling signal; the first output terminal of the first sub-TDC channel outputs the logic control signal Q1. <0> The first input terminal of the coarse time-to-digital converter is connected to the first input terminal of the encoder; the output terminals of the second to nth sub-TDC channels are respectively connected to the second to nth input terminals of the encoder; and the output terminal of the encoder is connected to the input terminal of register 1.

[0066] refer to Figure 4 Each sub-TDC channel consists of a delay chain TDC. The sub-TDC channel quantizes the transmission state of the corresponding input stimulus at the sampling time to determine the transmission state of the corresponding input stimulus in the corresponding delay chain TDC, and outputs an m-bit binary bit stream. The first input terminal of the sub-TDC channel is connected to the corresponding output terminal of the multiphase clock generator, and the second input terminal is connected to the sampling signal Sclk, which is the delayed signal of the external input signals Start and Stop. The output terminal of the sub-TDC channel is connected to the corresponding input terminal of the encoder.

[0067] like Figure 5 As shown, the first sub-TDC channel has two input terminals and three output terminals. Its first input terminal is connected to the first output terminal of the multiphase clock generator, and its second input terminal is connected to the sampling signal Sclk, which is the delayed signal of the external input signals Start and Stop. Its first output terminal outputs signal Q1. <0> The first input terminal of the coarse TDC is connected to the second input terminal, and the second output terminal output signal Cclk is connected to the second input terminal of the coarse TDC. Its third output terminal is connected to the first input terminal of the encoder.

[0068] The first sub-TDC channel is used to refine the input Clk1 by using phase interpolation with other sub-TDC channels to obtain n m-bit binary bit streams, and input the binary bit streams into the encoder;

[0069] The encoder is used to encode a binary bit stream into p-bit binary symbols, and input the binary symbols as a fine quantization result into register 1 or register 2.

[0070] Specifically, when the input signal Start arrives, the fine quantization result of the fine-time digitizer is stored in register 1, and when the input signal STOP arrives, the fine quantization result of the fine-time digitizer is stored in register 2.

[0071] The encoder is used to encode n m-bit binary bitstreams into a p-bit binary symbol, which is then used as the quantization result of the fine TDC. It has n m-bit inputs and one p-bit output. Each input corresponds to the output of a specific sub-TDC channel; its output is connected to the first inputs of registers 1 and 2.

[0072] Register 1 is used to store the quantization result of the fine TDC when the Start signal arrives. It has two input terminals and one output terminal (where the bit width of the first input terminal and the output terminal is p). The first input terminal is connected to the output terminal of the encoder in the fine TDC, the second input terminal is connected to the external input Start signal, and its output terminal is connected to the first input terminal of the readout circuit.

[0073] Register 2 is used to store the quantization result of the fine TDC when the Stop signal arrives. It also has two inputs and one output (where the bit width of the first input and the output is p). Its first input is connected to the output of the encoder in the fine TDC, and its second input is connected to the external input Stop signal; its output is connected to the second input of the readout circuit.

[0074] Register 3 is used to store the count value of the clock counter in the coarse TDC. It also has two input terminals and one output terminal (where the bit width of the second input terminal and the output terminal is q). Its first input terminal is connected to the output signal clk of the first output terminal of the coarse TDC, and its second input terminal is connected to the second output terminal of the coarse TDC; its output terminal is connected to the third input terminal of the readout circuit.

[0075] like Figure 6 As shown, the coarse-time digital converter includes control logic circuitry and a clock counter;

[0076] The control logic circuit includes three input terminals and two output terminals. The first input terminal receives the logic control signal Q1. <0> The second input terminal receives the external input signal Start, the third input terminal receives the external input signal Stop, the first output terminal outputs the enable signal en to the clock counter, and the second output terminal outputs the clk signal to the register 3. The clock counter includes two input terminals and one output terminal. The first input terminal of the clock counter is connected to the second output terminal of the first sub-TDC channel, and the second input terminal is connected to the first output terminal of the control logic circuit.

[0077] The control logic circuit is used to control the logic signal Q1. <0> The logic level determines whether to immediately generate an enable signal to start the clock counter or delay enabling the clock counter when the measurement begins; and whether to immediately stop the clock counter or delay stopping the clock counter when the measurement ends.

[0078] refer to Figure 6 The control logic circuit is used to start and stop the clock counter. It has three inputs and two outputs. Its first input is connected to the first output of the first sub-TDC channel, its second input is connected to the external input Start signal, and its third input is connected to the external input Stop signal. Its first output signal en is connected to the second input of the clock counter, and its second output signal clk is connected to the first input of register 3.

[0079] The clock counter is used to record the number of cycles of the counting clock signal Cclk received during the enable period, generate a counting result with a bit width of q, and use the counting result with a bit width of q as a coarse quantization result, and input the coarse quantization result into register 3.

[0080] The first input terminal of the clock counter is connected to the second output terminal of the first sub-TDC channel, and its second input terminal is connected to the second output terminal of the control logic circuit; its output terminal is connected to the second input terminal of register 3.

[0081] The readout circuit is used to merge the quantization results of the fine TDC and coarse TDC to obtain the final quantized binary code. It has three input terminals with a bit width of p and one output terminal with a bit width of k. Its first input terminal is connected to the output terminal of register 1, its second input terminal is connected to the output terminal of register 2, and its third input terminal is connected to the output terminal of register 3; its output terminal is connected to an external output.

[0082] The following is a specific implementation example of the present invention.

[0083] refer to Figures 7-11 , Figure 7This is a 4-channel coarse-fine two-stage TDC in an embodiment of the present invention; Figure 8 This is a 4-channel fine TDC circuit structure in the embodiment of the present invention; Figure 9 This is a schematic diagram illustrating the working principle of fine TDC for fine quantization in the embodiments described in this invention. Figure 10 This describes the working principle of the encoder in an embodiment of the present invention. Figure 11 This is a schematic diagram of the input time measurement in an embodiment of the present invention.

[0084] Figure 7 The diagram shown is a specific implementation example circuit structure of a multi-channel coarse-fine two-stage time-to-digital converter provided by the present invention. It mainly consists of a multi-phase clock generator, a fine TDC based on four delay chain sub-TDC modules, and an encoder (such as...). Figure 8 As shown in the figure, it consists of a coarse TDC based on control logic circuits and a clock counter, three registers, and a readout circuit.

[0085] Figure 8 In the fine TDC shown, each delay chain has a length of 42, and its output is an 8-bit binary code. This fine TDC achieves fine quantization of the input time by utilizing phase interpolation between channels. Its working principle is as follows: Figure 9 As shown. By uniformly interpolating the phase between each channel, the quantization accuracy of this fine TDC can be improved from τ0 of a single delay chain TDC to τ0 / 4.

[0086] First, set the appropriate parameters appropriately, so that... Figure 7 The multiphase clock generator outputs four internal clock signals, "Clk1", "Clk2", "Clk3", and "Clk4", with a single-phase delay of 1.250°. These signals are connected as excitation signals to the inputs of the corresponding delay chains in the fine TDC, such as... Figure 8 As shown.

[0087] To achieve the above requirements, this implementation example provides the following specific parameter setting: 1. Figure 3 The multiphase clock generator shown contains 55 inverter-based delay units in both its ring oscillator and voltage-controlled ring oscillator. The difference is that the delay units in the voltage-controlled ring oscillator are controlled. 2. The delay units used in the ring oscillator of the multiphase clock generator are the same as the basic delay units used in the delay chains of the fine TDC. 3. The division coefficients of divider 1 and divider 2 in the multiphase clock generator are 20 and 16, respectively. 4. Each delay chain in the fine TDC consists of 42 buffers. This allows for a phase delay of 1.250° between clock signals “Clk1”, “Clk2”, “Clk3”, and “Clk4”.

[0088] After setting the above parameters, the TDC can start working normally. When the external input enable signal "EN" is high, the multiphase clock generator starts working and generates four internal clocks: "Clk1", "Clk2", "Clk3", and "Clk4". These four internal clocks are connected as excitation signals to the input terminals of the four delay chains in the fine TDC.

[0089] When the external input signal Start arrives, its corresponding sampling signal Sclk begins sampling the phase of each delay chain in the fine TDC, obtaining four 42-bit binary bit streams. These four binary bit streams are then sent to the encoder for corresponding encoding, with the encoding rules as follows: Figure 10 As shown, after encoding, an 8-bit fine-tuned binary code is obtained and stored in register 1.

[0090] At the same time, the control logic circuit in the coarse TDC will adjust according to the input signal "Q1". <0> The logic level of "" determines whether to immediately enable the clock counter to start counting or delay enabling the clock counter. In this invention, when Q1 <0> When the level is low, the clock counter will be enabled with a delay. Once the clock counter is enabled, it begins counting the number of cycles of the received clock signal Cclk. In this embodiment, a 4-bit clock counter is provided.

[0091] When the external input signal Stop arrives, it also triggers the sampling signal Sclk to start sampling the phases of each delay chain in the fine TDC, obtaining four 42-bit binary bit streams. These four binary bit streams are then sent to the encoder for corresponding encoding, with the encoding rules as follows: Figure 10 As shown. After encoding, an 8-bit fine-tuned binary code is obtained and stored in register 2.

[0092] At the same time, the control logic circuit in the coarse TDC will also be based on the input signal Q1 <0> The logic level determines whether to immediately stop the clock counter or delay stopping it. In this invention, when Q1... <0> When the level is low, the clock counter will be delayed until it stops counting. Finally, when the clock counter stops counting, its count result will be stored in register 3.

[0093] Finally, the data in registers 1, 2, and 3 will be calibrated and merged by the readout circuit into a final 11-bit quantized binary code, which is the final quantization result.

[0094] The above measurement process can be performed by Figure 11The measurement diagram shown illustrates this. Here, t0 represents the clock period of the clock signal Cclk; t1 and t3 are the measurement times of the fine TDC at the start and end points, respectively; t5 is the measurement time of the coarse TDC; and T is the time difference between the input signals Start and Stop, i.e., the input measurement time. Figure 11 We can obtain the following formula:

[0095] T = t5 + t3 - t1

[0096] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0097] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0098] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A time-to-digital converter based on a multi-channel coarse-fine two-stage, characterized by, The application relates to a multi-phase clock generator, which comprises a fine time-to-digital converter (TDC) with n identical sub-TDC channels, a coarse TDC, three independent registers, namely register 1, register 2 and register 3, and a readout circuit. The multi-phase clock generator is used for generating a plurality of internal clocks with specific phase differences and taking the internal clocks as input excitation of the fine TDC. The fine TDC is used for fine quantization of a time difference between input signals Start and STOP through phase interpolation, obtaining n m-bit binary bit streams, encoding the binary bit streams into a p-bit binary symbol, taking the binary symbol as a fine quantization result and inputting the fine quantization result into register 1 or register 2, and generating a counting clock signal and a logic control signal to the coarse TDC. Register 1 and register 2 are used for storing the fine quantization result according to different arrival conditions of external input signals, and register 3 is used for storing a counting value of the coarse TDC. The coarse TDC is used for recording a counting time of the counting clock signal during measurement of the input time difference by the multi-channel coarse-fine two-stage TDC, starting or stopping counting according to the logic control signal and the input signal Start or the input signal STOP, obtaining a q-bit counting result and taking the q-bit counting result as a coarse quantization result, and inputting the coarse quantization result into register 3. The readout circuit is used for merging the coarse quantization result and the fine quantization result to obtain a k-bit quantization binary code and outputting the k-bit quantization binary code. The multi-phase clock generator is composed of a phase-locked loop (PLL), which comprises an input end and n output ends, the input end is used for inputting an external input signal EN, and each output end outputs an internal clock signal to the fine TDC.

2. The time-to-digital converter of claim 1, wherein, The phase-locked loop (PLL) is composed of a ring oscillator, a frequency divider 1, a frequency discriminator, a charge pump, a loop filter, a voltage-controlled ring oscillator and a frequency divider 2.

3. The time-to-digital converter of claim 2, wherein, An input end of the ring oscillator is used as an input end of the multi-phase clock generator, and an output end of the ring oscillator is connected to an input end of the frequency divider 1; the frequency divider 1 has an input end and an output end, and the output end of the frequency divider 1 is connected to a first input end of the frequency discriminator. ​ The phase frequency detector has two input ends and two output ends, the first input end is connected to the output end of the frequency divider 1, the second input end is connected to the output end of the frequency divider 2; the first output end outputs a pulse signal UP to the first input end of the charge pump, and the second output end outputs a pulse signal DN to the second input end of the charge pump; the charge pump has two input ends and one output end; the first input end is connected to the first output end of the phase frequency detector, and the second input end is connected to the second output end of the phase frequency detector; the output end is connected to the input end of the loop filter; the loop filter has one input end and one output end; the input end is connected to the output end of the charge pump, and the output end is connected to the input end of the voltage-controlled ring oscillator; the voltage-controlled ring oscillator has one input end and n+1 output ends; the input end is connected to the output end of the loop filter, and the 1st to n output ends output signals Clk1, Clk2, …, Clkn, which are respectively input to the corresponding input ends of the fine time-to-digital converter; the n+1 output end is connected to the input end of the frequency divider 2; the frequency divider 2 has one input end and one output end, the input end is connected to the n+1 output end of the voltage-controlled ring oscillator, and the output end is connected to the second input end of the phase frequency detector.

4. The multi-channel coarse-fine two-stage time-to-digital converter according to claim 3, wherein the ring oscillator is configured to provide an internal reference clock to the frequency divider 1; the frequency divider 1 is configured to divide the internal reference signal generated by the ring oscillator and output a signal ref_clk to the phase frequency detector; the phase frequency detector is configured to detect the phase difference between the internal reference clock and the clock signal output by the frequency divider 2, and output a pulse signal with a corresponding width at a certain output end according to the order of arrival of the two input clock signals; the charge pump is configured to charge and discharge the capacitor in the loop filter according to the pulse signal with a corresponding width; the voltage-controlled ring oscillator is composed of N voltage-controlled delay units connected in a loop, and is configured to generate a plurality of required internal clock signals; and the frequency divider 2 is configured to divide the internal clock signal output by the n+1 output end of the voltage-controlled ring oscillator and feed back the divided clock signal to the second input end of the phase frequency detector. ​ ​ ​ The loop filter is used to filter out high frequency components in the output control voltage V ctrl through capacitive charging and discharging, and then output to the input end of the voltage-controlled ring oscillator. ​ ​ 5. The time-to-digital converter of claim 3, wherein, The fine time-to-digital converter comprises n identical sub-TDC channels and an encoder module; the first sub-TDC channel has two input ends and three output ends, the second to n sub-TDC channels have two input ends and one output end, the first input end of all the sub-TDC channels is respectively connected to the corresponding output end of the corresponding multi-phase clock generator, and the second input end is connected to a sampling signal; the first output end of the first sub-TDC channel outputs a logic control signal Q1<0> to the first input end of the coarse time-to-digital converter, the second output end outputs a counting clock signal Cclk to the second input end of the coarse time-to-digital converter, and the third output end of the first sub-TDC channel is connected to the first input end of the encoder; the output end of the second to n sub-TDC channels is respectively connected to the second to n input ends of the encoder, and the output end of the encoder is connected to the input end of the register 1.

6. The time-to-digital converter of claim 5, wherein, Each sub-TDC channel is composed of a delay chain type TDC, and the sub-TDC channel quantizes the transmission state of the corresponding input excitation at the sampling moment to determine the transmission state of the corresponding input excitation in the corresponding delay chain type TDC and outputs an m-bit binary bit stream; the first input end of the sub-TDC channel is connected to the corresponding output end of the multi-phase clock generator, and the second input end is connected to a sampling signal Sclk, which is a signal obtained by delaying the external input signals Start and Stop; the output end of the sub-TDC channel is connected to the corresponding input end of the encoder.

7. The multi-channel coarse-fine two-stage time-to-digital converter of claim 6, wherein, The first sub-TDC channel is used for fine quantization of the input Clk1 by phase interpolation between the first sub-TDC channel and other sub-TDC channels, and n m-bit binary bit streams are obtained, which are input into the encoder. The encoder is used for encoding the binary bit stream into a p-bit binary symbol, and inputting the binary symbol as a fine quantization result into the register 1 or the register 2. Wherein, when the input signal Start comes, the fine quantization result of the fine time-to-digital converter is stored into the register 1, and when the input signal Stop comes, the fine quantization result of the fine time-to-digital converter is stored into the register 2.

8. The time-to-digital converter of claim 5, wherein, The coarse time-to-digital converter comprises a control logic circuit and a clock counter; The control logic circuit comprises three input ends and two output ends, the first input end inputs a logic control signal Q1<0>, the second input end inputs an external input signal Start, the third input end inputs an external input signal Stop, the first output end outputs an enable signal en to the clock counter, and the second output end outputs a clk signal stored into a register 3; the clock counter comprises two input ends and one output end, the first input end of the clock counter is connected to the second output end of the first sub-TDC channel, and the second input end is connected to the first output end of the control logic circuit.

9. The time-to-digital converter based on a multi-channel coarse-fine two-stage according to claim 8, characterized in that, The control logic circuit is used for judging whether to immediately generate an enable signal to control the clock counter to start counting or to delay the enable clock counter according to the logic level of the logic control signal Q1<0> when starting the measurement, and judging whether to immediately stop the clock counter counting or to delay the stop of the clock counter counting according to the logic level of the logic control signal Q1<0> when ending the measurement. The clock counter is used for recording the number of periods of the counting clock signal Cclk received during the enable period, generating a counting result with a bit width of q, taking the counting result with the bit width of q as a coarse quantization result, and inputting the coarse quantization result into the register 3.

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