Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure comprises: providing a substrate, the substrate comprising a plurality of discrete active regions and isolation structures between adjacent active regions, the substrate comprising word line regions extending along a first direction; forming buffer blocks and a filling layer, wherein the buffer blocks are located on the part of the isolation structures between the adjacent active regions of the word line regions, and the buffer blocks are spaced apart from the adjacent active regions, and the filling layer is located on the substrate and fills the region between the adjacent buffer blocks; using a dry etching process to etch the filling layer, the buffer blocks, the isolation structures and the active regions of the word line regions to form word line grooves, wherein the surface of the isolation structure opposite to the filling layer in the word line region is exposed to the environment of the dry etching process earlier than the surface of the isolation structure opposite to the buffer layer; and forming a word line structure filling the word line grooves. At least the control ability of the word line to the channel in the active region can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] As semiconductor device density increases, the feature size of dynamic random access memory (DRAM) is shrinking. For DRAM fabrication processes of 50nm and below, buried wordlines are widely used to reduce the gate area occupied by transistors. This significantly reduces the active area occupied by wordlines (by 40% to 60% compared to non-buried wordlines).

[0003] However, there are still some problems in the current method of manufacturing a semiconductor structure with a buried word line. Summary of the Invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial for improving the control capability of word lines over channels in active regions.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate comprising a plurality of discrete active areas and an isolation structure located between adjacent active areas, the substrate comprising a word line area extending along a first direction; forming a buffer block and a filling layer, wherein the buffer block is located on a portion of the isolation structure between adjacent active areas of the word line area, and the buffer block is spaced apart from the adjacent active areas, and the filling layer is located on the substrate and fills the area between adjacent buffer blocks; using a dry etching process to etch the filling layer, the buffer block, the isolation structure and the active area in the word line area to form a word line groove, wherein, in the word line area, the surface of the isolation structure facing the filling layer is exposed to the environment of the dry etching process before the surface of the isolation structure facing the buffer layer; forming a word line structure filling the word line groove.

[0006] According to some other embodiments of the present disclosure, the etching rate of the buffer block in the dry etching process is lower than the etching rate of the filling layer.

[0007] According to some other embodiments of the present disclosure, the method of forming the buffer block and the filling layer includes: first forming the buffer block, and then forming the filling layer.

[0008] According to some other embodiments of the present disclosure, the step of forming the filling layer includes: forming a filling film on the substrate, the filling film filling the area between adjacent buffer blocks and also covering the top surface of the buffer block; flattening the filling film, and the remaining filling film serves as the filling layer.

[0009] According to some other embodiments of the present disclosure, the stop position of the planarization process is higher than the top surface of the buffer block, and the formed filling layer also covers the top surface of the buffer block.

[0010] According to some other embodiments of the present disclosure, the stop position of the planarization process is the top surface of the buffer block, and the top surface of the formed filling layer is flush with the top surface of the buffer block.

[0011] According to some other embodiments of the present disclosure, the process steps for forming the buffer block include: forming a buffer layer on the substrate to cover the entire surface of the substrate; and patterning the buffer layer to form the buffer block.

[0012] According to other embodiments of the present disclosure, the method of forming the buffer block and the filling layer includes: first forming the filling layer, wherein the filling layer has an opening extending from the top surface to the bottom surface; and forming the buffer block to fill the opening.

[0013] According to some other embodiments of the present disclosure, a ratio of the depth of the opening to the thickness of the filling layer is in the range of 0.5-1.

[0014] According to some other embodiments of the present disclosure, the process steps for forming the buffer block include: forming a buffer layer, which fills the opening and is also located on the top surface of the filling layer; removing the buffer layer above the top surface of the filling layer, and the remaining buffer layer serves as the buffer block.

[0015] According to some other embodiments of the present disclosure, the method of forming the buffer block also includes: forming a first buffer block, the first buffer block is located on a portion of the first isolation structure, the first isolation structure is located between a pair of active areas adjacent to each other in the first direction; forming a second buffer block, the second buffer block is located on a portion of the second isolation structure, the second isolation structure is located between another pair of active areas adjacent to each other in the first direction, and along the first direction, the width of the second isolation structure is greater than the width of the first isolation structure.

[0016] According to some other embodiments of the present disclosure, along the first direction, the total width of the second buffer block is greater than or equal to the total width of the first buffer block; wherein, the total width of the second buffer block is greater than 0; the total width of the first buffer block is greater than or equal to 0.

[0017] According to some other embodiments of the present disclosure, on the same second isolation structure, the second buffer block includes at least two separate sub-buffer blocks.

[0018] According to some other embodiments of the present disclosure, the first buffer block is located in a central area of ​​the first isolation structure; and / or the second buffer block is located in a central area of ​​the second isolation structure.

[0019] According to some other embodiments of the present disclosure, the buffer block spans the word line region along a second direction and is also located in a region adjacent to the word line region in the second direction, wherein the second direction is parallel to the substrate surface and perpendicular to the first direction.

[0020] According to some other embodiments of the present disclosure, the buffer block spans across at least two of the word line regions.

[0021] According to some other embodiments of the present disclosure, in a direction perpendicular to the surface of the substrate, the thickness of the buffer block is 2 nm to 4 nm.

[0022] According to some other embodiments of the present disclosure, the material of the buffer block includes nitride or oxynitride; the material of the filling layer includes oxide; and the material of the isolation structure includes oxide.

[0023] According to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure further provide a semiconductor structure, comprising: a substrate, the substrate comprising a plurality of discrete active regions and an isolation structure located between adjacent active regions, the substrate comprising a word line region extending along a first direction; a word line structure, the word line structure being located within the word line region, the word line structure spanning the active regions and the isolation structure, wherein, in the first direction, the word line structure within the isolation structure located between adjacent active regions has at least two recesses.

[0024] According to other embodiments of the present disclosure, the word line structure includes: a first word line portion, the first word line portion is located in a first isolation structure, the first isolation structure is located between a pair of adjacent active regions, and the first word line portion has at least two recessed portions; a second word line portion, the second word line portion is located in a second isolation structure, the second isolation structure is located between another pair of adjacent active regions, the second word line portion has at least two recessed portions, and along the first direction, the width of the second isolation structure is greater than the width of the first isolation structure.

[0025] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0026] The method for forming a semiconductor structure provided by an embodiment of the present disclosure first provides a substrate, the substrate including a plurality of discrete active areas and an isolation structure located between adjacent active areas, the substrate including a word line area extending along a first direction; then a buffer block and a filling layer are formed, the buffer block is located on a portion of the isolation structure between adjacent active areas of the word line area, and the buffer block is spaced apart from the adjacent active areas, the filling layer is located on the substrate, and fills the area between adjacent buffer blocks; a dry etching process is used to etch the filling layer, the buffer block, the isolation structure and the active area of ​​the word line area to form a word line groove, wherein, in the word line area, the surface of the isolation structure facing the filling layer is exposed to the dry etching process environment before the surface of the isolation structure facing the buffer layer; finally, a word line structure filling the word line groove is formed. In related art, when etching an isolation layer to form a buried wordline, due to the characteristics of the etching process, the depth of the wordline structure directly opposite the center region of the isolation layer is greater than the depth of the wordline structure directly opposite the edge region of the isolation layer. The wordline structure located within the isolation structure presents a U-shaped structure, and the side walls of the U-shaped wordline structure are farther away from the active region, which results in a lower ability of the wordline to control the channel of the active region. In the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure, since a buffer block is formed on the surface of the isolation structure, when etching to form a wordline groove, the buffer block causes different regions of the isolation structure surface to come into contact with the etching environment at different times, and the surface of the region directly opposite the buffer block at the center of the isolation structure comes into contact with the etching environment later. The buffer block can delay the etching of the central area of ​​the isolation structure by the etching environment, so that the etching progress of the central area of ​​the isolation structure and the etching progress of the edge of the isolation structure are balanced to a certain extent. The area of ​​the isolation structure etched by the etching process will extend to both sides, so that the two side walls of the word line structure finally etched are closer to the active area, which can effectively improve the control ability of the word line over the channel in the active area. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figures 1 to 18 A schematic structural diagram of each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0029] Figure 19A schematic cross-sectional view of a semiconductor structure provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] As known from the background art, the semiconductor structure manufactured by the current semiconductor structure manufacturing method has the problem of poor channel control capability of the word line over the active region.

[0031] The disclosed embodiment provides a method for manufacturing a semiconductor structure. First, a substrate is provided. The substrate includes a plurality of discrete active areas and an isolation structure located between the active areas. The substrate includes a word line area extending along a first direction. A buffer block and a filling layer are formed. The buffer block is located on a portion of the isolation structure between adjacent active areas in the word line area, and the buffer block is spaced apart from the adjacent active areas. The filling layer is located on the substrate and fills the area between adjacent buffer blocks. A dry etching process is then used to etch word line grooves, the filling layer, buffer block, isolation structure, and active area of ​​the word line area. In the word line area, the surface of the isolation structure facing the isolation layer is exposed to the dry etching process before the surface of the isolation structure facing the buffer layer. Finally, a word line structure filling the word line groove is formed. In this way, the word line's ability to control the channel of the active area can be improved.

[0032] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0033] Figures 1 to 18 A schematic structural diagram of each step of the method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure. Figure 1 A schematic cross-sectional view of a step in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figure 2 for Figure 1 Schematic diagram of the top view of the structure, Figure 1 The cross-sectional direction is the X direction.

[0034] refer to Figures 1 to 2 A substrate 100 is provided. The substrate 100 includes a plurality of discrete active regions 110 and an isolation structure 120 located between adjacent active regions 110. The substrate 100 includes a word line region 130 extending along a first direction X.

[0035] A plurality of discrete active regions 110 are arranged in an array on a substrate 100, and isolation structures 120 surround the active regions 110, with an isolation structure 120 located between every two adjacent active regions 110. Along a first direction X, the widths of the isolation structures 120 between every two adjacent active regions 110 are inconsistent, with some isolation structures 120 between adjacent active regions 110 being narrower and others being wider. The active regions 110 may be made of silicon and used to form transistors in a semiconductor structure in subsequent steps. The isolation structures 120 may also be made of silicon oxide and used to isolate different active regions 110.

[0036] The word line region 130 is used to form a word line structure in subsequent steps. The word line structure contacts the plurality of active regions 110 and constitutes a part of the ultimately formed semiconductor structure.

[0037] refer to Figures 3 to 15 , forming a buffer block 140 and a filling layer 150, wherein the buffer block 140 is located on a portion of the isolation structure 120 between adjacent active areas 110 of the word line area 130, and the buffer block 140 is spaced apart from the adjacent active areas 110, and the filling layer 150 is located on the substrate 100 and fills the area between adjacent buffer blocks 140.

[0038] The buffer block 140 can ensure that different areas of the surface of the isolation structure 120 where the word line grooves are to be formed are exposed to the etching environment for different times when the semiconductor structure is subsequently subjected to the process step of etching the word line grooves. This can change the morphology of the etched word line grooves, which is beneficial for widening the width of the word line grooves in the isolation structure 120, reducing the distance between the word line grooves and the active areas 110 on both sides of the isolation structure 120, and improving the control ability of the word line over the channel of the active area 110.

[0039] refer to Figure 3 Before forming the buffer block 140 and the filling layer 150, the surface of the substrate 100 may be thinned. The surface to be thinned is the side of the substrate 100 where the wordline structure is to be formed. This thinning process exposes the surface of each active area 110 and the surface of the isolation structure 120 on the surface of the substrate 100, facilitating the formation of the buffer block 140 and the filling layer 150 in subsequent steps. The process for thinning the surface of the substrate 100 may be chemical mechanical polishing (CMP).

[0040] There are multiple methods for forming the buffer block 140 and the filling layer 150 , and the sizes and positions of the buffer block 140 and the filling layer 150 can also be multiple, which will be described in detail below.

[0041] refer to Figures 4 to 8 In some embodiments, the method of forming the buffer block 140 and the filling layer 150 may include: first forming the buffer block 140 and then forming the filling layer 150. The following description will take the example of first forming the buffer block 140 and then forming the filling layer 150.

[0042] refer to Figures 4 and 5 In some embodiments, the process steps of forming the buffer block 140 may include: forming a buffer layer 141 on the substrate 100 to cover the entire surface of the substrate 100; and then patterning the buffer layer 141 to form the buffer block 140.

[0043] Specifically, refer to Figure 4 The buffer layer 141 can cover the surfaces of all active areas 110 and the isolation structure 120 on the substrate 100. The process step of forming the buffer layer 141 can be a deposition process. This method of forming the buffer layer 141 first can reduce the difficulty of manufacturing the buffer block 140.

[0044] refer to Figure 5 , for the buffer layer 141 (reference Figure 4 ) is patterned to form buffer block 140. The patterning process may be an etching process. The patterned buffer layer 141 is located on the surface of isolation structure 120 and can adjust the contact time between the etching environment and various regions of isolation structure 120 during subsequent wordline groove etching, thereby increasing the width of the etched wordline groove.

[0045] refer to Figures 6 to 8 In some embodiments, the step of forming the filling layer 150 may include: forming a filling film 151 on the substrate 100, the filling film 151 filling the area between adjacent buffer blocks 140 and also covering the top surface of the buffer block 140; flattening the filling film 151, and the remaining filling film 151 serves as the filling layer 150.

[0046] Specifically, refer to Figure 6First, a filling film 151 is formed on the substrate 100. The height of the filling film 151 is greater than the height of the buffer block 140 formed in the aforementioned step, that is, the filling film 151 completely covers the buffer block 140. The process method for forming the filling film 151 may include a deposition method. Since the portion of the filling film 151 that exceeds the height of the buffer block 140 has the same etching rate in the same etching environment, in the subsequent step of etching the word line groove, the etching starting position is the upper surface of the semiconductor structure away from the substrate 100, and the portion of the filling film 151 that exceeds the height of the buffer block 140 has no obvious beneficial effect on the subsequently formed word line groove. Therefore, the filling film 151 can be thinned, that is, the filling film 151 can be flattened to reduce the time used for etching in the subsequent etching process. The process method for the flattening treatment can be a chemical mechanical polishing process.

[0047] refer to Figure 7 , Figure 7 Figure 1 is a schematic diagram of a structure after a filler film 151 is planarized to form a filler layer 150. In some embodiments, the planarization process can be stopped at a position higher than the top surface of the buffer block 140, and the formed filler layer 150 can also cover the top surface of the buffer block 140. This ensures that the planarization process does not change the size of the buffer block 140. This not only preserves the integrity of the buffer block 140 and does not weaken its buffering effect on the etching of the wordline grooves in subsequent process steps, but also minimizes the size of the filler layer 150 and reduces the processing time of the subsequent etching process.

[0048] refer to Figure 8 , Figure 8 This is a schematic diagram of the structure after planarizing another filler film 151 to form a filler layer 150. In some embodiments, the planarization process can stop at the top surface of the buffer block 140, so that the top surface of the filler layer 150 is flush with the top surface of the buffer block 140. This minimizes unnecessary etching process waste, reduces etching process time, energy consumption, and process materials, and effectively improves the manufacturing efficiency of the semiconductor structure.

[0049] The above is a method for forming the buffer block 140 and the filling layer 150 , in which the buffer block 140 is formed first and then the filling layer 150 is formed.

[0050] refer to Figures 9 to 11 In some embodiments, the buffer block 140 and the filling layer 150 can be formed by first forming the filling layer 150 and then forming the buffer block 140. The filling layer 150 can be formed first, with an opening extending from the top surface to the bottom surface; and then the buffer block 140 is formed to fill the opening. The following description uses the example of forming the filling layer 150 first and then forming the buffer block 140.

[0051] refer to Figure 9 First, a filling layer 150 is formed. The filling layer 150 has multiple openings. The openings are used to form buffer blocks 140 in a subsequent step. The positions of the openings are the positions where the buffer blocks 140 are to be formed. The width of the openings along the first direction X is the width of the buffer blocks 140 to be formed. The height of the openings can be equal to the height of the buffer blocks 140 to be formed. The process steps for forming the filling layer 150 may include: first, forming a full layer of filling film on the surface of the substrate 100, the filling film covering all active areas 110 and isolation structures 120 on the surface of the substrate 100; and then, patterning the full layer of filling film to form the filling layer 150 having openings.

[0052] In some embodiments, the ratio of the depth of the opening to the thickness of the filling layer 150 is in the range of 0.5-1. For example, the ratio of the depth of the opening to the thickness of the filling layer 150 can be 0.5, 0.6, 0.68, 0.72, 0.83, 0.96, 1, etc. It can be understood that the depth of the opening is the height of the buffer block 140 to be formed subsequently. When the ratio of the depth of the opening to the thickness of the filling layer 150 is greater than or equal to 0.5 and less than 1, the opening does not penetrate the filling layer 150; when the ratio of the depth of the opening to the thickness of the filling layer 150 is 1, the opening penetrates the filling layer 150. That is, the buffer block 140 may not penetrate the filling layer 150, or the buffer block 140 may also penetrate the filling layer 150. When buffer block 140 does not penetrate filling layer 150, the ratio of the depth of the opening to the thickness of filling layer 150 must also be greater than or equal to 0.5 and less than 1. That is, the ratio of the height of buffer block 140 to the height of filling layer 150 must also be greater than 0.5 and less than 1, and the thickness of buffer block 140 must still maintain a certain value. In this way, when etching the wordline groove in the subsequent step, buffer block 140 can still provide an excellent buffering effect, effectively adjusting the contact time between the etching environment and various surface areas of isolation structure 120, and adjusting the distance between the sidewalls of the wordline structure and the active areas 110 on both sides.

[0053] refer to Figures 10 and 11 In some embodiments, the process steps for forming the buffer block 140 may include: Figure 10 , forming a buffer layer 141, the buffer layer 141 fills the opening and is also located on the top surface of the filling layer 150; Figure 11 , remove the buffer layer 141 above the top surface of the filling layer 150, and the remaining buffer layer 141 serves as the buffer block 140. In this way, the buffer block 140 can completely fill the opening without any gaps or blanks in the opening, and the buffer block 140 can more effectively exert its buffering effect in subsequent steps.

[0054] In other embodiments, the process step of forming the buffer block 140 may also be to directly form the buffer block 140 to fill the opening, which can make the manufacturing process of the semiconductor structure more concise.

[0055] In other embodiments, the process steps for forming the buffer block 140 may also include: first forming a buffer layer 141 that completely fills the opening and is also located on the top surface of the filling layer 150, then not processing the buffer layer 141, and directly using the buffer layer 141 as the buffer block 140 for subsequent steps. In this case, the width of the buffer layer 141 as the buffer block 140 is larger in the first direction X, but this does not affect the improvement of the word line groove morphology formed subsequently by the buffer block 140.

[0056] The above is a method for forming the filling layer 150 first and then forming the buffer block 140. Similarly, the buffer block 140 and the filling layer 150 may also have different sizes and positions, which will be described in detail below.

[0057] refer to Figure 12 In some embodiments, the method of forming the buffer block 140 may further include: forming a first buffer block 142, the first buffer block 142 being located on a portion of the first isolation structure 121, the first isolation structure 121 being located between a pair of adjacent active regions 110 in the first direction; and forming a second buffer block 143, the second buffer block 143 being located on a portion of the second isolation structure 122, the second isolation structure 122 being located between another pair of adjacent active regions 110 in the first direction, and the width of the second isolation structure 122 being greater than the width of the first isolation structure 121 along the first direction X. That is, for the isolation structures 120 on the substrate 100, the isolation structures 120 exposed on the surface of the substrate 100 have different widths, the width of the second isolation structure 122 being greater than the width of the first isolation structure 121, and the buffer blocks 140 formed on the first isolation structure 121 and the second isolation structure 122 may also be different. The buffer blocks 140 formed on the surfaces of the first isolation structure 121 and the second isolation structure 122 may be the first buffer block 142 and the second buffer block 143, respectively.

[0058] refer to Figures 12 to 13In some embodiments, along the first direction X, the total width of the second buffer block 143 may be greater than or equal to the total width of the first buffer block 142. Specifically, the total width of the second buffer block 143 may be greater than 0; the total width of the first buffer block 142 may be greater than or equal to 0. That is, the width of the second buffer block 143 on the wider second isolation structure 122 is wider, and the width of the first buffer block 142 on the narrower first isolation structure 121 is narrower. This is because in the wider second isolation structure 122, when etching to form the word line groove, the word line groove is farther away from the active areas 110 on both sides. Therefore, the control effect of the word line structure formed in the wider isolation structure 120 on the active area 110 is weaker than that of the word line structure formed in the narrower isolation structure 120. Therefore, it is more necessary to set a buffer block 140 on the isolation structure 120 for adjustment. The wider second buffer block 143 can further enhance the control of the subsequently formed word line structure over the channel of the active area 110 . Therefore, forming the wider second buffer block 143 on the surface of the wider second isolation structure 122 can better enhance the control of the word line over the active area 110 .

[0059] refer to Figure 13 , the width of the first buffer block 143 may be equal to 0. That is, only the second buffer block 143 is provided on the surface of the second isolation structure 122, and the first buffer block 142 may not be provided on the surface of the first isolation structure 121 (refer to FIG. Figure 12 The buffer blocks 140 thus provided can also enhance the control effect of the word lines at the wider second isolation structure 122 on the active area 110 . Furthermore, since the number of buffer blocks 140 is reduced, the process flow can be simplified and the process difficulty can be reduced.

[0060] refer to Figure 14 In some embodiments, the second buffer block 143 on the same second isolation structure 122 may include at least two separate sub-buffer blocks 1431. Multiple buffer blocks may be provided on the surface of a wider second isolation structure 122, with the total width of the multiple buffer blocks in the first direction X being relatively wide. This allows the buffer blocks above the second isolation structure 122 to better regulate the exposure time of different regions of the second isolation structure 122 to the etching environment during subsequent wordline groove etching, thereby enhancing the wordline's control over the active area 110.

[0061] In some embodiments, the first buffer block 142 may be located in the center region of the first isolation structure 121, and / or the second buffer block 143 may be located in the center region of the second isolation structure 122. Being located in the center region means that the first buffer block 142 or the second buffer block 143 on the surface of the first isolation structure 121 or the second isolation structure 122 may be located in the center region of the corresponding isolation structure along the first direction X, and the first buffer block 142 or the second buffer block 143 on the surface of the first isolation structure 121 or the second isolation structure 122 may be located in the center region of the corresponding isolation structure along a direction perpendicular to the first direction X. This is because when etching the isolation structure 120, if the buffer block 140 is not provided, the etching depth of the etching environment in the center region of the isolation structure 120 is the deepest, and the etching depth of the etching environment in the edge region of the isolation structure 120 is the shallowest. The buffer block 140 can change the contact time between the etching environment and the center region and the edge region of the isolation structure, thereby changing the etching depth of the etching environment in the center region and the edge region of the isolation structure 120, and changing the morphology of the etched word line groove. When the buffer block 140 is located in the center of the isolation structure 120, the time for the center of the isolation structure 120 to come into contact with the etching environment can be appropriately delayed, thereby effectively improving the wordline groove morphology. In other embodiments, the position of the buffer block 140 on the surface of the isolation structure 120 can also be offset relative to the center.

[0062] In addition, the positions of the first buffer block 142 and the second buffer block 143 on the surfaces of the first isolation structure 121 and the second isolation structure 122 can have multiple possibilities. The first buffer block 142 and the second buffer block 143 can both be located in the central area of ​​the first isolation structure 121 and the second isolation structure 122, or the first buffer block 142 can be located in the central area of ​​the first isolation structure 121, and the second buffer block 143 can not be located in the central area of ​​the second isolation structure 122; or, the first buffer block 142 can not be located in the central area of ​​the first isolation structure 121, and the second buffer block 143 can be located in the central area of ​​the second isolation structure 122.

[0063] refer to Figure 15 , Figure 15This is a schematic top-down view of a step in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. It should be noted that, for ease of illustration, the figure does not show all structures within the semiconductor structure. In some embodiments, the buffer block 140 can span the wordline region 130 along the second direction Y and also be located in an area adjacent to the wordline region 130 along the second direction Y. The second direction Y is parallel to the surface of the substrate 100 and perpendicular to the first direction X. There are many situations regarding the length of the buffer block 140 in the second direction Y: for example, the buffer block 1401 spans across multiple word line regions 130 along the second direction Y, and in this case, the buffer block 1401 covers multiple first isolation structures 121 and second isolation structures 122; for another example, the length of the buffer block 1402 in the second direction Y can be greater than the length of the word line region 130 in the second direction Y, and such a buffer block 1402 can be located on the surface of the first isolation structure 121 or the surface of the second isolation structure 122; for another example, the length of the buffer block 1403 in the second direction Y can also be less than the length of the word line region 130 in the second direction Y, and such a buffer block 1403 can also be located on the surface of the first isolation structure 121 or the surface of the second isolation structure 122. Figure 15 The buffer blocks 1401 and 1402 shown in the figure have a larger size along the second direction Y. In actual production, this can reduce the difficulty of manufacturing the buffer blocks 140 to a certain extent, thereby improving production efficiency. In the subsequent dry etching process, the portion of the buffer blocks 140 located outside the wordline region 130 is not etched. The etching environment can act only on the wordline region 130, which can simplify the process flow and reduce the difficulty while ensuring that the appropriate wordline grooves are etched.

[0064] In some embodiments, the buffer block 140 can span at least two word line regions 130. The buffer block 140 can span multiple word line regions 130 along the second direction Y. In this case, the multiple word line regions 130 share the same buffer block 140. This configuration of the buffer block 140 has a larger size in the second direction Y. This can further reduce the difficulty of manufacturing the buffer block 140 during actual production. Furthermore, the reduced number of buffer blocks 140 can simplify the process flow, thereby improving production efficiency.

[0065] In some embodiments, the thickness of the buffer block 140 in a direction perpendicular to the surface of the substrate 100 may be 2 nm to 4 nm. For example, the thickness of the buffer block 140 in a direction perpendicular to the surface of the substrate 100 may be 2 nm, 2.8 nm, 3 nm, 3.3 nm, 4 nm, etc. The thickness of the buffer block 140 affects the degree to which the buffer block 140 alters the morphology of the subsequently formed wordline groove, thereby affecting the improvement in the wordline's ability to control the channel of the active area 110. If the buffer block 140 is too thick in a direction perpendicular to the surface of the substrate 100, it may result in some waste, and the bottom surface of the wordline groove facing the center area of ​​the isolation structure 120 may be too high compared to the bottom surface of the wordline groove facing the edge area of ​​the isolation structure 120. If the buffer block 140 is too thin in a direction perpendicular to the surface of the substrate 100, it may not effectively improve the morphology of the wordline groove and may not effectively improve the wordline's ability to control the channel of the active area 110. Therefore, the thickness of the buffer block 140 needs to be selected within a suitable range. When the thickness of the buffer block 140 is 2 nm to 4 nm, the subsequently formed word line can have a stronger control capability over the active area 110 while avoiding material waste.

[0066] In some embodiments, the material of the buffer block 140 may include nitride or oxynitride, for example, the material of the buffer block 140 may include silicon nitride or silicon oxynitride, etc. The material of the filling layer 150 may include oxide, for example, the material of the filling layer 150 may include silicon oxide, etc. The material of the isolation structure 120 may include oxide, for example, the material of the isolation structure 120 may include silicon oxide, etc. In this way, when the subsequent process step of etching the word line groove is performed, the etching rate of the buffer block 140 in the same etching environment is lower than the etching rate of the filling layer 150 and the isolation structure 120, so that the buffer block 140 can play a role in changing the morphology of the word line groove.

[0067] refer to Figure 16 , using a dry etching process, etching the filling layer 150 of the word line region 130 (refer to Figure 14 ), the buffer block 140, the isolation structure 120 and the active area 110 to form a word line groove 160, wherein, in the word line area 130, the surface of the isolation structure 120 facing the filling layer 150 is exposed to the dry etching process environment before the surface of the isolation structure 120 facing the buffer layer 141.

[0068] The word line groove 160 etched at this time is used to form a word line structure in subsequent steps. The morphology of the word line groove 160 is the morphology of the word line structure. The closer the two side walls of the word line groove 160 in the first direction X are to the active area 110, the stronger the control ability of the word line structure over the active area 110.

[0069] In some embodiments, the dry etching process can have a lower etching rate for the buffer block 140 than for the filling layer 150. When the dry etching process etches the wordline groove 160 along the second direction Y toward the substrate 100, the buffer block 140 located in the center area of ​​the isolation structure 120 and the filling layer 150 located in the edge area of ​​the isolation structure 120 are in contact with the dry etching environment at the same time, and the thickness of the buffer block 140 and the filling layer 150 in the direction perpendicular to the substrate surface are consistent. Since the dry etching process has a lower etching rate for the buffer block 140 than for the filling layer 150, the isolation structure 120 directly opposite the buffer block 140 will be exposed later than the isolation structure 120 directly opposite the filling layer 150, thereby improving the morphology of the wordline groove 160 and making the distance between the two side walls of the wordline groove 160 along the second direction Y and the active area 110 smaller. Regarding the bottom surface of the etched word line groove 160 , a central region of the bottom surface may protrude in a direction away from the substrate 100 relative to an edge region.

[0070] Figure 17 A schematic cross-sectional view of a step of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is provided. Figure 18 for Figure 17 Schematic diagram of the top view structure.

[0071] refer to Figures 17 and 18 , forming a word line structure 170 filling the word line groove 160.

[0072] In some embodiments, the wordline structure 170 may be formed by a deposition process, and the wordline structure may include a dielectric layer and a conductive layer. The morphology of the wordline structure 170 is the same as that of the wordline groove 160. The sidewalls of the wordline structure 170 along the first direction X are relatively close to the active area 110, which provides greater control over the channel of the active area 110 and improves the performance of the semiconductor structure.

[0073] refer to Figure 19 A word line capping layer 180 may also be formed. The word line capping layer 180 is located on a surface of the word line structure 170 away from the substrate 100 . The word line structure 170 and the word line capping layer 180 together fill the word line groove 160 .

[0074] An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which first provides a substrate 100 having a plurality of active areas 110 and an isolation structure 120 located between the active areas 110, and the substrate 100 also including a word line area 130 extending along a first direction X; then, a buffer block 140 and a filling layer 150 are formed, the buffer block 140 is located on a portion of the isolation structure 120 between adjacent active areas 110 of the word line area 130, and the buffer block 140 is spaced apart from the adjacent active areas 110, and the filling layer 150 is located on the substrate 100 and fills between adjacent buffer blocks 140; wherein the size, position and formation method of the buffer block 140 can have many variations; a dry etching process is used to etch word line grooves 160 in the word line area 130, and the surface of the isolation structure 120 facing the filling layer 150 is exposed to the dry etching process environment before the surface of the isolation structure 120 facing the buffer block 140; finally, a word line structure 170 is formed that fills the word line grooves 160. In this way, the ability of the word line structure 160 to control the channel of the active region 110 can be improved.

[0075] Accordingly, another embodiment of the present disclosure further provides a semiconductor structure, which is manufactured using the above-mentioned semiconductor structure manufacturing method. The semiconductor structure provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. For parts that are identical or corresponding to the previous embodiment, reference can be made to the corresponding description of the previous embodiment and will not be repeated in detail below.

[0076] Figure 19 A schematic cross-sectional view of a semiconductor structure provided in accordance with an embodiment of the present disclosure.

[0077] refer to Figure 19 The semiconductor structure includes a substrate 100, the substrate 100 includes a plurality of discrete active regions 110 and an isolation structure 120 located between adjacent active regions 110, the substrate 100 includes a word line region 130 extending along a first direction X (reference Figure 2 ); a word line structure 170, the word line structure 170 is located in the word line region 130, the word line structure 170 spans the active region 110 and the isolation structure 120, wherein in the first direction X, the word line structure 170 located in the isolation structure 120 between adjacent active regions 110 has at least two recessed portions 171.

[0078] The substrate 100 includes an active region 110 and an isolation structure 120. Multiple discrete active regions 110 are arranged in an array on the substrate 100, with the isolation structure 120 located between adjacent active regions 110. The active regions 110 may be made of silicon. The isolation structure 120 may be made of silicon oxide. The active regions 110 are transistors in a semiconductor structure. The substrate 100 includes multiple transistors arranged in an array. Wordline structures 170 are connected to the gates of the transistors, meaning that the wordline structures 170 are in contact with the active regions 110.

[0079] The wordline structure 170 has at least two recessed portions 171. Specifically, a wordline structure 170 located on the bottom surface of the substrate 100 has at least two regions with a greater depth than other regions. According to the above-described semiconductor structure manufacturing method embodiment, among the wordline structures 170 located within the isolation structure 120 between adjacent active regions 110, the wordline structures 170 located in the center region of the isolation structure 120 along the first direction X have a smaller bottom surface depth, while the wordline structures 170 located in the edge regions of the isolation structure 120 along the first direction X have a larger bottom surface depth.

[0080] In some embodiments, wordline structure 170 further includes: a first wordline portion 172, located within a first isolation structure 121, which is located between a pair of adjacent active regions 110. First wordline portion 172 has at least two recesses 171; and a second wordline portion 173, located within a second isolation structure 122, which is located between another pair of adjacent active regions 110. Second wordline portion 173 has at least two recesses 171, and the width of second isolation structure 122 is greater than the width of first isolation structure 121 along the first direction X. That is, along the first direction X, the second wordline portion 173 is located within the wider second isolation structure 122, while the first wordline portion 172 is located within the narrower first isolation structure 121. Both first wordline portion 172 and second wordline portion 173 may include at least two recesses 171. The distance between the two sidewalls of the word line structure 170 in the first direction X and the active area 110 is relatively small, and the word line structure 170 has a stronger ability to control the channel of the active area 110 .

[0081] In some embodiments, the semiconductor structure may further include a word line capping layer 180 . The word line capping layer 180 is located on a surface of the word line structure 170 away from the substrate 100 . The word line structure 170 and the word line capping layer 180 together fill the word line groove 160 .

[0082] An embodiment of the present disclosure provides a semiconductor structure comprising: a substrate 100 including a plurality of discrete active regions 110 and an isolation structure 120 located between adjacent active regions 110; the substrate 100 including a wordline region 130 extending along a first direction X; and a wordline structure 170 located within the wordline region 130. The wordline structure 170 spans the active regions 110 and the isolation structure 120, and the wordline structure 170 within the isolation structure 120 between adjacent active regions 110 in the first direction X has at least two recesses 171. This allows the wordline structure 170 to effectively control the channels of the active regions 110.

[0083] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a plurality of discrete active regions and an isolation structure located between adjacent active regions, the substrate comprising a word line region extending along a first direction; forming a buffer block and a filling layer, wherein the buffer block is located on a portion of the isolation structure between adjacent active areas of the word line region, and the buffer block is spaced apart from the adjacent active areas, and the filling layer is located on the substrate and fills the area between adjacent buffer blocks; Using a dry etching process, etching the filling layer, the buffer block, the isolation structure, and the active area in the word line region to form a word line groove, wherein a surface of the isolation structure facing the filling layer in the word line region is exposed to the dry etching process before a surface of the isolation structure facing the buffer block; A word line structure filling the word line groove is formed.

2. The manufacturing method according to claim 1, wherein The dry etching process has an etching rate on the buffer block that is lower than an etching rate on the filling layer.

3. The manufacturing method according to claim 1, wherein The method of forming the buffer block and the filling layer includes: The buffer block is formed first, and then the filling layer is formed.

4. The manufacturing method according to claim 3, wherein: The steps of forming the filling layer include: forming a filling film on the substrate, wherein the filling film fills the area between adjacent buffer blocks and also covers the top surface of the buffer block; The filling film is planarized, and the remaining filling film serves as the filling layer.

5. The manufacturing method according to claim 4, wherein: The stop position of the planarization process is higher than the top surface of the buffer block, and the formed filling layer also covers the top surface of the buffer block.

6. The manufacturing method according to claim 4, wherein: The stop position of the planarization process is the top surface of the buffer block, and the top surface of the formed filling layer is flush with the top surface of the buffer block.

7. The manufacturing method according to claim 3, wherein: The process steps for forming the buffer block include: forming a buffer layer on the substrate to cover the entire surface of the substrate; The buffer layer is patterned to form the buffer block.

8. The manufacturing method according to claim 1, wherein: The method of forming the buffer block and the filling layer includes: First, the filling layer is formed, and the filling layer has an opening extending from the top surface to the bottom surface; The buffer block is formed to fill the opening.

9. The manufacturing method according to claim 8, wherein: The ratio of the depth of the opening to the thickness of the filling layer is in the range of 0.5-1.

10. The manufacturing method according to claim 8, wherein: The process steps for forming the buffer block include: forming a buffer layer, wherein the buffer layer completely fills the opening and is also located on a top surface of the filling layer; The buffer layer that is higher than the top surface of the filling layer is removed, and the remaining buffer layer serves as the buffer block.

11. The manufacturing method according to claim 1, wherein The method of forming the buffer block further includes: forming a first buffer block, wherein the first buffer block is located on a portion of the first isolation structure, and the first isolation structure is located between a pair of the active regions adjacent to each other in the first direction; A second buffer block is formed, the second buffer block is located on a portion of the second isolation structure, the second isolation structure is located between another pair of the active regions adjacent in the first direction, and the width of the second isolation structure along the first direction is greater than the width of the first isolation structure.

12. The manufacturing method according to claim 11, wherein: Along the first direction, the total width of the second buffer block is greater than or equal to the total width of the first buffer block; wherein, the total width of the second buffer block is greater than 0; and the total width of the first buffer block is greater than or equal to 0.

13. The manufacturing method according to claim 12, wherein: On the same second isolation structure, the second buffer block includes at least two separate sub-buffer blocks.

14. The manufacturing method according to claim 11, wherein: The first buffer block is located in a central area of ​​the first isolation structure; and / or the second buffer block is located in a central area of ​​the second isolation structure.

15. The manufacturing method according to claim 1, wherein: The buffer block crosses the word line region along a second direction and is located in a region adjacent to the word line region in the second direction, wherein the second direction is parallel to the substrate surface and perpendicular to the first direction.

16. The manufacturing method according to claim 15, wherein: The buffer block spans across at least two word line regions.

17. The manufacturing method according to claim 1, wherein: In a direction perpendicular to the surface of the substrate, the thickness of the buffer block is 2 nm to 4 nm.

18. The manufacturing method according to claim 1, wherein: The material of the buffer block includes nitride or oxynitride; the material of the filling layer includes oxide; and the material of the isolation structure includes oxide.

19. A semiconductor structure, characterized in that include: a substrate comprising a plurality of discrete active regions and an isolation structure between adjacent active regions, the substrate comprising a word line region extending along a first direction; a word line structure, the word line structure being located in the word line region and spanning the active region and the isolation structure, wherein in the first direction, the word line structure located in the isolation structure between adjacent active regions has at least two recessed portions; Wherein, the semiconductor structure is obtained by the manufacturing method according to any one of claims 1-18.

20. The semiconductor structure according to claim 19, wherein The word line structure includes: a first word line portion, the first word line portion being located within a first isolation structure, the first isolation structure being located between a pair of adjacent active regions, and the first word line portion having at least two recessed portions; A second word line portion, wherein the second word line portion is located within a second isolation structure, the second isolation structure is located between another pair of adjacent active areas, the second word line portion has at least two recessed portions, and along the first direction, the width of the second isolation structure is greater than the width of the first isolation structure.

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