Sensors, autonomous sensors, and related systems, methods, and devices

Abstract

The disclosed embodiments relate to sensing the state and state changes of signals and sensors for such sensing, including but not limited to autonomous sensors. Such sensors may include analog signal threshold detection circuitry, state detection circuitry, and measurement circuitry. The analog signal threshold detection circuitry may be configured to alternately assert and de-assert a threshold detection indication in response to an input signal and its state. The state detection circuitry may be configured to generate a signal state indication regarding the state of the input signal. The measurement circuitry may be configured to generate a measurement result, such as a count, a conversion rate, or a frequency, in response to assertion of the threshold detection indication and the signal state indication. In some embodiments, the disclosed sensor may have a programmable threshold value for sensing signal states and changes therein.

Description

[0001] Priority Declaration

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 62 / 706,486, filed on August 19, 2020, entitled “AUTONOMOUS CORE INDEPENDENT DISCRETE SIGNAL SLEW RATESENSORS,” under 35 U.S.C. §119(e), the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments discussed herein generally relate to electronic components, and more particularly to sensing the state of discrete signals and sensors and autonomous sensors for performing such sensing. Some embodiments generally relate to sensors with programmable thresholds for sensing signal states. Some embodiments generally relate to slew rate sensing and frequency sensing. Background Art

[0004] Discrete signals are used in a variety of operating environments. Non-limiting examples of discrete signals include: digital signals used for communications, pulse width and pulse duration modulated signals, pulse density modulated signals, and clock signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the figure number in which the element is first introduced.

[0006] Figure 1 is a block diagram of a signal transmission system according to one or more embodiments.

[0007] Figure 2 is a block diagram of an autonomous sensor according to one or more embodiments.

[0008] Figure 3 is a block diagram of an analog signal threshold detection circuit according to one or more embodiments.

[0009] Figure 4A 、 Figure 4B and Figure 4C is a block diagram of a measurement circuit according to one or more embodiments.

[0010] Figure 5 is a flowchart of a process according to one or more embodiments.

[0011] Figure 6 is a flowchart of a process according to one or more embodiments.

[0012] Figure 7 Circuits are shown that may be used to implement various functions, operations, acts, processes and / or methods according to one or more embodiments. DETAILED DESCRIPTION

[0013] In the following detailed description, reference is made to the accompanying drawings which form a part of this disclosure and in which are shown, by way of example, specific examples of embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one skilled in the art to practice the present disclosure. However, other embodiments disclosed herein may be utilized, and structural, material, and process changes may be made without departing from the scope of this disclosure.

[0014] The illustrations presented herein are not intended to be actual views of any particular method, system, apparatus, or structure, but are merely idealized representations for describing embodiments of the present disclosure. In some cases, similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, construction, or any other attribute.

[0015] The following description may include examples to help those skilled in the art practice the embodiments disclosed herein. The terms "exemplary," "by way of example," and "for example" are used to indicate that the description is illustrative, and while the scope of the present disclosure is intended to encompass examples and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of the present disclosure to the specified components, steps, features, functions, etc.

[0016] It should be readily understood that the components of the embodiments as generally described herein and illustrated in the accompanying drawings may be arranged and designed in many different configurations. Therefore, the following description of various embodiments is not intended to limit the scope of the present disclosure, but rather is merely representative of various embodiments. Although various aspects of these embodiments may be shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0017] In addition, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement the present disclosure, unless otherwise indicated herein. Components, circuits, and functions may be shown in block diagram form so as not to obscure the present disclosure with unnecessary detail. On the contrary, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure, unless otherwise indicated herein. In addition, the block definitions and the partitioning of logic between the various blocks are examples of specific embodiments. It will be apparent to one of ordinary skill in the art that the present disclosure can be practiced through many other partitioning solutions. In most cases, details regarding timing considerations, etc. have been omitted, where such details are not required to obtain a complete understanding of the present disclosure and are within the capabilities of one of ordinary skill in the relevant art.

[0018] Those skilled in the art will appreciate that any of a variety of different technologies and techniques may be used to represent information and signals. For clarity of presentation and description, some figures may illustrate signals as a single signal. Those skilled in the art will appreciate that a signal may represent a signal bus, where the bus may have a variety of bit widths, and that the present disclosure may be implemented on any number of data signals, including a single data signal.

[0019] The various exemplary logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or executed with a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A general-purpose processor (also referred to herein as a "host processor" or simply "host") may be a microprocessor, but in an alternative embodiment, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer when it is configured to execute computing instructions (e.g., software code) associated with the embodiments of the present disclosure.

[0020] Embodiment can be described according to the process that is depicted as flow chart, structure diagram or block diagram.Although flow chart can describe operation action as continuous process, many actions in these actions can be performed according to another sequence, in parallel or substantially simultaneously.In addition, the order of action can be rearranged.The process herein can correspond to method, thread, function, process (procedure), subroutine, subprogram, other structure or their combination.In addition, the method disclosed herein can be implemented by hardware, software or both.If realized in software, these functions can be stored or transferred to computer-readable medium as one or more instructions or codes.Computer-readable medium includes both computer storage medium and communication medium, and this communication medium includes any medium that is conducive to transferring computer program from one location to another location.

[0021] Any reference to elements herein using designations such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitations are explicitly stated. Rather, these designations may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, reference to a first element and a second element does not mean that only two elements may be employed therein or that the first element must precede the second element in some manner. Furthermore, unless otherwise specified, a group of elements may include one or more elements.

[0022] As used herein, the term "substantially" with respect to a given parameter, property, or condition refers to and includes the degree to which a person of ordinary skill in the art would understand that the given parameter, property, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances. By way of example, depending on the specific parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be satisfied by at least 90%, by at least 95%, or even by at least 99%.

[0023] As used herein, any relative terms (such as "above", "below", "upper", "lower", etc.) are used for clarity and convenience in understanding the present disclosure and the drawings, and do not imply or depend on any particular preference, orientation, or order unless the context clearly indicates otherwise.

[0024] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, the elements may be in direct physical or electrical contact, or intervening elements or layers may be present. In contrast, when an element is described as being "directly coupled" to another element, there are no intervening elements or layers. The term "connected" may be used interchangeably with the term "coupled" in this specification and have the same meaning, unless expressly indicated otherwise or the context would indicate otherwise to one of ordinary skill in the art.

[0025] As used herein, a "discrete signal" refers to a signal that generally exhibits a change in state between a first state and a second state. Such a discrete signal may change substantially monotonically from the first state to the second state, and may additionally or alternatively change substantially monotonically from the second state to the first state. Optionally, such a discrete signal may remain in the first state for a first period of time and in the second state for a second period of time. Such first and second states may each be defined as a threshold value or as being above or below a threshold value, respectively.

[0026] The rate at which a discrete signal transitions from a first state (such as a first discrete value) to a second state (such as a second discrete value) during a given time period is referred to as its "slew rate." The slew rate can vary. As a non-limiting example, the slew rate of a digital signal on a wired portion of a communication path may decay by an amount proportional to the length of the wired path. As another non-limiting example, a faulty or limited connector coupling an electronic component may cause a degradation in the slew rate of a discrete signal. As yet another non-limiting example, capacitive or resistive loading on an electronic system (e.g., caused by capacitive connections to different voltage potentials, such as, but not limited to, physical proximity or touch by a human body, or a short circuit) may cause a degradation in the slew rate of a discrete signal. As a non-limiting example, in the case of digital signals, slew rate degradation may corrupt the data recovered from the digital signal. Due to corrupted or lost data, communications may be misinterpreted by a receiver. In a microcontroller, a pulse-width modulated (PWM) or pulse-density modulated (PDM) signal may incorrectly control a peripheral device. When a clock signal slowly increases and exceeds the signal threshold of an input device, noise may cause the signal threshold to be repeatedly crossed. As non-limiting examples, falsely detected threshold crossings and corrupted data may increase power consumption and result in undefined behavior of circuits using the clock.

[0027] As a non-limiting example, sensors are sometimes used to measure discrete signals to measure slew rates to identify slew rate degradation so that a user can take some appropriate action. A typical slew rate sensor can be configured to detect specific voltage levels associated with the discrete signal and determine the rate at which the discrete signal transitions between such detected voltage levels. Some sensors, slew rate sensors, or other sensors may include analog voltage comparators, one for each of the specific discrete voltage levels to be detected. However, the inventors of the present disclosure recognize that, compared to digital circuits, analog signal comparators, voltage comparators, or other comparators are typically more demanding in terms of space (i.e., silicon area, but not limited to), central processing unit (CPU) utilization (if the CPU is required to constantly reconfigure the analog comparator or monitor / supervise the output of the comparator - such as in software implementations), and / or the power required to accommodate integrated circuits used to implement analog electronic components.

[0028] In addition to or in lieu of analog hardware components, the operation, slew rate, or other aspects of a sensor can be implemented in software. However, even if the software portion of such a sensor is limited to setup and maintenance, there will still be intervention by the CPU, which occupies the CPU. This can reduce the efficiency of a computing system (e.g., an embedded system, a microcontroller system, or a microelectronic device, but not limited thereto) because CPU time is utilized by non-core processes of the system (e.g., setup and maintenance of a slew rate sensor, but not limited thereto) rather than by the core processes of the computing system. Furthermore, whenever the CPU performs an operation related to the sensor, setup, or maintenance, it consumes power at the CPU rate. In some cases, systems with single-core or dual-core CPUs may be completely unable to accommodate sensors that over-utilize the CPU. Furthermore, in the case of slew rate or frequency sensors, if the ratio of the slew rate or frequency period to the CPU speed is too high, the CPU will miss transitions between discrete signal levels or signal states.

[0029] The inventors of the present disclosure recognized that it would be desirable to have a slew rate sensor that did not have some or all of the above-mentioned disadvantages.

[0030] One or more embodiments relate to sensors. Such sensors may include analog voltage threshold detection circuitry, measurement circuitry, state detection circuitry, and one or more memories having upper signal thresholds, lower signal thresholds, and measurements stored therein. The memory may be any type of suitable volatile or non-volatile memory (e.g., random access memory (RAM), flash memory, read-only memory (ROM), programmable ROM, erasable programmable ROM, electrically erasable programmable read-only memory (EEPROM), and variations thereof (such as, but not limited to, read-only memory (REM) and resistive memory).

[0031] Disclosed herein are circuits for sensing the state and / or state changes of discrete signals, and in various embodiments, such sensing can be performed with or without intervention or supervision by a processing core or CPU. The ability to perform tasks (e.g., measurements associated with slew rate sensing, but not limited thereto) without intervention or supervision from the processing core or CPU is referred to herein as "core independence," "core-independent," "autonomous," or terms derived therefrom. While the processing core or CPU may initialize the parameters of the circuit (e.g., setting initial upper and lower thresholds for analog signal threshold detection, but not limited thereto), such circuits can perform the slew rate measurement, state detection, state change detection, and threshold detection operations discussed herein without intervention or supervision from the processing core or CPU. Thus, the slew rate measurement, state detection, and threshold detection operations can be performed without interrupting the processing core or CPU while it is otherwise operating, or without enabling the processing core or CPU when it is in a disabled state. As a non-limiting example, precious power and processing bandwidth may be conserved compared to computing systems that require a processing core or CPU to enable and disable multiple analog signal threshold detection circuits or measurement circuits as discussed above.

[0032] Figure 1 1 is a block diagram depicting a signal transmission system 100 configured to perform autonomous slew rate sensing according to one or more embodiments. A signal transmission link 108 is defined by a transmitter 104 and a receiver 106 configured to transmit and receive discrete signals, respectively, via a signal path 116. The signal path 116 may include any combination of wired and non-wired portions. The transmitter 104 is generally configured to generate and / or provide discrete signals. As non-limiting examples, the transmitter 104 may be or may include a serial or parallel communication transmitter or transceiver, a signal generator (such as a pulse width or pulse duration modulator), or a clock source. The receiver 106 is generally configured to receive discrete signals. As non-limiting examples, the receiver 106 may be or may include a serial or parallel communication receiver or transceiver, an electronic component configured to receive a pulse width or pulse duration modulated signal, or an electronic component configured to receive a clock signal.

[0033] The autonomous sensor 102 can generally be configured to detect and measure changes in state of a discrete signal (here, observation signal 114). The autonomous sensor 102 is arranged to observe one or more discrete signals, labeled observation signals 114, transmitted on a signal path 116. In one or more embodiments, the autonomous sensor 102 can be coupled to the transmitter 104, the receiver 106, or a portion of the signal path 116 that can exhibit or be affected by slew rate degradation. In some cases, it may be desirable to observe the discrete signal substantially as an input to the receiver 106, in which case the autonomous sensor 102 can be coupled to a location on the signal path 116 that is physically or electrically "close" to the receiver 106, to a terminal circuit from which the receiver 106 reads the discrete signal, or to an input pin of the receiver 106, without limitation, such that the observation signal 114 substantially matches the signal received by the receiver 106.

[0034] As another non-limiting example, the autonomous sensor 102 can be coupled to a portion of the signal path 116 near or after a connector (e.g., a physical connector such as a wire or trace, or a wireless connector such as a capacitive or inductive signal coupler, but not limited thereto) that couples the portion of the signal path 116. As yet another non-limiting example, the autonomous sensor 102 can be coupled to a location on the signal transmission link 108, where the portion of the signal transmission link 108 that couples the location to the transmitter 104 has a certain length (e.g., a predetermined, pre-specified, or specified length, but not limited thereto) that is associated with slew rate attenuation. Other selection criteria for the coupling location besides those discussed are within the scope of this disclosure. The use of multiple autonomous slew rate sensors (each of which is an autonomous sensor 102) is also within the scope of this disclosure. For example, in some embodiments, multiple portions of the signal transmission link 108 can have autonomous sensors 102 coupled thereto, or a portion of the signal transmission link 108 can have multiple such autonomous slew rate sensors coupled thereto.

[0035] The optional CPU 110 is coupled to the signal transmission link 108 and the autonomous sensor 102 and, generally speaking, is configured to communicate with the autonomous sensor 102 via signals 112 (e.g., communication signals or control signals, but not limited to such) and / or initialize the autonomous sensor, as discussed later herein (e.g., at setup time).

[0036] In one or more embodiments, the signal transmission system 100 can be implemented in a single system or device or in multiple systems or devices. As non-limiting examples, part or all of the signal transmission system 100 can be implemented in a system on a chip, a separate system on a chip, one or more microcontrollers, and combinations and sub-combinations thereof. In one or more embodiments, the transmitter 104 or the receiver 106 can include the autonomous sensor 102. In one or more embodiments, the electronic component coupled to the signal path 116 or including a portion thereof can include the autonomous sensor 102. In one or more embodiments, the autonomous sensor 102 can be implemented by a chip, microcontroller, or device coupled to the signal path 116. In one or more embodiments, the CPU 110 can be the CPU of a device or microcontroller that includes an embodiment of the autonomous sensor 102 and, optionally, the transmitter 104 and the receiver 106, for example, in peripheral devices of such a device or microcontroller.

[0037] In one or more embodiments, as a non-limiting example, the signal path 116 may include 1 to n wired or wireless signal sub-paths for parallel communication (where n ≥ 2). The signal transmission system 100 may include a plurality of autonomous slew rate sensors, each being an autonomous sensor 102, individually coupled to each signal sub-path (e.g., coupled to each line, but not limited thereto) or portion thereof of the signal path 116. Although Figure 1 The particular example depicted includes the same number of autonomous slew rate sensors as signal paths, but a one-to-one correspondence is not required and the signal transmission system 100 may include any number of autonomous sensors 102 without exceeding the scope of this disclosure.

[0038] Figure 2 is a block diagram illustrating an autonomous sensor 200 according to one or more embodiments. Figure 1 Non-limiting examples of autonomous sensors 102 .

[0039] The autonomous sensor 200 can generally be configured to calculate measurements associated with an input signal (here, the observation signal 216) and store the measurements in a measurement register 208 of the memory 202. Non-limiting examples of the calculated measurements include: conversion rate, frequency, total operating time, time in a particular state, number of state changes per a specified time period, differences in the above items for different time periods, and changes in the above items over time. The autonomous sensor 200 can include the memory 202, an analog signal threshold detection circuit 210, a measurement circuit 212, and a state detection circuit 214.

[0040] The state detection circuit 214 may generally be configured to generate a signal state indication 220 for provision to the analog signal threshold detection circuit 210 and the measurement circuit 212. The signal state indication 220 may be an indication of the current state of the observation signal 216. In one or more embodiments, the available states to be indicated include: below a lower signal threshold, above an upper signal threshold, between the lower and upper signal thresholds and rising (e.g., a rising edge of a signal having a signal level between the specified thresholds, but not limited thereto), and between the lower and upper signal thresholds and falling (e.g., a falling edge of a signal having a signal level between the specified thresholds, but not limited thereto).

[0041] The analog signal threshold detection circuit 210 may generally be configured to assert a threshold detection indication 218 in response to the observation signal 216, the signal state indication 220, and either the upper threshold reference signal 222 or the lower threshold reference signal 224. The analog signal threshold detection circuit 210 may alternately select a reference signal based on the upper threshold reference signal 222 or the lower threshold reference signal 224 in response to the state indicated by the signal state indication 220, and assert the threshold detection indication 218 in response to detecting that the signal level of the observation signal 216 is greater than (i.e., higher than) the selected reference signal.

[0042] The upper threshold reference signal 222 and the lower threshold reference signal 224 may be or be based on values ​​stored at the upper signal threshold register 204 and the lower signal threshold register 206, respectively. The stored values ​​may correspond to or represent specific (e.g., but not limited to, specified, pre-specified, or predetermined) thresholds for the signal levels expected for the observation signal 216. Figure 2 In the particular example depicted, the particular thresholds are a programmed upper signal threshold 228 and a programmed lower signal threshold 230 , provided by, as non-limiting examples, CPU 110 , configuration registers (not shown), a configuration tool (not shown), or a combination thereof.

[0043] It is worth noting that programmed threshold values ​​(e.g., programmed upper signal threshold value 228 and programmed lower signal threshold value 230, but not limited thereto), stored signal threshold values ​​(e.g., stored at upper signal threshold value register 204 or lower signal threshold value register 206, but not limited thereto), or reference signals based thereon (e.g., Figure 3The values ​​or signal levels of the upper threshold reference signal 222 and the lower threshold reference signal 224 or the fixed level reference signal 314 (including, but not limited to, the values ​​of the upper threshold reference signal 222 and the lower threshold reference signal 224 or the fixed level reference signal 314) can be offset from the corresponding discrete signal levels. Signal thresholds and signal levels that are the same as or offset from a specified signal threshold for a discrete signal (e.g., specified by, but not limited to, an industry standard, a data sheet, a configuration file, a register, or a technical specification) are contemplated herein and encompassed by the term "signal threshold." As non-limiting examples, the offsets can be used for timing purposes and to account for noise or attenuation (e.g., noise or amplitude attenuation expected on a transmission line, but not limited to).

[0044] In one or more embodiments, the analog signal threshold detection circuit 210 can be configured to alternately use the upper threshold reference signal 222 or the lower threshold reference signal 224 in response to the signal state indication 220. Figure 3 As discussed, the analog signal threshold detection circuit 210 can be configured to use the lower threshold reference signal 224 when the signal state indication 220 corresponds to being below the lower signal threshold or between the lower signal threshold and the upper signal threshold and falling (e.g., a falling edge), and to use the upper threshold reference signal 222 when the signal state indication 220 corresponds to being above the upper signal threshold or between the lower signal threshold and the upper signal threshold and rising (e.g., a rising edge).

[0045] Autonomous sensor 200 can be configured to provide a threshold detection indication 218 asserted / deasserted by analog signal threshold detection circuit 210 to measurement circuit 212 and state detection circuit 214. Measurement circuit 212 can generally be configured to generate a slew rate measurement 226 in response to threshold detection indication 218 and signal state indication 220.

[0046] State detection circuitry 214 may generally be configured to generate signal state indication 220 in response to threshold detection indication 218, and more specifically to modify the state indicated by signal state indication 220 in response to assertion / deassertion of threshold detection indication 218 and the previous state indicated by signal state indication 220. As a non-limiting example, upon assertion / deassertion of threshold detection indication 218, state detection circuitry 214 may be configured to determine a new state of observation signal 216 using a map of previous states and possible state transitions (a "state transition map").

[0047] In one or more embodiments, the state detection circuit 214 can be configured to detect an initial state of the observation signal 216, for example, upon startup of the autonomous sensor 200. As a non-limiting example, the initial state can be detected by assuming a state of the observation signal 216 and then adjusting the assumed state (e.g., using a state of a particular pattern via the signal state indication 220, without limitation) in response to assertion / deassertion of the threshold detection indication 218 until it stabilizes at the current state of the observation signal 216. In embodiments where the state detection circuit 214 is configured to detect an initial state upon startup of the autonomous sensor 200, the autonomous sensor 200 can be activated and deactivated as needed (e.g., by the CPU 110 or another device, without limitation).

[0048] As a specific non-limiting example, upon startup of the autonomous sensor 200, the state detection circuit 214 may configure the analog signal threshold detection circuit 210 to use a lower signal threshold (e.g., stored at the lower signal threshold register 206 of the memory 202) (via selection of a particular state of the signal state indication 220) and receive the lower threshold reference signal 224 at the analog signal threshold detection circuit 210. If the analog signal threshold detection circuit 210 does not immediately assert the threshold detection indication 218 in response to the lower signal threshold, the state detection circuit 214 thereby recognizes that the observed signal 216 is below the lower signal threshold and sets the signal state indication 220 to “below the lower signal threshold.” If the analog signal threshold detection circuit 210 immediately asserts the threshold detection indication 218, it will indicate that the signal level of the observed signal 216 is above the lower signal threshold. If the signal level of observation signal 216 is above the lower signal threshold, state detection circuitry 214 may (via selection of a particular state of signal state indication 220) configure analog signal threshold detection circuitry 210 to use an upper signal threshold (e.g., stored at upper signal threshold register 204 of memory 202) and receive as upper threshold reference signal 222 at analog signal threshold detection circuitry 210. If analog signal threshold detection circuitry 210 does not immediately de-assert threshold detection indication 218, this will indicate that the signal level of observation signal 216 is above the upper signal threshold, and state detection circuitry 214 will set signal state indication 220 to indicate a state indicating “above upper signal threshold.” If the analog signal threshold detection circuit 210 immediately de-asserts the threshold detection indication 218 in response to the upper signal threshold, the state detection circuit 214 recognizes that the observed signal 216 is between the upper signal threshold and the lower signal threshold, however there is no indication as to whether the observed signal is rising or falling, and therefore may wait until the threshold detection indication 218 is asserted, and in response to the assertion of the threshold detection indication 218, set the signal state indication 220 to indicate a state that indicates "above the upper signal threshold".

[0049] Upon detecting the current state of observation signal 216, state detection circuitry 214 may accordingly set signal state indication 220 to the detected current state and continuously update the state indication in response to state information gathered from assertion / deassertion of threshold detection indication 218 and according to the previous state of state transition logic, as set forth in Table 1, as a non-limiting example:

[0050]

[0051] Table 1: State transitions detected by the state detection circuit

[0052] Figure 3 is a block diagram illustrating an analog signal threshold detection circuit 300 according to one or more embodiments. Figure 2 The analog signal threshold detection circuit 300 may include a threshold selection logic 304 , a selection circuit 308 , a digital-to-discrete signal converter 318 , and an analog signal threshold detector 302 .

[0053] The selection circuit 308 can be configured to alternately select the upper threshold reference signal 222 or the lower threshold reference signal 224 available at an input (not labeled) of the selection circuit 308 in response to a selection signal 310 and provide a digital reference signal 306 corresponding to the selected signal. The threshold selection logic 304 can be configured to generate the selection signal 310 in response to the signal state indication 220 to control the selection of the upper threshold reference signal 222 or the lower threshold reference signal 224 at the selection circuit 308 according to logic configured as set forth in Table 2, as a non-limiting example:

[0054]

[0055] Table 2: Selection of threshold reference signals

[0056] The digital reference signal 306 is provided to a digital-to-discrete signal converter 318. The digital-to-discrete signal converter 318 may be configured to generate a fixed level reference signal in response to the digital signal, the fixed level reference signal having a signal level suitable for comparison with the observation signal 216 by the analog signal threshold detector 302. The fixed level reference signal or its signal level may correspond to the value represented by the digital signal. Figure 3In the particular example depicted, digital-to-discrete signal converter 318 includes a selection circuit 312 configured to select and provide a fixed-level reference signal 314 (e.g., a bandgap voltage reference) from among several fixed-level reference signals 316 (e.g., several available bandgap voltage references, but not limited thereto) available at an input of the selection circuit 312. In another embodiment, digital-to-discrete signal converter 318 may be or include a digital-to-analog converter (DAC).

[0057] Fixed-level reference signal 314 is provided to a reference input (unlabeled input) of analog signal threshold detector 302. Analog signal threshold detector 302 can be configured to assert threshold detection indication 218 in response to detecting that the signal level of observation signal 216 is greater than the signal level of fixed-level reference signal 314, and to de-assert threshold detection indication 218 in response to detecting that the signal level of observation signal 216 is less than the signal level of fixed-level reference signal 314. In another embodiment, the upper and lower threshold references can be read directly from memory as voltage signals having discrete voltage levels suitable for use as fixed-level reference signal 314 by analog signal threshold detector 302.

[0058] It is worth noting that Figure 3 As shown, the analog signal threshold detection circuit 300 may include a single analog signal threshold detector 302 that may be alternately provided with the upper threshold reference signal 222 and the lower threshold reference signal 224 as the fixed level reference signal 314 .

[0059] Figure 4A is a block diagram illustrating a measurement circuit 400a according to one or more embodiments. Figure 2 2 is a non-limiting example of a measurement circuit 212 where the slew rate measurement 226 is a count.

[0060] The counter 402 can be configured to increment a count 408 in response to a start / stop signal 406 generated by the start / stop logic 412 and provide the count 408 (here, as an n-bit signal) to a count buffer 410. In one or more embodiments, the counter 402 can be configured to increment the count 408 of a countable element 404 representing time, such as every clock cycle of a clock or a derivative thereof, such as every rising or falling edge of a clock or some multiple of a clock cycle of a clock (e.g., every 2, 4, or 8 clock cycles, but not limited thereto).

[0061] In one or more embodiments, the slew rate measurement may be determined in response to a measurement (e.g., count 408, but not limited to) of the time between a lower signal threshold and an upper signal threshold (referred to herein as "rise time"), in response to the time between an upper signal threshold and a lower signal threshold (referred to herein as "fall time"), or in response to the time between states such as "above the upper signal threshold" and "below the lower signal threshold" as discussed above.

[0062] Where the slew rate is determined in response to the rise time, the start / stop logic 412 may be configured to generate a start signal in response to assertion of the signal state indication 220 and the threshold detection indication 218 corresponding to being below the lower signal threshold, and to generate a stop signal in response to assertion of the signal state indication 220 and the threshold detection indication 218 corresponding to being between the lower and upper thresholds and rising.

[0063] In the case of a fall time-based slew rate, the start / stop logic 412 may be configured to generate a start signal in response to de-assertion of the signal state indication 220 and the threshold detection indication 218 corresponding to being above the upper signal threshold, and to generate a stop signal in response to a second de-assertion (after an intermediate assertion of the threshold detection indication 218) of the signal state indication 220 and the threshold detection indication 218 corresponding to being between the lower and upper thresholds and falling.

[0064] In one or more embodiments, the start / stop logic 412 may be configured to generate the start / stop signal 406 in response to assertion / deassertion of the threshold detection indication 218 and the status indicated by the signal status indication 220, as discussed in Table 3:

[0065]

[0066] Table 3: Start / Stop signals based on signal status indication

[0067] In another embodiment, the start / stop logic 412 may be configured to generate the start / stop signal 406 in response to a detected change in the state indicated by the signal state indication 220, such as: "start" in response to a change from below a lower signal threshold to between the lower and upper signal thresholds and rising, "stop" in response to a change from between the lower and upper signal thresholds and rising to above the upper signal threshold, "start" in response to a change from above the upper signal threshold to between the lower and upper signal thresholds and falling, and "stop" in response to a change from between the lower and upper signal thresholds and falling to below the lower signal threshold.

[0068] Figure 4B is a block diagram illustrating a measurement circuit 400b according to one or more embodiments. Figure 2 , which optionally includes circuitry such that slew rate measurement 226 is a calculated value of the slew rate.

[0069] Elements of measurement circuit 400b having similar reference numbers as elements of measurement circuit 400a will not be described again. Measurement circuit 400b includes a slew rate calculator 414 that is configured to calculate a slew rate measurement 226 based on upper and lower threshold reference signals 222 and 224 and a count stored at slew rate count buffer 410.

[0070] Figure 4C is a block diagram illustrating a measurement circuit 400c according to one or more embodiments. Figure 2 2 , which optionally includes a rising edge indicator or a falling edge indicator 416 that can be used to indicate whether the slew rate measurement result 226 corresponds to a rising edge or a falling edge in response to the signal state indication 220. Elements of the measurement circuit 400c having similar reference numbers as elements of the measurement circuit 400a will not be described again.

[0071] Those skilled in the art will appreciate that many changes or additions may be made to the measurement circuits 400a, 400b, and 400c. Counter 402 and measurement circuits 400a, 400b, and 400c may include logic blocks other than those depicted without exceeding the scope of this disclosure. As non-limiting examples, calibration may be performed to adjust the count, average the count (i.e., provide an average slew rate value for multiple signal edges (e.g., multiple falling edges, multiple rising edges, or multiple rising and falling edges, but not limited thereto) in addition to or as an alternative to the absolute slew rate value), or perform other processing, and counter 402 and measurement circuits 400a, 400b, or 400c may optionally be configured to perform the processing.

[0072] Although the slew rate measurement results have been specifically described Figures 4A to 4C The present invention relates to a circuit, but this is not intended to be limiting in any way. Any measurement can be performed, including measurement of a periodic signal that varies substantially monotonically to rise above and fall below upper and lower signal thresholds. For example, the frequency of such a periodic signal can be measured by starting and stopping counter 402 as described above and determining the frequency based on the clock frequency of the input clock to counter 402.

[0073] Figure 5is a flow chart depicting a process 500 for determining a slew rate of an observation signal according to one or more embodiments. As a non-limiting example, the process 500 may be performed by the autonomous sensor 102 and the autonomous sensor 200.

[0074] At operation 502, process 500 provides a first reference signal in response to a first state of an observation signal. The observation signal can be a discrete signal. The first state can be one of the states indicated by signal state indication 220 discussed herein. The signal level of the first reference signal corresponds to a value of a first signal threshold (e.g., stored in upper signal threshold register 204 or lower signal threshold register 206, respectively, but not limited thereto). The first signal threshold, and therefore the first reference signal, can be selected in response to the first state.

[0075] At operation 504, process 500 observes a first relationship between a first signal level of the observation signal and a signal level of a first reference signal. In one or more embodiments, the first relationship can be that the first signal level is greater than or less than the signal level of the first reference signal.

[0076] At operation 506, process 500 provides a second reference signal in response to the second state of the observation signal. The signal level of the second reference signal corresponds to the value of a second signal threshold (e.g., but not limited to, stored in upper signal threshold register 204 or lower signal threshold register 206, respectively).

[0077] At operation 508, process 500 observes a second relationship between a second signal level of the observation signal and a signal level of the second reference signal. In one or more embodiments, the second relationship can be that the first signal level is greater than or less than the signal level of the second reference signal.

[0078] In operations 504 and 508, process 500 observes whether the first signal level of the observation signal is greater than or less than the signal level of the first reference signal in response to the state of the observation signal. If the state corresponds to a rising signal (i.e., a signal having a generally increasing amplitude), process 500 observes that the signal level of the observation signal is greater than the signal level of the reference signal. If the state corresponds to a falling signal (i.e., a signal having a generally decreasing amplitude), process 500 observes that the signal level of the observation signal is less than the signal level of the reference signal.

[0079] At operation 510, process 500 stores a slew rate measurement of the observation signal in response to a transition time between observing a first relationship between a first signal level of the observation signal and a signal level of a first reference signal and observing a second relationship between a second signal level of the observation signal and a signal level of a second reference signal. In various implementations, the slew rate measurement can be a direct measurement of the time it takes the observation signal to transition between the first signal level and the second signal level, or a more robust calculation.

[0080] Figure 6 is a flow chart of a process 600 for controlling signal status indication, for example, by the status detection circuit 214 .

[0081] At operation 602 , process 600 optionally detects an initial state of an observation signal as discussed herein.

[0082] At operation 604, process 600 determines a state of the observation signal in response to a previous state of the observation signal and an indication of a relationship between a signal level of the observation signal and a signal threshold. The relationship may be whether the signal level of the observation signal is greater than or less than the signal threshold.

[0083] At operation 606, process 600 provides a signal status indication associated with the observation signal in response to the determined status of the observation signal. Each provided value of the signal status indication corresponds to one of: below a lower signal threshold, above an upper signal threshold, between the lower signal threshold and the upper signal threshold and rising (e.g., a rising edge of a signal having a signal level between the specified thresholds, but not limited thereto), and between the lower signal threshold and the upper signal threshold and falling (e.g., a falling edge of a signal having a signal level between the specified thresholds, but not limited thereto).

[0084] Those skilled in the art will appreciate that the functional elements of the embodiments disclosed herein (e.g., functions, operations, actions, processes and / or methods, but not limited thereto) may be implemented in any suitable hardware, software, firmware, or a combination thereof. Figure 7 Non-limiting examples of implementations of the functional elements disclosed herein are shown.In some embodiments, some or all of the functional elements disclosed herein may be performed by hardware specifically configured to perform these functional elements.

[0085] Figure 7700 is a block diagram of a circuit 700 that, in some embodiments, can be used to implement the various functions, operations, actions, processes, and / or methods disclosed herein. The circuit 700 includes one or more processors 702 (sometimes referred to herein as "processors 702") operably coupled to one or more data storage devices (sometimes referred to herein as "storage devices 704"). The storage devices 704 include machine-executable code 706 stored thereon, and the processor 702 includes logic circuitry 708. The machine-executable code 706 includes information describing functional elements that can be implemented (e.g., executed) by the logic circuitry 708. The logic circuitry 708 is suitable for implementing (e.g., executing) the functional elements described by the machine-executable code 706. When executing the functional elements described by the machine-executable code 706, the circuit 700 should be considered to be dedicated hardware configured to implement the functional elements disclosed herein. In some embodiments, the processor 702 can be configured to execute the functional elements described by the machine-executable code 706 sequentially, simultaneously (e.g., on one or more different hardware platforms), or in one or more parallel process flows.

[0086] When implemented by the logic circuitry 708 of the processor 702, the machine executable code 706 is configured to adapt the processor 702 to perform the operations of the embodiments disclosed herein. For example, the machine executable code 706 can be configured to adapt the processor 702 to perform at least some or all of the features and functions discussed with reference to the signal transmission system 100, the autonomous sensor 200, the analog signal threshold detection circuit 300, or the measurement circuits 400a, 400b, and 400c. As a specific non-limiting example, the machine executable code 706 can be configured to adapt the processor 702 to perform at least some of the analog signal threshold detection and slew rate measurement functions discussed herein, including, for example, Figure 5 The process of 500 and Figure 6 As a specific non-limiting example, the machine executable code 706 may be configured to adapt the processor 702 to perform at least a portion of the logic discussed with respect to Tables 1, 2, and 3.

[0087] The processor 702 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. When a general-purpose computer including a processor is configured to execute functional elements corresponding to machine executable code 706 (e.g., software code, firmware code, hardware code) associated with the embodiments of the present disclosure, the general-purpose computer is considered a special-purpose computer. It should be noted that the general-purpose processor (also referred to herein as a host processor or simply host) can be a microprocessor, but in the alternative, the processor 702 can include any conventional processor, controller, microcontroller, or state machine. The processor 702 can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0088] In some embodiments, the storage device 704 includes a volatile data storage device (e.g., random access memory (RAM)), a non-volatile data storage device (e.g., but not limited to, a flash memory, a hard disk drive, a solid-state drive, an erasable programmable read-only memory (EPROM)). In some embodiments, the processor 702 and the storage device 704 may be implemented as a single device (e.g., a semiconductor device product, a system on a chip (SoC), but not limited thereto). In some embodiments, the processor 702 and the storage device 704 may be implemented as separate devices.

[0089] In some embodiments, machine executable code 706 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored by storage device 704, directly accessed by processor 702, and executed by processor 702 using at least logic circuitry 708. Also as a non-limiting example, the computer-readable instructions may be stored on storage device 704, transferred to a memory device (not shown) for execution, and executed by processor 702 using at least logic circuitry 708. Thus, in some embodiments, logic circuitry 708 includes logic circuitry 708 that is electrically configurable.

[0090] In some embodiments, machine executable code 706 may describe hardware (e.g., circuitry) to be implemented in logic circuit 708 to perform a functional element. The hardware may be described at any of a variety of abstraction levels, from low-level transistor layouts to high-level description languages. At a high level of abstraction, a hardware description language (HDL) such as an IEEE standard hardware description language (HDL) may be used. As a non-limiting example, VERILOG may be used. TM 、SYSTEMVERILOG TM or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL™).

[0091] The HDL description may be converted into descriptions at any of a variety of other levels of abstraction as desired. As non-limiting examples, the high-level description may be converted into a logic-level description such as a register transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As non-limiting examples, micro-operations to be performed by hardware logic circuits (e.g., gates, flip-flops, registers, but not limited thereto) of logic circuit 708 may be described in RTL and then converted to a GL description by a synthesis tool, and the GL description may be converted to a layout-level description by a placement and routing tool that corresponds to the physical layout of an integrated circuit, discrete gate or transistor logic components, discrete hardware components, or a combination thereof of a programmable logic device. Thus, in some embodiments, the machine executable code 706 may include an HDL, RTL, GL description, a mask-level description, other hardware description, or any combination thereof.

[0092] In embodiments where the machine executable code 706 includes a hardware description (at any level of abstraction), a system (not shown, but including the storage device 704) can be configured to implement the hardware description described by the machine executable code 706. As a non-limiting example, the processor 702 can include a programmable logic device (e.g., an FPGA or a PLC), and the logic circuit 708 can be electrically controlled to implement circuitry corresponding to the hardware description into the logic circuit 708. Also as a non-limiting example, the logic circuit 708 can include hard-wired logic components that are manufactured by a manufacturing system (not shown, but including the storage device 704) according to the hardware description of the machine executable code 706. Such fabrication of hard-wired logic components can also be characterized herein as permanently configuring the logic circuitry of the processor.

[0093] Regardless of whether the machine-executable code 706 includes computer-readable instructions or a hardware description, the logic circuit 708 is adapted to perform the functional elements described by the machine-executable code 706 when implementing the functional elements of the machine-executable code 706. It should be noted that although the hardware description may not directly describe the functional elements, the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description are capable of performing.

[0094] Those skilled in the art will recognize additional embodiments and advantages from the disclosure in Appendix A herein, the entire contents and disclosure of which are incorporated herein by reference.

[0095] As used in this disclosure, the term "combination" referring to multiple elements may include all of the elements in combination or any of various subcombinations of certain elements. For example, the phrase "A, B, C, D or a combination thereof" may refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0096] The terms used in this disclosure and in particular in the appended claims (e.g., the bodies of the appended claims, etc.) are generally intended to be "open-ended" terms (e.g., the term "including" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," the term "includes" should be interpreted as "including but not limited to," etc.). As used herein, the term "each" means some or all. As used herein, the term "each" means all.

[0097] In addition, if a specific number of introduced claim recitations is intended, such intent will be expressly recited in the claim, and in the absence of such recitation, no such intent is present. For example, as an aid to understanding, the following appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that a claim recitation introduced by the indefinite article "a" or "an" limits any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "an" (e.g., "a" and / or "an" may be interpreted to mean "at least one" or "one or more," but are not limited thereto); the same is true when a definite article is used to introduce a claim recitation.

[0098] In addition, even if a specific number of an introduced claim recitation is explicitly recited, one skilled in the art will recognize that such recitation should be interpreted as intending at least the recited number (e.g., the unmodified recitation "two recitations" without other modifiers intends at least two recitations, or two or more recitations, but is not limited thereto). Moreover, in those instances where a convention similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, such construction is generally intended to include only A, only B, only C, both A and B, both A and C, both B and C, or all three of A, B, and C, etc.

[0099] Furthermore, any discrete word or phrase presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to include the possibility of one, either, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B."

[0100] Additional non-limiting embodiments of the present disclosure include:

[0101] Embodiment 1: A sensor comprises: a state detection circuit, the state detection circuit being configured to generate a signal state indication regarding the state of an observation signal; an analog signal threshold detection circuit, the analog signal threshold detection circuit being configured to alternately assert and de-assert a threshold detection indication in response to the observation signal and the signal state indication; and a measurement circuit, the measurement circuit being configured to generate a measurement result in response to assertion and de-assertion of the threshold detection indication and the signal state indication.

[0102] Embodiment 2: The sensor of Embodiment 1, wherein the state detection circuit is configured to generate the signal state indication in response to assertion and deassertion of the threshold detection indication and a previous state of the observation signal.

[0103] Embodiment 3: A sensor according to any one of embodiments 1 and 2, wherein the analog signal threshold detection circuit includes an analog signal threshold detector, and the analog signal threshold detector is configured to: assert the threshold detection indication in response to a first relationship between a fixed-level reference signal and the observation signal; and de-assert the threshold detection indication in response to a second relationship between the fixed-level reference signal and the observation signal.

[0104] Embodiment 4: A sensor according to any one of Embodiments 1 to 3, wherein the analog signal threshold detection circuit includes threshold selection logic, and the threshold selection logic is configured to alternately select an upper threshold reference signal or a lower threshold reference signal for the fixed level reference signal in response to the signal state indication.

[0105] Embodiment 5: A sensor according to any one of Embodiments 1 to 4, wherein the analog signal threshold detection circuit includes a signal selection circuit, and the signal selection circuit is configured to provide the fixed level reference signal in response to a selected upper threshold reference signal or a lower threshold reference signal.

[0106] Embodiment 6: A sensor according to any one of Embodiments 1 to 5, wherein the measurement circuit includes: start / stop logic, which is configured to alternately generate a start signal or a stop signal in response to the threshold detection indication and the signal status indication; and a counter, which is configured to count upward during a time period defined between the generated start signal and the generated stop signal.

[0107] Embodiment 7: The sensor of any one of Embodiments 1 to 6, wherein the counter is configured to increment the count in response to a countable element, the countable element comprising one of: a clock cycle, a rising edge of a clock, or a falling edge of a clock.

[0108] Embodiment 8: The sensor of any one of Embodiments 1 to 7, wherein the measurement is one of counts, slew rate, or frequency.

[0109] Embodiment 9: The sensor of any one of Embodiments 1 to 8, wherein the measurement circuit comprises a rising edge indicator or a falling edge indicator.

[0110] Embodiment 10: The sensor of any one of Embodiments 1 to 9, further comprising an upper signal threshold register and a lower signal threshold register.

[0111] Embodiment 11: The sensor of Embodiments 1 to 10, wherein the upper signal threshold register and the lower signal threshold register are each coupled to the analog signal threshold detection circuit.

[0112] Embodiment 12: The sensor according to any one of Embodiments 1 to 11, further comprising a measurement register.

[0113] Embodiment 13: The sensor of Embodiments 1 to 12, wherein the measurement register is coupled to the measurement circuit.

[0114] Embodiment 14: A method comprising: providing a first reference signal in response to a first state of an observation signal; observing a first relationship between a first signal level of the observation signal and a signal level of the first reference signal; providing a second reference signal in response to a second state of the observation signal; observing a second relationship between a second signal level of the observation signal and a signal level of the second reference signal; and storing a measurement result of the observation signal in response to observing a transition time between the first relationship and the second relationship.

[0115] Embodiment 15: The method of embodiment 14, wherein the observed signal is a discrete signal.

[0116] Embodiment 16: The method of any one of Embodiments 14 and 15, wherein providing the first reference signal and the second reference signal comprises providing a first fixed-level reference signal and a second fixed-level reference signal, respectively.

[0117] Embodiment 17: The method according to any one of Embodiments 14 to 16 further includes: determining the state of the observation signal in response to a previous state of the observation signal and an indication of the relationship between the signal level of the observation signal and a signal threshold; and providing a signal state indication associated with the observation signal in response to the determined state of the observation signal.

[0118] Embodiment 18: The method according to any one of Embodiments 14 to 17 further includes detecting an initial state of the observation signal.

[0119] Embodiment 19: The method according to any one of Embodiments 14 to 18 further includes receiving the value of the signal threshold.

[0120] Embodiment 20: A computing system comprising: a processor; and a memory storage device having machine executable code thereon, the machine executable code being suitable for permanently configuring the logic circuit of the processor to: provide a first reference signal in response to a first state of an observation signal; observe a first relationship between a first signal level of the observation signal and a signal level of the first reference signal; provide a second reference signal in response to a second state of the observation signal; observe a second relationship between a second signal level of the observation signal and a signal level of the second reference signal; and store a measurement result of the observation signal in response to observing a transition time between the first relationship and the second relationship.

[0121] A computing system according to embodiment 20, configured to perform according to any one of embodiments 1 to 19.

[0122] The present invention is described herein with respect to certain illustrative embodiments, but those skilled in the art will recognize and understand that the invention is not so limited. Rather, many additions, deletions, and modifications may be made to the illustrated and described embodiments without departing from the scope of the invention as claimed below and its legal equivalents. Furthermore, features from one embodiment may be combined with features from another embodiment while still being included within the scope of the invention as contemplated by the inventors.

Claims

1. A sensor comprising: a state detection circuit configured to generate a signal state indication regarding a state of the observation signal; an analog signal threshold detection circuit configured to alternately assert and de-assert a threshold detection indication in response to the observation signal and the signal state indication; and a measurement circuit configured to generate a measurement result in response to assertion and de-assertion of the threshold detection indication and the signal state indication, The measuring circuit comprises: start / stop logic configured to alternately generate a start signal or a stop signal in response to the threshold detection indication and the signal status indication; and A counter is configured to count up during a time defined between the generated start signal and the generated stop signal. 2 . The sensor of claim 1 , wherein the state detection circuit is configured to generate the signal state indication in response to assertion and de-assertion of the threshold detect indication and a previous state of the observation signal.

3. The sensor according to claim 1 , wherein the analog signal threshold detection circuit comprises an analog signal threshold detector configured to: asserting the threshold detect indication in response to a first relationship between a fixed-level reference signal and the observation signal; and The threshold detect indication is de-asserted in response to a second relationship between the fixed-level reference signal and the observation signal.

4. The sensor of claim 3 , wherein the analog signal threshold detection circuit comprises threshold selection logic configured to alternately select an upper threshold reference signal or a lower threshold reference signal for the fixed level reference signal in response to the signal state indication. 5 . The sensor of claim 4 , wherein the analog signal threshold detection circuit comprises a signal selection circuit configured to provide the fixed-level reference signal in response to a selected upper threshold reference signal or a lower threshold reference signal. 6 . The sensor of claim 1 , wherein the counter is configured to increment the count in response to a countable element, the countable element comprising one of: a clock cycle, a rising edge of a clock, or a falling edge of a clock. The sensor of claim 1 , wherein the measurement is one of counts, slew rate, or frequency. The sensor according to claim 1 , wherein the measurement circuit comprises a rising edge indicator or a falling edge indicator.

9. The sensor of claim 1, further comprising an upper signal threshold register and a lower signal threshold register. 10 . The sensor according to claim 9 , wherein the upper signal threshold register and the lower signal threshold register are respectively coupled to the analog signal threshold detection circuit. The sensor of claim 1 , further comprising a measurement register.

12. The sensor of claim 11, wherein the measurement register is coupled to the measurement circuit.

13. A method for determining a measurement result of an observation signal, comprising: providing a first reference signal in response to a first state of the observation signal; observing a first relationship between a first signal level of the observation signal and a signal level of the first reference signal; starting a counter in response to the state of the observation signal being the first state and observing the first relationship between a first signal level of the observation signal and a signal level of the first reference signal; providing a second reference signal in response to a second state of the observation signal; observing a second relationship between a second signal level of the observation signal and a signal level of the second reference signal; stopping the counter in response to the state of the observation signal being the second state and observing the second relationship between a second signal level of the observation signal and a signal level of the second reference signal; Responsive to observing a transition time between the first and second relationships as indicated by the value of the counter, a measurement of the observation signal is stored. The method according to claim 13 , wherein the observation signal is a discrete signal.

15. The method of claim 13, wherein providing the first reference signal and the second reference signal comprises providing a first fixed level reference signal and a second fixed level reference signal, respectively.

16. The method according to claim 13, further comprising: determining a state of the observation signal in response to a previous state of the observation signal and an indication of a relationship between a signal level of the observation signal and a signal threshold; and providing a signal status indication associated with the observation signal in response to the determined status of the observation signal. The method according to claim 16 , further comprising detecting an initial state of the observation signal. The method of claim 16 , further comprising receiving a value for the signal threshold.

19. A computing system comprising: processor; and a memory storage device having machine-executable code thereon, the machine-executable code being adapted to permanently configure the logic circuitry of the processor to: providing a first reference signal in response to a first state of the observation signal; observing a first relationship between a first signal level of the observation signal and a signal level of the first reference signal; starting a counter in response to the state of the observation signal being the first state and observing the first relationship between a first signal level of the observation signal and a signal level of the first reference signal; providing a second reference signal in response to a second state of the observation signal; observing a second relationship between a second signal level of the observation signal and a signal level of the second reference signal; stopping the counter in response to the state of the observation signal being the second state and observing the second relationship between a second signal level of the observation signal and a signal level of the second reference signal; Responsive to observing a transition time between the first and second relationships as indicated by the value of the counter, a measurement of the observation signal is stored.

Images