Automatic parallel testing method and system for electrical performance parameters of semiconductor devices

Abstract

The application provides a kind of semiconductor device electric performance parameter automatic parallel test method and system, the semiconductor device electric performance parameter automatic parallel test method includes: based on the test port in target analysis unit, the all-to-all combination discrimination of all devices to be tested in each target analysis unit is carried out, to obtain the parallel test group of several levels of corresponding target analysis unit, and there is no common test port between the devices to be tested in parallel test group.The application obtains the parallel test group of several levels of corresponding test unit by the all-to-all combination discrimination of all devices to be tested in each test unit, and there is no common test port between the devices to be tested in parallel test group, generates the new test file for the automatic parallel test of the devices to be tested of all test units, realizes the purpose of the electric performance parameter automatic parallel test of semiconductor device, reduces the difficulty of test operation, improves test efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit device testing technology, and in particular to a method and system for automatically and in parallel testing electrical performance parameters of semiconductor devices. BACKGROUND

[0002] Wafer Acceptance Test (WAT) is an important link to ensure that integrated circuit devices on a wafer meet the required performance and quality parameters, and is an indispensable part of the design, production and application of integrated circuit products, and has become one of the key technologies for ensuring the reliability of integrated circuit products. WAT testing mainly obtains the characteristics of the devices under test by testing a plurality of test keys distributed on the scribe lane. A WAT testing system mainly includes a host computer, a tester, a test head, a probe station and test probes. The probe station and test probes are special test connection devices introduced for the pins or pads of each device under test on the wafer. The test head serves as a connection bridge between the general-purpose test instrument and the test probes, and is used to establish each test channel between the general-purpose test instrument and the test probes and to perform excitation and signal conditioning.

[0003] In the prior art, the testing of semiconductor devices is mainly in a serial mode, i.e., the devices under test are tested one by one in sequence, so the testing time is long, which seriously restricts the testing efficiency.

[0004] Therefore, it is necessary to improve the method for measuring the electrical performance parameters of semiconductor devices in the prior art to solve the above problems. SUMMARY

[0005] The present application aims to disclose a method for automatically and in parallel testing the electrical performance parameters of semiconductor devices, which is used to solve the defects of the prior art and improve the testing efficiency.

[0006] To achieve one of the above objects, the present application provides a method for automatically and in parallel testing the electrical performance parameters of semiconductor devices, comprising:

[0007] Based on an initial test file, the structure information of all test units is obtained, each test unit including a plurality of devices under test and a plurality of test ports, the devices under test being connected to at least one test port, and the test ports being used to connect to a test system to test the electrical performance parameters of the devices under test;

[0008] Based on the structural information of the test unit, at least one target analysis unit is obtained, wherein the target analysis unit is the test unit including at least two of the devices under test;

[0009] Based on the test port in the target analysis unit, all the devices under test in each target analysis unit are combined and judged in pairs to obtain several levels of parallel test groups for the corresponding target analysis unit. The parallel test group includes at least two devices under test, and the devices under test in the parallel test group do not share the test port.

[0010] According to the hierarchical order of the parallel test groups of several levels of the target analysis unit, establish the parallel test order of the corresponding target analysis unit;

[0011] Based on the parallel testing sequence of each target analysis unit, a new test file is generated to automatically perform parallel testing on the device under test of all the test units.

[0012] As a further improvement of the present invention, the step of performing pairwise combination discrimination on all the devices under test in each target analysis unit based on the test port in the target analysis unit to obtain parallel test groups of several levels for the corresponding target analysis unit includes:

[0013] Obtain the test port information corresponding to each device under test in each target analysis unit;

[0014] For each target analysis unit, all the devices under test are divided into pairs at the first level to obtain... A combination unit, wherein m represents the number of devices under test in the target analysis unit;

[0015] Regarding the Each combined unit performs parallel testing and discrimination to obtain the first-level parallel test group of the corresponding target analysis unit.

[0016] As a further improvement of the present invention, the parallel test discrimination includes: comparing the test ports corresponding to the two devices under test in each of the combined units one by one, merging the devices under test of the combined units that do not share a test port into a parallel test group of the corresponding target analysis unit, and marking the devices under test of the combined units that share a test port as the successor devices under test of the corresponding target analysis unit.

[0017] As a further improvement of the present application, based on the test ports in the target analysis unit, the two-by-two combination discrimination is performed on all the DUTs in each target analysis unit to obtain parallel test groups of several levels of the corresponding target analysis unit, and the method further comprises:

[0018] Based on the remaining DUTs other than the first-level parallel test group in the target analysis unit, parallel test groups of N levels of the target analysis unit are obtained, where N is an integer greater than 1.

[0019] As a further improvement of the present application, based on the test ports in the target analysis unit, the two-by-two combination discrimination is performed on all the DUTs in each target analysis unit to obtain parallel test groups of several levels of the corresponding target analysis unit, and the method further comprises:

[0020] After the first-level parallel test group in the target analysis unit is removed, the remaining DUTs are further divided into several two-by-two combinations, wherein after each two-by-two combination division, the parallel test discrimination is performed to obtain the parallel test group of the corresponding level, and until the Nth-level parallel test group is obtained, there is no remaining DUT in the corresponding target analysis unit.

[0021] As a further improvement of the present application, based on the parallel test sequence of the target analysis unit, a new test file is generated to automatically perform parallel testing on all the DUTs of the test unit, and the method comprises:

[0022] Based on the initial test file, a sequential test sequence of all the test units on the DUT is obtained;

[0023] A new test file is generated in combination with the sequential test sequence and the parallel test sequence of the target analysis unit;

[0024] Based on the new test file, the parallel test is performed on the target analysis unit one by one.

[0025] As a further improvement of the present application, the DUTs include MOS devices, and the test ports include gate ports, source ports, drain ports, and substrate ports.

[0026] As a further improvement of the present application, based on the test ports in the target analysis unit, the two-by-two combination discrimination is performed on all the DUTs in each target analysis unit, and the test port connected to ground is excluded.

[0027] As a further improvement of the present application, based on the test ports in the target analysis unit, the two-by-two combination discrimination is performed on all the DUTs in each target analysis unit, and the test port applying 0V voltage is excluded.

[0028] Meanwhile, based on the same inventive concept, the application further provides a system for testing electrical performance parameters of semiconductor devices, comprising:

[0029] a file configuration module configured to initialize a test file, wherein the test file comprises setting a plurality of test units and a test sequence of the plurality of test units;

[0030] a judgment module configured to obtain at least one target analysis unit based on structure information of the plurality of test units, wherein the target analysis unit comprises the test units including at least two devices under test; based on the test ports in the target analysis unit, all the devices under test in each target analysis unit are pairwise combined and discriminated to obtain a plurality of levels of parallel test groups of the corresponding target analysis unit, wherein the parallel test group comprises at least two devices under test, and the devices under test in the parallel test group do not share the test ports; and a parallel test sequence of the corresponding target analysis unit is established according to the level sequence of the plurality of levels of parallel test groups of the target analysis unit;

[0031] a test module configured to generate a new test file based on the parallel test sequence of each target analysis unit to automatically and in parallel test the devices under test of all the test units.

[0032] Compared with the prior art, the application has the following beneficial effects:

[0033] The application provides an automatic parallel test method for electrical performance parameters of semiconductor devices, wherein all the devices under test in each test unit are pairwise combined and discriminated to obtain a plurality of levels of parallel test groups of the corresponding test unit, the devices under test in the parallel test group do not share the test ports, a parallel test sequence of the corresponding test unit is established according to the level sequence of the plurality of levels of parallel test groups of the test unit, and a new test file for automatically and in parallel testing the devices under test of all the test units is generated based on the parallel test sequence of each test unit, thereby achieving the purpose of automatically and in parallel testing the electrical performance parameters of semiconductor devices, reducing the difficulty of test operation, and improving the test efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A flowchart of the automatic parallel test method for electrical performance parameters of semiconductor devices of the application;

[0035] Figure 2 A schematic diagram of the plurality of test units contained in the initial test file of the application, wherein q is an integer greater than or equal to 1, f is an integer greater than or equal to 2, g is an integer greater than or equal to 2, and the values of f and g can be equal or not equal;

[0036] Figure 3 It is a schematic structural diagram of a device to be tested in a target analysis unit provided for an embodiment in the initial test file of the present invention;

[0037] Figure 4 It is a parallel test group of N levels of a target analysis unit of an embodiment of the present invention, where N is equal to 3, and in this target analysis unit, the remaining devices to be tested in sub - divisions are divided into pairs (N - 1 = 2 times);

[0038] Figure 5 It is a flowchart for the present invention to perform pairwise combination discrimination on all devices to be tested in each target analysis unit based on the test ports in the target analysis unit, so as to obtain parallel test groups of several levels of the corresponding target analysis unit;

[0039] Figure 6 It is a flowchart for the present invention to generate a new test file based on the parallel test order of the target analysis unit to perform automatic parallel testing on the devices to be tested in all test units;

[0040] Figure 7 It is a system diagram for testing the electrical performance parameters of a semiconductor device of the present invention. Specific embodiments

[0041] The present invention will be described in detail below in conjunction with the various embodiments shown in the accompanying drawings. However, it should be noted that these embodiments are not limitations on the present invention, and any equivalent transformation or substitution in terms of function, method, or structure made by those of ordinary skill in the art based on these embodiments shall fall within the protection scope of the present invention.

[0042] The method and system for automatically parallel testing the electrical performance parameters of semiconductor devices disclosed by the present invention aim to obtain a new test file for automatically parallel testing the devices to be tested in all test units, so as to achieve the purpose of automatically parallel testing the semiconductor devices to be tested and improve the testing efficiency of the electrical performance parameters of semiconductor devices.

[0043] The method for automatically parallel testing the electrical performance parameters of semiconductor devices disclosed in this embodiment uses a fully automatic, semi - automatic, and manual test system to test the devices to be tested. During testing, the test probes of the test system are connected to the test ports 110 or pins of the devices to be tested to test the electrical performance parameters of the devices to be tested.

[0044] Refer Figure 1 As shown, this embodiment discloses a method for automatically parallel testing the electrical performance parameters of semiconductor devices (hereinafter referred to as "the method"), which includes the following steps S1 to S5.

[0045] Step S1, based on the initial test file 10, obtaining the structure information of all test units, each test unit including a plurality of devices under test and a plurality of test ports 110, the device under test being connected with at least one test port 110, and the test port 110 being used for connecting the test system to test the electrical performance parameters of the device under test;

[0046] Specifically, referring to Figure 2 and Figure 3 As shown in the figure, the initial test file 10 is obtained from the test system, and the initial test file 10 includes the structure information and test condition information of a plurality of test units. Based on the initial test file 10, a plurality of test units are obtained: a first test unit 101, …, and a qth test unit 102, where q is greater than or equal to 1. Each test unit includes a first device under test 103, …, and an fth device under test 104, or each test unit includes a first device under test 103, …, and a gth device under test 105, where f and g are both integers greater than or equal to 2, and the values of f and g can be equal or not equal. Each device under test is connected with at least one test port 110, and each test unit further includes the position sequence of the test ports 110.

[0047] Wherein, the device under test can be a MOS device 120, and the MOS transistor is generally monitored by five test parameters. The five test parameters are threshold voltage V t , saturation current I dsat , drain current I off , breakdown voltage BVD, and substrate current I sub . Taking the measurement of threshold voltage Vt and saturation current I dsat as an example, when measuring the threshold voltage V t and the saturation current I dsat of the MOS transistor, the four test ports 110 of the MOS transistor need to be tested, including the gate (Gate, hereinafter referred to as “G”) port, the source (Source, hereinafter referred to as “S”) port, the drain (Drain, hereinafter referred to as “D”) port, and the bulk (Bulk, hereinafter referred to as “B”) port. The structure and the number of test ports 110 of each MOS device 120 and the position sequence of the test ports 110 can be obtained through the initial test file 10.

[0048] S2, based on the structure information of the test unit, obtaining at least one target analysis unit 100, the target analysis unit 100 being a test unit including at least two devices under test;

[0049] Specifically, referring to Figure 2 and Figure 3As shown, one test unit in the initial test file 10 can be selected as the target analysis unit 100, or two or more test units can be selected as the target analysis unit 100. For ease of illustration, one test unit is selected as the target analysis unit 100. Meanwhile, in the selected target analysis unit 100, two MOS devices 120 can be included, or three or more MOS devices 120 can be included, but the selected target analysis unit 100 must include at least two MOS devices 120 to perform combined discrimination on the MOS devices 120 in the target analysis unit 100.

[0050] For example, referring to FIG. 1, the initial test file 10 includes five test units, and each test unit includes four MOS devices 120. The target analysis unit 100 is selected from the initial test file 10, and the target analysis unit 100 includes five MOS devices 120. Figure 3 As shown, the threshold voltage V t and the saturation current I dsat of the MOS transistor are measured. For example, one test unit in the initial test file 10 is selected as the target analysis unit 100, and the target analysis unit 100 includes five MOS devices 120, and each MOS device 120 is connected to four test ports 110.

[0051] It should be noted that, for example, the threshold voltage V t and the saturation current I dsat of the MOS transistor are measured, and the MOS device 120 in the target analysis unit 100 is connected to four test ports 110. When other parameters of the MOS transistor are measured, such as when the integrity of the gate oxide layer of the MOS transistor is measured, the MOS transistor is only connected to two test ports 110. Therefore, when different MOS devices 120 are tested or different electrical performance parameters of the same MOS device 120 are tested, the number of test ports 110 connected to the MOS device 120 will be different. In addition, the number of MOS devices 120 that can be tested simultaneously in parallel by this method is only related to the process control monitor (PCM), and is not related to the test system performing the test.

[0052] In addition, for the NMOS transistor, a deep N-well (i.e., Deep N-Well, hereinafter referred to as "DNW") port is also included. When testing the device, the test of the deep N-well port can be omitted according to the requirements of the customer, or the deep N-well port needs to be tested when the customer requires improved performance testing of the product. Therefore, whether to test the deep N-well port should be selected according to the actual situation.

[0053] S3, based on the test ports 110 in the target analysis unit 100, all the DUTs in each target analysis unit 100 are combined in pairs to determine, to obtain a parallel test group of several levels of the corresponding target analysis unit 100, and the parallel test group includes at least two DUTs, and the DUTs in the parallel test group do not share the test ports 110;

[0054] Specifically, referring to Figure 3 to Figure 4 As shown in the foregoing, based on the test ports 110 in the target analysis unit 100, all the MOS devices 120 in each target analysis unit 100 are combined in pairs to determine, to obtain a parallel test group of several levels of the corresponding target analysis unit 100, including the following steps S21 to S23:

[0055] S21, obtaining the test port 110 information corresponding to each DUT in each target analysis unit 100;

[0056] Specifically, taking Figure 3 The target analysis unit 100 as an example for illustration. The target analysis unit 100 includes five MOS devices 120, each of which corresponds to a structure, and the five MOS devices 120 correspond to structure 1, structure 2, structure 3, structure 4, and structure 5, respectively. The position order of the four test ports 110 in structure 1 is 1, 2, 3, and 4, respectively, and is marked as P1, P2, P3, and P4. Similarly, the position order of the four test ports 110 in structure 2 is P1, P5, P6, and P7; the position order of the four test ports 110 in structure 3 is P8, P9, P11, and P10; the position order of the four test ports 110 in structure 4 is P1, P12, P13, and P14; and the position order of the four test ports 110 in structure 5 is P10, P15, P16, and P18.

[0057] S22, combining in pairs all the DUTs in each target analysis unit 100 to determine the first level 130, to obtain combinatorial units, where m represents the number of DUTs in the target analysis unit 100;

[0058] Exemplarily, also taking Figure 3 The target analysis unit 100 as an example for illustration. Since the target analysis unit 100 includes five MOS devices 120, the five MOS devices 120 are combined in pairs to determine the first level 130, to obtain combinatorial units, where m is equal to 5, That is, 10 combination units of the first level 130 are obtained. The 10 combination units are structure 1 and structure 2, structure 1 and structure 3, structure 1 and structure 4, structure 1 and structure 5, structure 2 and structure 3, structure 2 and structure 4, structure 2 and structure 5, structure 3 and structure 4, structure 3 and structure 5, and structure 4 and structure 5, respectively.

[0059] S23, parallel test discrimination is performed on each of the 10 combination units to obtain a parallel test group of the first level 130 of the corresponding target analysis unit 100.

[0060] Specifically, the parallel test discrimination includes: comparing the test ports 110 corresponding to the two MOS devices 120 in each combination unit one by one, merging the MOS devices 120 of the combination units without common test ports 110 into a parallel test group of the corresponding target analysis unit 100, and marking the MOS devices 120 of the combination units with common test ports 110 as to-be-tested devices of the corresponding target analysis unit 100.

[0061] For example, as shown in FIG. 2, in order to obtain the parallel test group of the first level 130 of the target analysis unit 100, the test ports 110 corresponding to the two MOS devices 120 in each combination unit are compared one by one based on the 10 combination units, and it is found that structure 1 and structure 2 and structure 1 and structure 4 have common test ports 110 (i.e., P1), respectively, while structure 1, structure 3, and structure 5 do not have common test ports 110. However, since structure 3 and structure 5 have common test ports 110 (i.e., P10), the two MOS devices 120 corresponding to structure 1 and structure 3 can be merged into the parallel test group of the first level 130 of the target analysis unit 100, and the MOS devices 120 corresponding to structure 2, structure 4, and structure 5 are marked as to-be-tested devices. Figure 3 Figure 4 As shown in FIG. 2, in order to obtain the parallel test group of the first level 130 of the target analysis unit 100, the test ports 110 corresponding to the two MOS devices 120 in each combination unit are compared one by one based on the 10 combination units, and it is found that structure 1 and structure 2 and structure 1 and structure 4 have common test ports 110 (i.e., P1), respectively, while structure 1, structure 3, and structure 5 do not have common test ports 110. However, since structure 3 and structure 5 have common test ports 110 (i.e., P10), the two MOS devices 120 corresponding to structure 1 and structure 3 can be merged into the parallel test group of the first level 130 of the target analysis unit 100, and the MOS devices 120 corresponding to structure 2, structure 4, and structure 5 are marked as to-be-tested devices.

[0062] In addition, for MOS transistors, since the test port 110 grounded (i.e., the B test port) and the test port 110 with a voltage of 0V applied can share the test port 110, the parallel test judgment is not performed on the test port 110 grounded and the test port 110 with a voltage of 0V applied. For example, when the test parameters in structure 1 are Vd=V1, Vb=0, Vs=0, and Vg=V2, where V1 and V2 are not equal to 0, only the parallel test judgment comparison of the D port and the G port needs to be performed, and the parallel test judgment comparison of the B port and the S port can be omitted.

[0063] ​​Further, based on the test ports 110 in the target analysis unit 100, all DUTs in each target analysis unit 100 are combined in pairs to determine, to obtain parallel test groups of several levels of the corresponding target analysis unit 100, and further includes: based on the remaining DUTs other than the parallel test group of the first level 130 in the target analysis unit 100, obtaining parallel test groups of N levels of the target analysis unit 100, N is an integer greater than 1. Illustratively, after removing the parallel test group of the first level 130 in the target analysis unit 100, the remaining DUTs are again divided into several times of combination in pairs, wherein after each combination in pairs, parallel test determination is performed to obtain the parallel test group of the corresponding level, and after obtaining the parallel test group of the Nth level, there is no remaining DUT in the corresponding target analysis unit 100.

[0064] Specifically, continuing to refer to Figure 3 and Figure 4 As shown, after removing the MOS devices 120 corresponding to the structures 1 and 3 in the parallel test group of the first level 130 in the target analysis unit 100, the remaining structures 2, 4 and 5 in the target analysis unit 100 are again divided into combination in pairs, and C3 2= 3 second-level 140 combination units, based on which the three second-level 140 combination units, each of which has two MOS devices 120 corresponding to the test ports 110, find that structure 2 and structure 4 have a common test port 110 (i.e., P1), while structure 2 and structure 5 have no common test port 110, so the MOS devices 120 corresponding to structure 2 and structure 5 are merged into a parallel test group of the second level 140 in the target analysis unit 100, and structure 4 is marked as a remaining MOS device 120. Since the target analysis unit 100 only has the MOS device 120 corresponding to structure 4, i.e., structure 4 is taken as a parallel test group of the third level 150. After obtaining the parallel test group of the third level 150, there is no remaining MOS device 120 in the corresponding target analysis unit 100. At this point, all MOS devices 120 in the target analysis unit 100 have completed the parallel test judgment. In this target analysis unit 100, N is equal to 3. And the remaining MOS device 120 in the target analysis unit 100 is divided into N-1 = 2 times of two-by-two combination. In other embodiments, after obtaining the parallel test group of the first level 130, there may be several remaining MOS devices 120, and there are common test ports 110 between the several remaining MOS devices 120. Therefore, each remaining MOS device 120 is taken as a parallel test group of a level to complete the parallel test judgment. In addition, in other embodiments, after obtaining the parallel test group of the first level 130, there may be several remaining MOS devices 120, and the several remaining MOS devices 120 include some MOS devices 120 with common test ports 110 and some MOS devices 120 without common test ports 110. Therefore, the remaining MOS devices 120 in the target analysis unit 100 can be divided into N-2 times or N-3 times of two-by-two combination, where N is a natural number greater than 1. It should be noted that this embodiment is only for the convenience of description, and the target analysis unit 100 includes five devices to be tested, but in actual testing, the target analysis unit 100 includes more or less than five devices to be tested, and the specific number is not limited.

[0065] S4, according to the level order of the parallel test groups of several levels of the target analysis unit 100, establishing the parallel test order of the corresponding target analysis unit 100;

[0066] Specifically, continuing to refer to Figure 3 and Figure 4As shown, for the target analysis unit 100, there are three levels, the first level 130 includes a parallel test group composed of MOS devices 120 corresponding to structure 1 and structure 3, the second level 140 includes a parallel test group composed of MOS devices 120 corresponding to structure 2 and structure 4, and the third level 150 includes a parallel test group composed of MOS devices 120 corresponding to structure 4. According to the level order of the parallel test groups, the parallel test sequence of the target analysis unit 100 is established as shown in Figure 4

[0067] S5, based on the parallel test sequence of each target analysis unit 100, a new test file is generated to automatically perform parallel test on the devices to be tested of all test units.

[0068] Specifically, referring to the parallel test sequence of the target analysis unit 100, the new test file is generated to automatically perform parallel test on the MOS devices 120 of all test units, including the following steps S61 to S63. Figure 2 to Figure 6

[0069] S61, based on the initial test file 10, the sequential test sequence of all test units on the sample to be tested is obtained;

[0070] Specifically, referring to the parallel test sequence of the target analysis unit 100, the new test file is generated to automatically perform parallel test on the MOS devices 120 of all test units, including the following steps S61 to S63. Figure 3 Figure 4 As shown, the sample to be tested includes semiconductor devices containing MOS devices 120. Based on the initial test file 10, the sequential test sequence of several test units is obtained as shown in Figure 2

[0071] S62, the new test file is generated in combination with the sequential test sequence and the parallel test sequence of the target analysis unit 100;

[0072] Specifically, based on the method of generating the parallel test sequence of the initial test sequence of the target analysis unit 100, the parallel test sequence of all test units in the initial test file 10 is generated, and the test units of all parallel test sequences are generated into a new test file.

[0073] S63, based on the new test file, the parallel test is performed on the target analysis unit 100 one by one.

[0074] Specifically, using the new test file in step S62, the parallel test is performed one by one according to the parallel test sequence in the target analysis unit 100, that is, the new test file is used to automatically perform parallel test on the electrical performance parameters of the sample to be tested, achieving the purpose of automatic parallel test of the electrical performance parameters of the semiconductor devices, reducing the difficulty of test operation and improving the test efficiency.

[0075] Based on the method disclosed in the foregoing embodiments, referring to​​​​Figure 7 As shown, the embodiment also discloses a system for testing electrical performance parameters of a semiconductor device (hereinafter referred to as "the system"), which comprises: a file configuration module 201; a judgment module 202; and a test module 203.

[0076] The file configuration module 201 is configured to initialize a test file, and the initialization of the test file comprises setting a plurality of test units and a test sequence of the plurality of test units.

[0077] Specifically, in combination with Figure 2 As shown, the file configuration module 201 initializes the test file, which comprises configuring structure information and test condition information of a plurality of test units, including a test sequence of the first test unit 101 to the qth test unit 102, an electrical signal applied to each test unit, and the like, wherein q is an integer greater than or equal to 1.

[0078] The judgment module 202 is configured to obtain at least one target analysis unit 100 based on the structure information of the plurality of test units, the target analysis unit 100 being a test unit comprising at least two MOS devices 120; to perform pairwise combination discrimination on all MOS devices 120 in each target analysis unit 100 based on the test ports 110 in the target analysis unit 100, so as to obtain a plurality of levels of parallel test groups of the corresponding target analysis unit 100, the parallel test group comprising at least the MOS device 120, and the MOS devices 120 in the parallel test group having no common test port 110; and to establish a parallel test sequence of the corresponding target analysis unit 100 according to the level order of the plurality of levels of parallel test groups of the target analysis unit 100.

[0079] Specifically, in combination with Figure 2 to Figure 4 As shown, for the test sequence initially set for the target analysis unit 100 in the initial test file 10, the pairwise combination discrimination is performed on all MOS devices 120 in each target analysis unit 100 according to the method described above, so as to obtain a plurality of levels of parallel test groups of the corresponding target analysis unit 100, and a parallel test sequence of the corresponding target analysis unit 100 is established according to the level order of the plurality of levels of parallel test groups of the target analysis unit 100.

[0080] The test module 203 is configured to generate a new test file based on the parallel test sequence of each target analysis unit 100, so as to automatically perform parallel testing on the MOS devices 120 of all test units.

[0081] Specifically, based on the parallel test sequence of the target analysis unit 100, the parallel test sequence of each test unit in the initial test file 10 is established, and all the test units with the re-established parallel test sequence are generated into a new test file to automatically perform parallel test on the MOS device 120, so as to achieve the purpose of automatically performing parallel test on the electrical performance parameters of the semiconductor device, reduce the difficulty of test operation, and improve the test efficiency.

[0082] The above series of detailed descriptions are only specific descriptions of the feasible embodiments of the present application, and are not intended to limit the protection scope of the present application. Any equivalent embodiments or changes made without departing from the spirit of the present application shall be included in the protection scope of the present application.

[0083] It is obvious for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be regarded as exemplary and non-limiting, and the scope of the present application is defined by the appended claims rather than the above description, and all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present application. Any reference signs in the claims should not be regarded as limiting the claims involved.

[0084] In addition, it should be understood that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description manner of the specification is only for the sake of clarity, and those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be properly combined to form other embodiments that those skilled in the art can understand.

Claims

1. An automatic parallel testing method for the electrical performance parameters of semiconductor devices, characterized in that, include: Based on the initial test file, obtain the structural information of all test units. Each test unit includes several devices under test and several test ports. The devices under test are connected to at least one of the test ports. The test ports are also used to connect to the test system to test the electrical performance parameters of the devices under test. Based on the structural information of the test unit, at least one target analysis unit is obtained, wherein the target analysis unit is the test unit including at least two of the devices under test; Based on the test port in the target analysis unit, all the devices under test in each target analysis unit are combined and judged in pairs to obtain several levels of parallel test groups for the corresponding target analysis unit. The parallel test group includes at least two devices under test, and the devices under test in the parallel test group do not share the test port. According to the hierarchical order of the parallel test groups of several levels of the target analysis unit, establish the parallel test order of the corresponding target analysis unit; Based on the parallel testing sequence of each target analysis unit, a new test file is generated to automatically perform parallel testing on the device under test of all the test units.

2. The method according to claim 1, characterized in that, Based on the test ports in the target analysis unit, pairwise combination discrimination is performed on all the devices under test in each target analysis unit to obtain parallel test groups at several levels for the corresponding target analysis unit, including: Obtain the test port information corresponding to each device under test in each target analysis unit; For each target analysis unit, all the devices under test are divided into pairs at the first level to obtain... A combination unit, wherein m represents the number of devices under test in the target analysis unit; Regarding the Each combined unit performs parallel testing and discrimination to obtain the first-level parallel test group of the corresponding target analysis unit.

3. The method according to claim 2, characterized in that, The parallel test discrimination includes: comparing the test ports corresponding to the two devices under test in each of the combined units one by one; merging the devices under test of the combined units that do not share test ports into a parallel test group of the corresponding target analysis unit; and marking the devices under test of the combined units that share test ports as the successor devices under test of the corresponding target analysis unit.

4. The method according to claim 3, characterized in that, The method of performing pairwise combination discrimination on all the devices under test in each target analysis unit based on the test port in the target analysis unit to obtain parallel test groups of several levels for the corresponding target analysis unit also includes: Based on the devices under test (DUTs) outside the first-level parallel test group in the target analysis unit, N levels of parallel test groups of the target analysis unit are obtained, where N is an integer greater than 1.

5. The method according to claim 4, characterized in that, The step of obtaining N levels of parallel test groups for the target analysis unit based on the device under test (DUT) outside the first-level parallel test group in the target analysis unit includes: After removing the first-level parallel test group from the target analysis unit, the remaining devices under test are further divided into pairs several times. Each time the pairwise division is performed, the parallel test discrimination is performed to obtain the corresponding level of the parallel test group, until the Nth level of parallel test group is obtained, at which point the device under test does not exist in the corresponding target analysis unit.

6. The method according to any one of claims 1-5, characterized in that, The process of generating new test files based on the parallel test sequence of the target analysis unit to automatically perform parallel testing on the device under test for all the test units includes: Based on the initial test file, obtain the successive test order of all the test units on the sample under test; A new test file is generated by combining the sequential test order and the parallel test order of the target analysis unit; Based on the new test file, the parallel test is performed on each of the target analysis units.

7. The method according to claim 6, characterized in that, The device under test includes a MOS device, and the test ports include a gate port, a source port, a drain port, and a substrate port.

8. The method according to claim 7, characterized in that, Based on the test ports in the target analysis unit, the devices under test in each target analysis unit are combined and judged in pairs, excluding the test ports that are grounded.

9. The method according to claim 7, characterized in that, Based on the test ports in the target analysis unit, all the devices under test in each target analysis unit are combined and judged in pairs, excluding the test ports where a 0V voltage is applied.

10. A system for testing the electrical performance parameters of a semiconductor device, characterized in that, include: The file configuration module is used to initialize the test file, which includes setting several test units and the test order of the several test units; The judgment module is used to obtain at least one target analysis unit based on the structural information of the plurality of test units, wherein the target analysis unit is the test unit including at least two of the devices under test; Based on the test ports in the target analysis unit, all the devices under test in each target analysis unit are combined and judged in pairs to obtain several levels of parallel test groups for the corresponding target analysis unit. Each parallel test group includes at least two devices under test, and the devices under test in the parallel test group do not share a test port. The parallel test order of the corresponding target analysis unit is established according to the hierarchical order of the parallel test groups of the target analysis unit. The testing module is used to generate new test files based on the parallel testing sequence of each of the target analysis units to automatically perform parallel testing on the device under test of all the test units.

Images