Chip Layout Method, Device, Electronic Device and Storage Medium

Abstract

An embodiment of the present invention discloses a chip layout method, apparatus, electronic device, and storage medium, which relate to the field of integrated circuit technologies and can improve the physical design integration of a chip. The method includes: determining a source instantiation module and a target instantiation module having a connection relationship in the chip based on a netlist file of the chip; determining a feedthrough connection line between the source instantiation module and the target instantiation module based on the connection relationship and a preset wiring rule; wherein the feedthrough connection line passes through an intermediate instantiation module between the source instantiation module and the target instantiation module; determining a target layout position of a relay register required on the feedthrough connection line; determining existing relay registers at at least one position among the source instantiation module on the feedthrough connection line, the target instantiation module on the feedthrough connection line, and the intermediate instantiation module on the feedthrough connection line, and adjusting the existing relay registers to the target layout position.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular, to a chip layout method, device, electronic device, and storage medium. Background Art

[0002] In the physical design process of a chip, the top-level layout planning is restricted by factors such as the size and connection relationship of lower-level instantiated modules. Therefore, it may cause two lower-level instantiated modules (source instantiated module and target instantiated module) with top-level connection relationships not to be placed adjacent to each other, and their placement positions are relatively far apart. At this time, the connection line between the two is very likely to pass through other intermediate instantiated modules, thus forming a feedthrough connection line.

[0003] When the placement positions of the source instantiated module that sends data and the target instantiated module that receives data are far apart, the length of the feedthrough connection line between the two is also long. When the length of the feedthrough connection line is greater than the transmission distance of data within one clock cycle, the data cannot be transmitted from the source instantiated module to the target instantiated module within one clock cycle. At this time, a certain number of relay registers need to be inserted into the feedthrough connection line to achieve the normal transmission of data between the source instantiated module and the target instantiated module. And such a design method will undoubtedly increase the number of logic units in the chip, thereby reducing the integration degree of the chip physical design. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a chip layout method, device, electronic device, and storage medium, which can improve the integration degree of the chip physical design.

[0005] In a first aspect, an embodiment of the present invention provides a chip layout method, including: based on a netlist file of a chip, determining a source instantiation module and a target instantiation module having a connection relationship in the chip; based on the connection relationship and a preset routing rule, determining a feedthrough connection line between the source instantiation module and the target instantiation module; wherein, the feedthrough connection line passes through an intermediate instantiation module between the source instantiation module and the target instantiation module; determining a target layout position of a relay register required on the feedthrough connection line; determining existing relay registers at at least one position among the source instantiation module on the feedthrough connection line, the target instantiation module on the feedthrough connection line, and the intermediate instantiation module on the feedthrough connection line; and adjusting the existing relay registers to the target layout position. Optionally, the determining, based on the netlist file of the chip, the source instantiation module and the target instantiation module having a connection relationship in the chip includes: loading a top-level netlist file of the chip and netlist files of each instantiation module; and based on the top-level netlist file and the netlist files of each instantiation module, determining the source instantiation module and the target instantiation module having a connection relationship.

[0006] Optionally, the determining, based on the connection relationship and the preset routing rule, the feedthrough connection line between the source instantiation module and the target instantiation module includes: based on the connection relationship and the preset routing rule, determining the feedthrough connection line between the source instantiation module and the target instantiation module and at least one intermediate instantiation module through which the feedthrough connection line passes.

[0007] Optionally, the determining existing relay registers at at least one position among the source instantiation module on the feedthrough connection line, the target instantiation module on the feedthrough connection line, and the intermediate instantiation module on the feedthrough connection line includes: obtaining attribute information of each register from a front-end design configuration file of the chip; and based on the attribute information of each register, determining existing relay registers at at least one position among the source instantiation module on the feedthrough connection line, the target instantiation module on the feedthrough connection line, and the intermediate instantiation module on the feedthrough connection line.

[0008] Optionally, the determining the target layout position of the relay register required on the feedthrough connection line includes: based on the physical length of the feedthrough connection line between the source instantiation module and the target instantiation module and corresponding clock cycle information, determining the target layout position of the relay register required on the feedthrough connection line.

[0009] Optionally, adjusting the existing relay register to the target layout position includes: adjusting the existing relay register from its original position to the target layout position with a different logical level from the original position.

[0010] Optionally, the intermediate instantiation module includes a first intermediate instantiation module; the target layout position includes on the internal feedthrough connection line in the first intermediate instantiation module; wherein, determining the existing relay register at at least one position of the source instantiation module on the feedthrough connection line, the target instantiation module on the feedthrough connection line, and the intermediate instantiation module on the feedthrough connection line; adjusting the existing relay register to the target layout position includes: determining whether there is a relay register in the first intermediate instantiation module; if there is no relay register in the first intermediate instantiation module, then determine

[0011] whether there is a relay register in other instantiation modules on the feedthrough connection line; if there is a relay register in other instantiation modules on the feedthrough connection line, adjust the existing relay register to the target layout position in the first intermediate instantiation module.

[0012] Optionally, adjusting the existing relay register to the target layout position in the first intermediate instantiation module includes: modifying the netlist file of the chip to adjust the existing

[0013] relay register to the netlist file corresponding to the first intermediate instantiation module; based on the modified netlist file of the chip, in the physical design environment of the chip, adjust the existing relay register to the target layout position in the first intermediate instantiation module.

[0014] Optionally, after adjusting the existing relay register to the target layout position in the first intermediate instantiation module, the method further includes: if there is no remaining relay register in other

[0015] instantiation modules on the feedthrough connection line, add a new relay register at the target layout position in the first intermediate instantiation module.

[0016] In a second aspect, an embodiment of the present invention provides a chip layout device, including: a first determination module, configured to determine a source instantiation module and a target instantiation module having a connection relationship in the chip based on a netlist file of the chip; a second determination module, configured to determine based on the connection relationship and a preset wiring rule

[0017] A feedthrough connection line between the source instantiation module and the target instantiation module; wherein, the feedthrough connection line passes through an intermediate instantiation module between the source instantiation module and the target instantiation module; a third determination module, configured to determine a target layout position of a relay register required on the feedthrough connection line; a fourth determination module, configured to determine existing relay registers at at least one position among the source instantiation module on the feedthrough connection line, the target instantiation module on the feedthrough connection line, and the intermediate instantiation module on the feedthrough connection line; an adjustment module, configured to adjust the existing relay registers to the target layout position.

[0018] Optionally, the existing relay registers are adjusted to the target layout position.

[0019] Optionally, the first determination module includes: a loading unit, configured to load a top-level netlist file of the chip and netlist files of each instantiation module; a determination unit, configured to determine a source instantiation module and a target instantiation module having a connection relationship based on the top-level netlist file and the netlist files of each instantiation module.

[0020] Optionally, the second determination module is specifically configured to: determine a feedthrough connection line between the source instantiation module and the target instantiation module and at least one intermediate instantiation module through which the feedthrough connection line passes based on the connection relationship and a preset routing rule.

[0021] Optionally, the fourth determination module is specifically configured to: obtain attribute information of each register from a front-end design configuration file of the chip; and determine existing relay registers at at least one position among the source instantiation module on the feedthrough connection line, the target instantiation module on the feedthrough connection line, and the intermediate instantiation module on the feedthrough connection line according to the attribute information of each register.

[0022] Optionally, the third determination module is specifically configured to: determine a target layout position of a relay register required on the feedthrough connection line based on a physical length of the feedthrough connection line between the source instantiation module and the target instantiation module and corresponding clock cycle information.

[0023] Optionally, the adjustment module is specifically configured to: adjust the existing relay registers from the original position to the target layout position having a different logical level from the original position.

[0024] Optionally, the intermediate instantiation module includes a first intermediate instantiation module; the target layout position is located on the internal feedthrough connection line in the first intermediate instantiation module; wherein, the fourth determination module is specifically configured to: determine whether there is a relay register in the first intermediate instantiation module; if there is no relay register in the first intermediate instantiation module, determine whether there is an adjustable relay register in other instantiation modules on the feedthrough connection line; the adjustment module is specifically configured to: if there is a relay register in other instantiation modules on the feedthrough connection line, adjust the existing relay register to the target layout position in the first intermediate instantiation module.

[0025] Optionally, the adjustment module includes: a modification unit, configured to modify the netlist file of the chip to adjust the existing relay register to the netlist file corresponding to the first intermediate instantiation module; an adjustment unit, configured to, based on the modified netlist file of the chip, in the physical design environment of the chip, adjust the existing relay register to the target layout position in the first intermediate instantiation module.

[0026] Optionally, the device further includes: an adding module, configured to add a new relay register to the target layout position in the first intermediate instantiation module if there is no remaining relay register in other instantiation modules on the feedthrough connection line.

[0027] In a third aspect, an embodiment of the present invention further provides an electronic device, including: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space surrounded by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is configured to supply power to each circuit or device of the above electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, and is configured to execute any one of the chip layout methods provided by the embodiments of the present invention.

[0028] In a fourth aspect, an embodiment of the present invention further provides a non-transitory computer-readable storage medium, storing one or more programs, where the one or more programs can be executed by one or more processors to implement any one of the chip layout methods provided by the embodiments of the present invention.

[0029] The chip layout method, device, electronic device and storage medium provided by the embodiments of the present invention can determine the source instantiation module and the target instantiation module with a connection relationship in the chip based on the netlist file of the chip, and then can determine the feedthrough connection line between the source instantiation module and the target instantiation module based on the connection relationship and the preset wiring rules, wherein the feedthrough connection line passes through the intermediate instantiation module between the source instantiation module and the target instantiation module. Finally, determine the target layout position of the relay register required on the feedthrough connection line, determine the existing relay registers on the feedthrough connection line, and adjust the existing relay registers to the target layout position. In this way, by determining the existing relay registers on the feedthrough connection line and adjusting these existing relay registers to the target layout position on the feedthrough connection line, the existing relay registers can be used to play the role of data transmission relay during data transmission, thereby reducing the number of newly added relay registers in the physical design process of the chip, and further improving the integration degree of the physical design of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0031] Figure 1 It is a schematic structural diagram of a physical design method of a chip in some embodiments;

[0032] Figure 2 It is a schematic flowchart of a chip layout method provided by the embodiments of the present invention;

[0033] Figure 3 It is a schematic structural diagram of a feedthrough connection line planning method in the embodiments of the present invention;

[0034] Figure 4 It is a schematic diagram of the target layout position of the relay register required on the feedthrough connection line in the embodiments of the present invention;

[0035] Figure 5 It is a schematic structural diagram of a relay register position adjustment method of a chip in the embodiments of the present invention;

[0036] Figure 6 It is a schematic structural diagram of a new relay register adding method of a chip in the embodiments of the present invention;

[0037] Figure 7Schematic diagram of a chip layout device provided by an embodiment of the present invention;

[0038] Figure 8 Schematic diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0039] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0040] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0041] To facilitate the understanding of the technical solutions of the present application, the relevant background knowledge of the present application will be briefly introduced first.

[0042] The design process of a chip includes a logic design stage and a physical design stage. The logic design stage can further include a functional design sub-stage, a simulation design sub-stage, and a logic synthesis sub-stage. In the functional design sub-stage, for the chip functions to be implemented by the user, a hardware description language (for example, Verilog language or VHDL language) is generally used for description to form register transfer level (RTL) level code. In the simulation verification sub-stage, in order to ensure the correctness of the circuit function, a circuit simulator of Verilog or VHDL can be used to perform functional verification on the functional design described by the hardware description language. In the logic synthesis sub-stage, for the functional design verified correctly in the simulation verification sub-stage, a logic synthesis tool can be used to generate a process-related netlist file through steps of translation, optimization, and mapping of the functional design described by the hardware description language. The netlist file is a file that records the connection relationships and delay information between logic gates. Logic synthesis is a bridge connecting the high level of the circuit and the physical implementation. The given constraints and the synthesized gate-level netlist will be sent to the back-end tools in the physical design stage for placement and routing.

[0043] The physical design stage includes a placement and routing sub-stage and an output sub-stage. In the placement and routing sub-stage, placement refers to reasonably arranging the designed functional modules on the chip and planning their positions. Routing refers to completing the connection lines between the functional modules. In the output sub-stage, a layout file is output, which is used to instruct the foundry how to etch the silicon wafer and how to connect the metal, etc. Of course, there will be various auxiliary steps in this process to ensure the correctness of the circuit.

[0044] In some embodiments, such as Figure 1As shown, the feed-through connection line between the instantiated module A and the instantiated module D is too long. It is necessary to add the relay register PipeB and the relay register PipeC on the feed-through connection line AD to achieve normal data transmission. Such a design method will undoubtedly increase the number of logic units in the chip, thereby reducing the integration of the physical design of the chip.

[0045] In a first aspect, an embodiment of the present invention provides a chip layout method, which can improve the integration of the physical design of the chip.

[0046] As Figure 2 shown, an embodiment of the present invention provides a chip layout method, which may include:

[0047] S11, based on the netlist file of the chip, determine the source instantiated module and the target instantiated module having a connection relationship in the chip;

[0048] The connection relationship information between each instantiated module is recorded in the netlist file of the chip. Therefore, according to the connection relationship information between each instantiated module in the netlist file of the chip, any pair of instantiated modules having a connection relationship in the chip can be determined. For example, the instantiated module A and the instantiated module D. Generally, the instantiated module that sends data can be called the source instantiated module, and the instantiated module that receives data can be called the target instantiated module.

[0049] S12, based on the connection relationship and the preset wiring rules, determine the feed-through connection line between the source instantiated module and the target instantiated module; wherein, the feed-through connection line passes through the intermediate instantiated module between the source instantiated module and the target instantiated module;

[0050] In the physical design process of the chip, referring to Figure 3 as shown, first, the instantiated module A and the instantiated module D having a connection relationship can be positionally arranged on the physical design interface to determine their specific positions. Then, according to their specific positions and the preset wiring rules, the connection line between them can be determined. When the distance between them is relatively far, if the connection line between them passes through one or more other intermediate instantiated modules, the connection line between them belongs to the feed-through connection line. In Figure 3 the example shown, the intermediate instantiated modules between the instantiated module A and the instantiated module D include the instantiated module B and the instantiated module C, and the feed-through connection line between the instantiated module A and the instantiated module D is the feed-through connection line AD.

[0051] In one example, according to the preset wiring rules, the shortest connection line between the two can be used as the connection line between them. Of course, the connection line between the two can also be wired according to other preset wiring rules, and the embodiments of the present invention do not limit this.

[0052] S13. Determine the target layout positions of the relay registers required on the feedthrough connection line;

[0053] When the length of the feedthrough connection line is relatively long, the source instantiation module cannot transmit data to the target instantiation module within the preset time. To ensure the normal transmission of data, it is necessary to arrange relay registers in the feedthrough connection line, and each relay register is used to implement the data transmission relay function. Specifically, the structure in which multiple relay registers existing in the chip are connected in series to transmit data can be called a pipeline structure. In the first transmission process, the data is transmitted from the source instantiation module to the first adjacent relay register. In the second transmission process, the data is transmitted from the first relay register to the second adjacent relay register, and so on. After multiple transmissions, the data can be transmitted to the target instantiation module.

[0054] Before arranging relay registers in the feedthrough connection line, it is first necessary to determine the target layout positions of the relay registers to be connected on the feedthrough connection line, that is, to determine at which specific positions on the feedthrough connection line the relay registers should be arranged to ensure the normal transmission of data in the pipeline structure formed by the relay registers.

[0055] S14. Determine the existing relay registers at at least one position among the source instantiation module on the feedthrough connection line, the target instantiation module on the feedthrough connection line, and the intermediate instantiation module on the feedthrough connection line;

[0056] S15. Adjust the existing relay registers to the target layout positions.

[0057] The chip includes both relay registers with adjustable positions and non-relay registers with non-adjustable positions. Specifically, the relay register has a simple structure with one input corresponding to one output. This simple structure makes the data flow very clear when passing through the relay register. Changing the physical position of the relay register in the physical design will not have too much impact on aspects such as the timing of the surrounding logic. Therefore, the physical position of the relay register can be adjusted. In contrast, due to the complex structure of the non-relay register with multiple inputs and multiple outputs, changing its physical position during the physical design process will have a greater impact on aspects such as the timing of the surrounding logic. Therefore, generally, the physical position of the non-relay register is not allowed to be adjusted.

[0058] After determining the target layout positions of the relay registers on the feedthrough connection line, the existing relay registers in the chip can be first divided according to the type of relay register to determine the existing relay registers in the chip, and then determine which of the existing relay registers are in the instantiated module A, instantiated module B, instantiated module C, and instantiated module D. Specifically, it is the relay register PipeA in the instantiated module A.

[0059] Adjusting the existing relay registers on the above-mentioned feedthrough connection line to the target layout positions can enable the above-mentioned relay registers to realize their original functions while also realizing the data transmission relay function, thereby reducing the number of new relay registers added in the physical design process of the chip and improving the integration degree of the physical design of the chip.

[0060] The chip layout method provided by the embodiment of the present invention can determine the source instantiated module and the target instantiated module with a connection relationship in the chip based on the netlist file of the chip, and then can determine the feedthrough connection line between the source instantiated module and the target instantiated module based on the connection relationship and the preset wiring rules, where the feedthrough connection line passes through the intermediate instantiated module between the source instantiated module and the target instantiated module. Finally, determine the target layout positions of the relay registers required on the feedthrough connection line, determine the existing relay registers on the feedthrough connection line, and adjust the existing relay registers to the target layout positions. In this way, by determining the existing relay registers on the feedthrough connection line and adjusting these existing relay registers to the target layout positions on the feedthrough connection line, the existing relay registers can be used to play the role of data transmission relay during the data transmission process, thereby reducing the number of new relay registers added in the physical design process of the chip, and further improving the integration degree of the physical design of the chip.

[0061] Optionally, in an embodiment of the present invention, the determining the source instantiated module and the target instantiated module with a connection relationship in the chip based on the netlist file of the chip (step S11) may include: loading the top-level netlist file of the chip and the netlist files of each instantiated module; determining the source instantiated module and the target instantiated module with a connection relationship based on the top-level netlist file and the netlist files of each instantiated module.

[0062] The netlist file of the chip may include the top-level netlist file and the netlist files of each instantiated module. The top-level netlist file records the connection relationships between the instantiated modules, and the netlist file of each instantiated module records the interface information of the instantiated module, and may also include the information of the internal circuit of the instantiated module.

[0063] For example, the top-level netlist file records the connection information that the X interface of the instantiated module A is connected to the Y interface of the instantiated module D. The netlist of the instantiated module A can be a simplified netlist file that only records the interface information of the instantiated module A, or a full-version netlist file that records both the interface information of the instantiated module A and the information of the internal circuit of the instantiated module. The same applies to the instantiated module D, which will not be elaborated here.

[0064] Therefore, after loading the top-level netlist file of the chip and the netlist files of each instantiated module, the connection relationship information between each instantiated module can be determined based on these netlist files, and then any pair of instantiated modules with a connection relationship in the chip can be determined, such as the instantiated module A and the instantiated module D, as Figure 3 shown.

[0065] Optionally, in an embodiment of the present invention, based on the connection relationship and the preset wiring rules, determining the feedthrough connection line between the source instantiated module and the target instantiated module (step S12) may include: based on the connection relationship and the preset wiring rules, determining the feedthrough connection line between the source instantiated module and the target instantiated module and at least one intermediate instantiated module through which the feedthrough connection line passes.

[0066] In the physical design process of the chip, after determining the positions of all instantiated modules in the chip, each instantiated module has determined size information and position information. As Figure 3 shown, for the instantiated module A and the instantiated module D with a connection relationship, after determining the feedthrough connection line AD between the two according to the preset wiring rules, the feedthrough connection line AD has determined routing path information. According to the routing path information of the feedthrough connection line AD and the size information and position information of each instantiated module (instantiated module A, instantiated module B, instantiated module C, and instantiated module D), it can be determined which intermediate instantiated modules the feedthrough connection line AD passes through. In Figure 3 the example shown, it can be determined that the intermediate instantiated modules through which the feedthrough connection line AD passes are the instantiated module B and the instantiated module C.

[0067] Optionally, in an embodiment of the present invention, determining at least one existing relay register among the source instantiation module, the target instantiation module, and the intermediate instantiation module on the feedthrough connection line in step S14 may include: obtaining the attribute information of each register from the front-end design configuration file of the chip; and determining at least one existing relay register among the source instantiation module, the target instantiation module, and the intermediate instantiation module on the feedthrough connection line according to the attribute information of each register.

[0068] In the functional design sub-phase of the chip, when describing the chip function using a hardware description language, a front-end design configuration file of the chip can also be generated. The front-end design configuration file can be a constraint file in the format of Extensible Markup Language (XML) or a constraint file in the format of JavaScript Object Notation (JSON).

[0069] The attribute information of each register can be stored in the front-end configuration file. According to the attribute information of each register, it is possible to determine whether each register is a relay register. In one example, in the front-end configuration file, the attribute of each relay register can be marked as "is PD Pipe = true", while other attribute marking methods can be used for non-relay registers to distinguish between the two. In this way, it is possible to determine which existing registers in the chip belong to adjustable relay registers and which existing registers belong to non-adjustable non-relay registers according to the attribute information of each relay register in the front-end configuration file.

[0070] In Figure 3 In the example shown, the existing relay registers included in the instantiation module A, instantiation module B, instantiation module C, and instantiation module D on the feedthrough connection line can be screened out from all the relay registers in the chip, and the screening result is that the instantiation module A includes the relay register PipeA. The relay register PipeA can be used to be adjusted to the target layout position in the subsequent process.

[0071] Optionally, in an embodiment of the present invention, determining the target layout position of the relay register required on the feedthrough connection line may include: determining the target layout position of the relay register required on the feedthrough connection line based on the physical length of the feedthrough connection line between the source instantiation module and the target instantiation module and the corresponding clock cycle information.

[0072] In the embodiment of the present invention, followingFigure 3 In the illustrated example, for the instantiated module A and the instantiated module D with a connection relationship, the feedthrough connection line AD between the two corresponds to a certain clock cycle. The product of this clock cycle and the data transmission speed is the transmission distance H of the data within one clock cycle. If the length of the feedthrough connection line AD is greater than H, it indicates that the data cannot be transmitted from the instantiated module A to the instantiated module D within one clock cycle. In one example, a target layout position can be set at intervals of distance H on the feedthrough connection line AD between the instantiated module A and the instantiated module D, so as to place a relay register at each target layout position in the subsequent process to achieve the data transmission relay function. Of course, the distance between adjacent target layout positions can be less than the distance H, and the embodiments of the present invention do not limit this.

[0073] Optionally, in an embodiment of the present invention, adjusting the existing relay register to the target layout position in step S14 may include: adjusting the existing relay register from its original position to the target layout position with a different logical level from the original position.

[0074] The logical level of the relay register in the chip represents the position of the relay register in the physical design interface. Specifically, if both the relay register E and the relay register F are located in the same instantiated module, their logical levels are the same; if both the relay register E and the relay register F are located in the top-level design of the chip, their logical levels are also the same; if the relay register E and the relay register F are located in different instantiated modules, their logical levels are different; if the relay register E is located in the top-level design of the chip and the relay register F is located in a low-level instantiated module, their logical levels are also different.

[0075] Refer to Figure 4In the illustrated example, the existing relay register PipeA in the feedthrough connection line AD is located in the instantiated module A, while the target layout position b is located in the instantiated module B, and the target layout position c is located in the instantiated module C. The logical levels of the relay register PipeA and the target layout position b are different, and the logical levels of the relay register PipeA and the target layout position c are also different. To add a relay register at the target layout position, the relay register PipeA can be adjusted to the target layout position b, or the relay register PipeA can also be adjusted to the target layout position c. In this way, the data transmission relay function can be implemented in the instantiated module B (or the instantiated module C) by using the existing relay register PipeA. Compared with the prior art solution that requires adding two new relay registers at two target layout positions, the solution of the present invention only needs to add one new relay register on the basis of using the existing relay register PipeA, thereby reducing the number of new relay registers added in the physical design process of the chip, and further improving the integration degree of the chip physical design.

[0076] Optionally, in an embodiment of the present invention, the intermediate instantiated module includes a first intermediate instantiated module; the target layout position is located on an internal feedthrough connection line in the first intermediate instantiated module; wherein, determining at least one existing relay register at the source instantiated module on the feedthrough connection line, the target instantiated module on the feedthrough connection line, and the intermediate instantiated module on the feedthrough connection line; adjusting the existing relay register to the target layout position may include: determining whether there is a relay register in the first intermediate instantiated module; if there is no relay register in the first intermediate instantiated module, determining whether there is a relay register in other instantiated modules on the feedthrough connection line; if there is a relay register in other instantiated modules on the feedthrough connection line, adjusting the existing relay register to the target layout position in the first intermediate instantiated module.

[0077] In an embodiment of the present invention, for any intermediate instantiated module (referred to as the first intermediate instantiated module for short) in the chip where there is a target layout position, taking the first intermediate instantiated module as the instantiated module B as an example, first determine whether there is a relay register in the instantiated module B. If so, there is no need to adjust the logical level of the relay register in the netlist file. Directly in the physical design environment, adjust the position of the relay register inside the instantiated module B and adjust it to the target layout position. If not, such as Figure 4As shown, it is determined whether there are relay registers in other instantiated modules (instantiated module A, instantiated module C, and instantiated module D) on the feedthrough connection line and in the top-level design of the chip. It can be determined that there is a relay register PipeA in instantiated module A, and then the relay register PipeA is adjusted from instantiated module A to the target layout position b of instantiated module B, as Figure 5 shown.

[0078] Optionally, in an embodiment of the present invention, the adjusting the existing relay register to the target layout position in the first intermediate instantiated module may include: modifying the netlist file of the chip to adjust the existing relay register to the netlist file corresponding to the first intermediate instantiated module; based on the modified netlist file of the chip, in the physical design environment of the chip, adjusting the existing relay register to the target layout position in the first intermediate instantiated module.

[0079] Referring to Figure 5 the example shown, there is an existing relay register PipeA in instantiated module A. When adjusting the relay register PipeA to instantiated module B, the logical level of the relay register PipeA can be adjusted in the netlist file first. Specifically, the relay register PipeA can be deleted from the netlist file of instantiated module A and added to the netlist file of instantiated module B, while retaining the original connection relationship of the relay register PipeA, so as not to affect the original function of the relay register PipeA.

[0080] Based on the modified netlist file, in the physical design environment of the chip, the relay register PipeA can be adjusted to the target layout position b of instantiated module B and connected to the feedthrough connection line AD, so that the relay register PipeA can play the data transmission relay function.

[0081] Optionally, in an embodiment of the present invention, after adjusting the existing relay register to the target layout position in the first intermediate instantiated module, the method may further include: if there are no remaining relay registers in other instantiated modules on the feedthrough connection line, adding a new relay register at the target layout position in the first intermediate instantiated module.

[0082] In an embodiment of the present invention, referring to Figure 5In the example shown, among the other instantiated modules on the feedthrough connection line AD, there is only one relay register, i.e., PipeA, in the existing relay registers, and the target layout positions include target layout position b and target layout position c. After adjusting the relay register PipeA to the target layout position b of the instantiated module B, there are no other relay registers left in the other instantiated modules on the feedthrough connection line AD. Therefore, the newly added relay register PipeC can be placed at the target layout position c in the instantiated module C to implement the data transmission relay function, as Figure 6 shown. In this way, based on the existing relay register PipeA, the technical solution of the present invention only needs to newly add one relay register, i.e., PipeC. Compared with Figure 1 the prior art in which two relay registers (relay register PipeB and relay register PipeC) need to be added, the number of newly added relay registers in the physical design of the chip can be reduced, thereby improving the integration degree of the physical design of the chip.

[0083] In a second aspect, an embodiment of the present invention provides a chip layout device, which can improve the integration degree of the physical design of the chip.

[0084] As Figure 7 shown, an embodiment of the present invention provides a chip layout device 1, which may include: a first determination module 11, configured to determine a source instantiated module and a target instantiated module having a connection relationship in the chip based on a netlist file of the chip; a second determination module 12, configured to determine a feedthrough connection line between the source instantiated module and the target instantiated module based on the connection relationship and a preset wiring rule; wherein the feedthrough connection line passes through an intermediate instantiated module between the source instantiated module and the target instantiated module; a third determination module 13, configured to determine a target layout position of a relay register required on the feedthrough connection line; a fourth determination module 14, configured to determine an existing relay register at at least one position among the source instantiated module on the feedthrough connection line, the target instantiated module on the feedthrough connection line, and the intermediate instantiated module on the feedthrough connection line; and an adjustment module 15, configured to adjust the existing relay register to the target layout position.

[0085] The chip layout device provided by the embodiments of the present invention can determine the source instantiation module and the target instantiation module with a connection relationship in the chip based on the netlist file of the chip, and then can determine the feedthrough connection line between the source instantiation module and the target instantiation module based on the connection relationship and the preset wiring rules, wherein the feedthrough connection line passes through the intermediate instantiation module between the source instantiation module and the target instantiation module. Finally, determine the target layout position of the relay register required on the feedthrough connection line, determine the existing relay registers on the feedthrough connection line, and adjust the existing relay registers to the target layout position. In this way, by determining the existing relay registers on the feedthrough connection line and adjusting these existing relay registers to the target layout position on the feedthrough connection line, the existing relay registers can be used to play the role of data transmission relay during data transmission, thereby reducing the number of newly added relay registers in the physical design process of the chip, and further improving the integration degree of the physical design of the chip.

[0086] Optionally, in an embodiment of the present invention, the first determination module 11 includes: a loading unit for loading the top-level netlist file of the chip and the netlist files of each instantiation module; a determination unit for determining the source instantiation module and the target instantiation module with a connection relationship based on the top-level netlist file and the netlist files of each instantiation module.

[0087] Optionally, in an embodiment of the present invention, the second determination module 12 is specifically configured to: determine the feedthrough connection line between the source instantiation module and the target instantiation module and at least one intermediate instantiation module passed by the feedthrough connection line based on the connection relationship and the preset wiring rules.

[0088] Optionally, in an embodiment of the present invention, the fourth determination module 14 is specifically configured to: obtain the attribute information of each register from the front-end design configuration file of the chip; determine the existing relay registers at at least one position among the source instantiation module on the feedthrough connection line, the target instantiation module on the feedthrough connection line, and the intermediate instantiation module on the feedthrough connection line according to the attribute information of each register.

[0089] Optionally, in an embodiment of the present invention, the third determination module 13 is specifically configured to: determine the target layout position of the relay register required on the feedthrough connection line based on the physical length of the feedthrough connection line between the source instantiation module and the target instantiation module and the corresponding clock cycle information.

[0090] Optionally, in an embodiment of the present invention, the adjustment module 15 is specifically configured to: adjust the existing relay register from its original position to the target layout position that is at a different logical level from the original position.

[0091] Optionally, in an embodiment of the present invention, the intermediate instantiation module includes a first intermediate instantiation module; the target layout position includes being on the internal feedthrough connection line in the first intermediate instantiation module;

[0092] Among them, the fourth determination module 14 is specifically configured to: determine whether there is a relay register in the first intermediate instantiation module; if there is no relay register in the first intermediate instantiation module, determine whether there is an adjustable relay register in other instantiation modules on the feedthrough connection line;

[0093] The adjustment module 15 is specifically configured to: if there is a relay register in other instantiation modules on the feedthrough connection line, adjust the existing relay register to the target layout position in the first intermediate instantiation module.

[0094] Optionally, in an embodiment of the present invention, the adjustment module 15 includes: a modification unit, configured to modify the netlist file of the chip to adjust the existing relay register to the netlist file corresponding to the first intermediate instantiation module; an adjustment unit, configured to, based on the modified netlist file of the chip, in the physical design environment of the chip, adjust the existing relay register to the target layout position in the first intermediate instantiation module.

[0095] Optionally, in an embodiment of the present invention, the device further includes: an addition module, configured to, if there is no remaining relay register in other instantiation modules on the feedthrough connection line, add a new relay register at the target layout position in the first intermediate instantiation module.

[0096] In a third aspect, an embodiment of the present invention provides an electronic device, which can improve the physical design integration degree of a chip.

[0097] Such as Figure 8As shown in the figure, an electronic device provided by an embodiment of the present invention may include: a housing 100, at least one processor 110, a memory 120, a circuit board 130, and a power supply circuit 140. Among them, the circuit board 130 is disposed inside the space surrounded by the housing 100, and the processor 110 and the memory 120 are provided on the circuit board 130; the power supply circuit 140 is used to supply power to each circuit or device of the above-mentioned server; the memory 120 is used to store executable program codes; the processor 110 runs a program corresponding to the executable program code by reading the executable program codes stored in the memory 120, and is used to execute any one of the chip layout methods provided by the foregoing embodiments. For the specific execution process of the above steps by the processor 110 and the further steps executed by the processor 110 by running the executable program code, reference may be made to the description of the foregoing embodiments, which will not be elaborated herein.

[0098] In a fourth aspect, an embodiment of the present invention further provides a non-transitory computer-readable storage medium, where the non-transitory computer-readable storage medium has one or more programs, and the one or more programs can be executed by one or more processors to implement any one of the chip layout methods provided by the foregoing embodiments. For the specific execution process of the above steps by the processor and the further steps executed by the processor by running the executable program code, reference may be made to the description of the foregoing embodiments, which will not be elaborated herein.

[0099] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including the element.

[0100] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. The key point of each embodiment is to illustrate the differences from other embodiments.

[0101] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for the relevant parts, reference can be made to the partial description of the method embodiment.

[0102] For the convenience of description, the above device is described by dividing it into various units / modules according to functions. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0103] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc.

[0104] The above is only a specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A chip layout method, characterized in that, Including: Based on the chip's netlist file, determine the source instantiation module and the target instantiation module with a connection relationship in the chip; Based on the connection relationship and preset wiring rules, determine the feedthrough connection line between the source instantiation module and the target instantiation module; wherein, the feedthrough connection line passes through an intermediate instantiation module between the source instantiation module and the target instantiation module; Determine the target layout position of the relay register required on the feedthrough connection line; Determine the existing relay registers at at least one position among the source instantiation module on the feedthrough connection line, the target instantiation module on the feedthrough connection line, and the intermediate instantiation module on the feedthrough connection line; Adjust the existing relay register to the target layout position.

2. The chip layout method according to claim 1, wherein The determining, based on the chip's netlist file, the source instantiation module and the target instantiation module with a connection relationship in the chip includes: Load the top-level netlist file of the chip and the netlist files of each instantiation module; Based on the top-level netlist file and the netlist files of each instantiation module, determine the source instantiation module and the target instantiation module with a connection relationship.

3. The chip layout method according to claim 1, wherein The determining, based on the connection relationship and preset wiring rules, the feedthrough connection line between the source instantiation module and the target instantiation module includes: Based on the connection relationship and preset wiring rules, determine the feedthrough connection line between the source instantiation module and the target instantiation module and at least one intermediate instantiation module through which the feedthrough connection line passes.

4. The chip layout method according to claim 3, wherein The determining the existing relay registers at at least one position among the source instantiation module on the feedthrough connection line, the target instantiation module on the feedthrough connection line, and the intermediate instantiation module on the feedthrough connection line includes: Obtain the attribute information of each register from the front-end design configuration file of the chip; Based on the attribute information of each register, determine the existing relay registers at at least one position among the source instantiation module on the feedthrough connection line, the target instantiation module on the feedthrough connection line, and the intermediate instantiation module on the feedthrough connection line.

5. The chip layout method according to claim 1, wherein The determining the target layout position of the relay register required on the feedthrough connection line includes: Based on the physical length of the feedthrough connection line between the source instantiation module and the target instantiation module and the corresponding clock cycle information, determine the target layout position of the relay register required on the feedthrough connection line.

6. The chip layout method according to claim 1, wherein The adjusting the existing relay register to the target layout position includes: Adjust the existing relay register from its original position to the target layout position with a different logical level from the original position.

7. The chip layout method according to claim 1, wherein The intermediate instantiation module includes a first intermediate instantiation module; The target layout position includes being on the internal feedthrough connection line in the first intermediate instantiation module; Among them, determining at least one existing relay register at the source instantiation module on the feedthrough connection line, the target instantiation module on the feedthrough connection line, and the intermediate instantiation module on the feedthrough connection line; adjusting the existing relay register to the target layout position includes: Judging whether there is a relay register in the first intermediate instantiation module; If there is no relay register in the first intermediate instantiation module, determining whether there is a relay register in other instantiation modules on the feedthrough connection line; If there is a relay register in other instantiation modules on the feedthrough connection line, adjusting the existing relay register to the target layout position in the first intermediate instantiation module.

8. The chip layout method according to claim 7, wherein The adjusting the existing relay register to the target layout position in the first intermediate instantiation module includes: Modifying the netlist file of the chip to adjust the existing relay register to the netlist file corresponding to the first intermediate instantiation module; Based on the modified netlist file of the chip, in the physical design environment of the chip, adjusting the existing relay register to the target layout position in the first intermediate instantiation module.

9. The chip layout method according to claim 7, wherein After adjusting the existing relay register to the target layout position in the first intermediate instantiation module, the method further includes: If there are no remaining relay registers in other instantiation modules on the feedthrough connection line, adding a new relay register at the target layout position in the first intermediate instantiation module.

10. A chip layout device, characterized in that, Including: A first determination module, configured to determine a source instantiation module and a target instantiation module with a connection relationship in the chip based on the netlist file of the chip; A second determination module, configured to determine a feedthrough connection line between the source instantiation module and the target instantiation module based on the connection relationship and a preset routing rule; wherein, the feedthrough connection line passes through an intermediate instantiation module between the source instantiation module and the target instantiation module; A third determination module, configured to determine the target layout position of the relay register required on the feedthrough connection line; A fourth determination module, configured to determine at least one existing relay register at the source instantiation module on the feedthrough connection line, the target instantiation module on the feedthrough connection line, and the intermediate instantiation module on the feedthrough connection line; an adjustment module, configured to adjust the existing relay register to the target layout position.

11. The chip layout device according to claim 10, wherein The first determination module includes: A loading unit, configured to load the top-level netlist file of the chip and the netlist files of each instantiation module; A determination unit, configured to determine a source instantiation module and a target instantiation module with a connection relationship based on the top-level netlist file and the netlist files of each instantiation module.

12. The chip layout device according to claim 10, wherein, The second determination module is specifically configured to: Based on the connection relationship and the preset wiring rules, determine the feedthrough connection line between the source instantiation module and the target instantiation module and at least one intermediate instantiation module through which the feedthrough connection line passes.

13. The chip layout device according to claim 12, wherein The fourth determination module is specifically configured to: Obtain the attribute information of each register from the front-end design configuration file of the chip; based on the attribute information of each register, determine at least one relay register existing at a position among the source instantiation module on the feedthrough connection line, the target instantiation module on the feedthrough connection line, and the intermediate instantiation module on the feedthrough connection line.

14. The chip layout device according to claim 10, wherein The third determination module is specifically configured to: Based on the physical length of the feedthrough connection line between the source instantiation module and the target instantiation module and the corresponding clock cycle information, determine the target layout position of the relay register required on the feedthrough connection line.

15. The chip layout device according to claim 10, wherein The adjustment module is specifically configured to: Adjust the existing relay register from its original position to the target layout position that is logically different from the original position.

16. The chip layout device according to claim 10, characterized in that, The intermediate instantiation module includes a first intermediate instantiation module; the target layout position includes on the internal feedthrough connection line in the first intermediate instantiation module; Wherein, the fourth determination module is specifically configured to: determine whether there is a relay register in the first intermediate instantiation module; if there is no relay register in the first intermediate instantiation module, determine whether there is an adjustable relay register in other instantiation modules on the feedthrough connection line; The adjustment module is specifically configured to: if there is a relay register in other instantiation modules on the feedthrough connection line, adjust the existing relay register to the target layout position in the first intermediate instantiation module.

17. The chip layout device according to claim 16, wherein, The adjustment module includes: A modification unit, configured to modify the netlist file of the chip to adjust the existing relay register to the netlist file corresponding to the first intermediate instantiation module; An adjustment unit, configured to, based on the modified netlist file of the chip, in the physical design environment of the chip, adjust the existing relay register to the target layout position in the first intermediate instantiation module.

18. The chip layout device according to claim 16, wherein, The device further includes: An addition module, configured to add a new relay register at the target layout position in the first intermediate instantiation module if there is no remaining relay register in other instantiation modules on the feedthrough connection line.

19. An electronic device, characterized in that, The electronic device includes: a housing, a processor, a memory, a circuit board, and a power circuit. Among them, the circuit board is arranged inside the space surrounded by the housing, and the processor and the memory are arranged on the circuit board; the power circuit is used to supply power to each circuit or device of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used to execute the chip layout method according to any one of the preceding claims 1 to 9.

20. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium stores computer instructions for causing the computer to execute the chip layout method according to any one of claims 1 to 9.

Images