Amplifier and Memory

Abstract

Embodiments of the present application relate to the field of semiconductors, and provide an amplifier and a memory. The amplifier at least includes: a sense amplifier, the sense amplifier includes a pull-up driving circuit and an amplifying circuit, one end of the pull-up driving circuit is connected to a supply voltage, and the other end is connected to the power supply terminal of the amplifying circuit; the sense amplifier includes a first sense amplifier and a second sense amplifier, the first sense amplifier includes a first pull-up driving circuit and a first amplifying circuit, the second sense amplifier includes a second pull-up driving circuit and a second amplifying circuit, and both the first pull-up driving circuit and the second pull-up driving circuit are located between the first amplifying circuit and the second amplifying circuit. Embodiments of the present application are beneficial to improving the layout of the amplifier.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductors, and particularly to an amplifier and a memory. Background Art

[0002] A DRAM (Dynamic Random Access Memory) memory includes multiple word lines and multiple bit lines arranged crosswise, and memory cells formed by capacitors are connected to the word lines and the bit lines; during the read operation of the memory cells, the word lines connected to the memory cells are activated, the charge state of the capacitors in the memory cells is applied to the bit lines, a tiny voltage signal is formed on the bit line pair, and an amplifier circuit connected to the bit line pair amplifies the tiny voltage signal and transmits it to the lower-layer local input / output line. Summary of the Invention

[0003] The embodiments of the present application provide an amplifier and a memory, which are at least beneficial to improving the layout of the amplifier.

[0004] According to some embodiments of the present application, on the one hand, the embodiments of the present application provide an amplifier, including: a sense amplifier, the sense amplifier includes a pull-up driving circuit and an amplifying circuit, one end of the pull-up driving circuit is connected to a supply voltage, and the other end is connected to the power supply terminal of the amplifying circuit; the sense amplifier includes a first sense amplifier and a second sense amplifier, the first sense amplifier includes a first pull-up driving circuit and a first amplifying circuit, the second sense amplifier includes a second pull-up driving circuit and a second amplifying circuit, and both the first pull-up driving circuit and the second pull-up driving circuit are located between the first amplifying circuit and the second amplifying circuit.

[0005] According to some embodiments of the present application, on the other hand, the embodiments of the present application further provide a memory, including the above amplifier.

[0006] The technical solutions provided by the embodiments of the present application have at least the following advantages:

[0007] In the above technical solution, the first pull-up driving circuit and the second pull-up driving circuit are arranged between the first amplifying circuit and the second amplifying circuit, which is beneficial to making the number of like circuit devices between the first amplifying circuit and the second amplifying circuit an even number. The like circuit devices include the pull-up driving circuit and other connected circuit devices, such as a local equalization circuit. Setting the number of like circuit devices to an even number is beneficial to improving the layout, enhancing the symmetry of the layout, and improving the corresponding electrical performance. Brief Description of the Drawings

[0008] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation.

[0009] Figure 1 Schematic diagram of the circuit structure of the amplifier provided by the embodiment of the present application;

[0010] Figure 2 Schematic diagram of the layout structure of the amplifier provided by the embodiment of the present application;

[0011] Figure 3 Schematic diagram of the structure of the memory provided by the embodiment of the present application. Detailed implementation manners

[0012] The following will elaborate on each embodiment of the present application in conjunction with the drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present application, many technical details are presented for the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0013] Figure 1 Schematic diagram of the circuit structure of the amplifier provided by the embodiment of the present application; Figure 2 Schematic diagram of the layout structure of the amplifier provided by the embodiment of the present application; Figure 3 Schematic diagram of the structure of the memory provided by the embodiment of the present application.

[0014] Refer to Figures 1 to 2 , the amplifier includes: a sense amplifier (not labeled), the sense amplifier includes a pull-up drive circuit 11 and an amplification circuit 12, one end of the pull-up drive circuit 11 is connected to the supply voltage VDD, and the other end is connected to the power supply terminal 12a of the amplification circuit 12; the sense amplifier includes a first sense amplifier and a second sense amplifier, the first sense amplifier includes a first pull-up drive circuit 111 and a first amplification circuit 121, the second sense amplifier includes a second pull-up drive circuit 112 and a second amplification circuit 122, and both the first pull-up drive circuit 111 and the second pull-up drive circuit 112 are located between the first amplification circuit 121 and the second amplification circuit 122.

[0015] The following will further elaborate on the embodiments of the present application in conjunction with the drawings.

[0016] Refer to Figure 1, the amplifier circuit 12 includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2. The drains of P1 and P2 are connected to the power supply terminal 12a, and the sources of N1 and N2 are connected to the ground terminal 12b of the amplifier circuit 12. The gates of P1, N1, the source of P2, and the drain of N2 are connected to the bit line BL, and the gates of P2, N2, the source of P1, and the drain of N1 are connected to the complementary bit line BLB. When the memory is in standby, the power supply terminal 12a and the ground terminal 12b of the amplifier circuit 12 are driven to the same pre-charge voltage as the bit line pair BL / BLB, such as VDD / 2, through the electrode lines PCS / NCS; during the read operation of the memory, by activating the corresponding word line, the charge state of the capacitor is transferred to the bit line pair BL / BLB, and a small voltage signal is generated on the bit line pair BL / BLB. At this time, the voltage of the power supply terminal 12a can be set to the internal step-down voltage through the electrode line PCS, and the voltage of the ground terminal 12b can be set to the ground voltage through the electrode line NCS to activate the amplifier circuit 12. The activated amplifier circuit 12 is used to amplify the small voltage signal and transmit the amplified read signal to the local input / output line LIO / local complementary input / output line LIOB.

[0017] In some embodiments, the amplifier further includes: a local equalization circuit 13, one end of which is connected to the power supply terminal 12a of the amplifier circuit 12, and the other end of which is connected to the ground terminal 12b of the amplifier circuit 12, and is used to connect the power supply terminal 12a and the ground terminal 12b. In other words, the local equalization circuit 13 is used to connect or disconnect the power supply terminal 12a and the ground terminal 12b of the amplifier circuit 12. When the memory is in the standby state, the power supply terminal 12a and the ground terminal 12b are connected, and the voltage values of the power supply terminal 12a and the ground terminal 12b are equal; when the memory is in the read operation, the power supply terminal 12a and the ground terminal 12b are disconnected to activate the amplifier circuit 12.

[0018] Among them, the local equalization circuit 13 can be composed of two transistors. The gates of the two transistors are used to receive the local equalization signal corresponding to the local equalization circuit 13, and the two transistors are both connected to a common voltage to control the connection or disconnection of the power supply terminal 12a and the ground terminal 12b of the amplification unit 12 to the same common voltage.

[0019] In some embodiments, refer to Figure 2, the first sense amplifier further includes a first local equalization circuit 131, and the second sense amplifier further includes a second local equalization circuit 132. The first local equalization circuit 131 is located between the first pull-up driving circuit 111 and the first amplifying circuit 121, and the second local equalization circuit 132 is located between the second pull-up driving circuit 112 and the second amplifying circuit 122. Among them, when taking the first pull-up driving circuit 111 and the second pull-up driving circuit 112 as the whole pull-up driving circuit 11, the first local equalization circuit 131 can be regarded as being located at the middle position on the side of the pull-up driving circuit 11 close to the first amplifying circuit 121, and the second local equalization circuit 132 can be regarded as being located at the middle position on the side of the pull-up driving circuit 11 close to the second amplifying circuit 122. The first local equalization circuit 131 and the second local equalization circuit 132 are axially symmetrically distributed with respect to the pull-up driving circuit 11.

[0020] Among them, the arrangement direction of the pull-up driving circuit 11 is perpendicular to the arrangement direction of the amplifying circuit 12, and the arrangement direction of the local equalization circuit 13 is parallel to the arrangement direction of the amplifying circuit 12. Refer to Figure 2 , the amplifier has a first direction D1 and a second direction D2 that are perpendicular to each other. The arrangement direction of the pull-up driving circuit 11 is the direction in which the first pull-up driving circuit 111 faces the second pull-up driving circuit 112, the arrangement direction of the amplifying circuit 12 is the arrangement direction in which the first amplifying circuit 121 faces the second amplifying circuit 122, the arrangement direction of the local equalization circuit 13 is the direction in which the first local equalization circuit 131 faces the second local equalization circuit 132, the arrangement directions of the amplifying circuit 12 and the local equalization circuit 13 are both the first direction D1, and the arrangement direction of the pull-up driving circuit 11 is the second direction D2.

[0021] In addition, the pull-up driving circuit 11 can be a transistor. The drain of the transistor is used to connect to the supply voltage VDD, and the gate is used to receive a control signal to turn on or off the source-drain of the transistor. Setting the arrangement direction of the local equalization circuit 13 perpendicular to the arrangement direction of the pull-up driving circuit 11 is beneficial to reserve more space for the pull-up driving circuit 11 in its own arrangement direction to fabricate a transistor with a wider gate width, thereby improving the conduction rate of the transistor and the voltage boosting rate of the power supply terminal 12a of the amplifying circuit 12, and further improving the read rate of the memory. It should be noted that the embodiments of the present application only illustrate the role of reserving space with the pull-up driving circuit 11 being a transistor. In other embodiments, the pull-up driving circuit 11 can also be composed of other functional components. Reserving more space in the arrangement direction of the pull-up driving circuit 11 can leave room for improving the performance of the pull-up driving circuit 11.

[0022] In some embodiments, refer to Figure 1, the amplifier further includes: a bit line equalization circuit 14, one end of which is connected to the bit line BL and the other end is connected to the complementary bit line BLB, for connecting the bit line BL and the complementary bit line BLB. Among them, the bit line equalization circuit 14 can be a transistor, and the gate of the transistor is used to receive the bit line equalization signal corresponding to the bit line equalization circuit 14 to control the connection or disconnection of the bit line pair BL / BLB; when the memory is in the standby state, the bit line equalization circuit 14 connects the bit line pair BL / BLB based on the bit line equalization signal to make the voltages of the bit line BL and the complementary bit line BLB equal.

[0023] In addition, the bit line equalization circuit 14 is often connected to the bit line pre-charge circuit, and the two work together to make the voltages of the bit line BL and the complementary bit line BLB in the standby state both at the reference voltage, such as VDD / 2. The bit line pre-charge circuit may include two transistors. The source of one transistor is connected to the bit line BL, and the source of the other transistor is connected to the complementary bit line BLB. The drains of the two transistors both receive the pre-charge voltage, and the gates of the two transistors both receive the bit line equalization signal. When the memory receives the bit line equalization signal, the bit line BL and the complementary bit line BLB are respectively charged through the pre-charge voltage. At this time, connecting the bit line BL and the complementary bit line BLB through the bit line equalization circuit 14 is beneficial to ensuring that the voltage values of the bit line BL and the complementary bit line BLB are equal and avoiding a voltage difference between the bit line BL and the complementary bit line BLB.

[0024] In some embodiments, referring to Figure 1 , the amplifier further includes: a column switch circuit 15, connected to the bit line BL and the complementary bit line BLB, and connected to the local input / output line LIO and the local complementary input / output line LIOB, for receiving the column select signal Ys, and connecting or disconnecting the local input / output line LIO and the bit line BL based on the column select signal Ys, and connecting or disconnecting the local complementary input / output line LIOB and the complementary bit line BLB based on the column select signal Ys.

[0025] Among them, the column switch circuit 15 includes a first transistor M1 and a second transistor M2. The first transistor M1 is used to connect the local input / output line LIO and the bit line BL, and the second transistor M2 is used to connect the local complementary input / output line LIOB and the complementary bit line BLB. The gates of the first transistor M1 and the second transistor M2 are used to receive the column select signal Ys. The column select signal Ys is controlled by a column decoder to selectively read out the minute voltage signals of the part of the bit line pairs actually needed connected to the activated word line. When the source-drain of the first transistor M1 and the second transistor M2 is turned on, the minute voltage signal amplified by the amplifier circuit 12 is transmitted to the local input / output line pair LIO / LIOB through the bit line pair BL / BLB.

[0026] The first transistor M1 and the second transistor M2 may be either PMOS transistors or NMOS transistors; illustratively, the first transistor M1 and the second transistor M2 are NMOS transistors, and the column selection signal Ys has an internal boost voltage.

[0027] In some embodiments, the amplifier further includes: an input-output equalization circuit 16, one end of which is connected to the local input-output line LIO, and the other end of which is connected to the local complementary input-output line LIOB, for connecting the local input-output line LIO and the local complementary input-output line LIOB. Similar to the function of the bit line equalization circuit 14, the input-output equalization circuit 16 connects or disconnects the local input-output line LIO and the local complementary input-output line LIOB based on the corresponding input-output equalization signal, so that the local input-output line LIO and the local complementary input-output line LIOB have the same voltage in the memory standby state.

[0028] Among them, reference Figure 2 The first sensitive amplifier further includes a first input-output balancing circuit 161, and the second sensitive amplifier further includes a second input-output balancing circuit 162. In the arrangement direction of the pull-up driving circuit, the first input-output balancing circuit 161, the first pull-up driving circuit 111, the second pull-up driving circuit 112, and the second input-output balancing circuit 162 are arranged in sequence. That is, the local balancing circuit 13 and the input-output balancing circuit 16 are located on different sides of the pull-up driving circuit 11.

[0029] In some embodiments, reference Figure 1 , the amplifier also includes: a precharge circuit 17, one end of which is connected to the local input-output line LIO, and the other end is connected to the local complementary input-output line LIOB, for precharging the local input-output line LIO and the local complementary input-output line LIOB. The precharge circuit 17 has a similar function to the bit line precharge circuit mentioned above, and the two can have a similar structure, that is, the source of one transistor is connected to the local input-output line LIO, the source of the other transistor is connected to the local complementary input-output line LIOB, the drains of the two transistors are connected and receive the precharge voltage, and the gates of the two transistors are used to receive the input-output equalization signal. Among them, the precharge voltage can be the power supply voltage VDD, that is, the pull-up drive circuit 11 is also connected to the precharge circuit 17 through the electrode line PCS.

[0030] In some embodiments, the first sense amplifier further includes a first pre-charge circuit 171 and a second pre-charge circuit 172, and the second sense amplifier further includes a third pre-charge circuit 173 and a fourth pre-charge circuit 174. In the arrangement direction of the amplifier circuit 12, the first pre-charge circuit 171 and the second pre-charge circuit 172 are located on opposite sides of the first input / output equalization circuit 161, and the third pre-charge circuit 173 and the fourth pre-charge circuit 174 are located on opposite sides of the second input / output equalization circuit 162.

[0031] According to the illustrated content, the first pre-charge circuit 171, the second pre-charge circuit 172, and the first input / output equalization circuit 161 are located on the same side of the first pull-up driving circuit 111. At the same time, to improve the regularity of the amplifier profile, in the first direction D1, the total width of the first pre-charge circuit 171, the second pre-charge circuit 172, and the first input / output equalization circuit 161 is less than or equal to the width of the first pull-up driving circuit 111; correspondingly, the third pre-charge circuit 173, the fourth pre-charge circuit 174, and the second input / output equalization circuit 162 are located on the same side of the second pull-up driving circuit 112. In the first direction D1, the total width of the third pre-charge circuit 173, the fourth pre-charge circuit 174, and the second input / output equalization circuit 162 is less than or equal to the width of the second pull-up driving circuit 112.

[0032] In some embodiments, the first sense amplifier further includes a fifth pre-charge circuit 175, and the second sense amplifier further includes a sixth pre-charge circuit 176. The fifth pre-charge circuit 175 is located between the first pull-up driving circuit 111 and the first amplifier circuit 121, and the sixth pre-charge circuit 176 is located between the second pull-up driving circuit 112 and the second amplifier circuit 122. According to the illustration, the above positional relationship can also be expressed as the fifth pre-charge circuit 175 is located between the second pull-up driving circuit 112 and the first amplifier circuit 121, and the sixth pre-charge circuit 176 is located between the first pull-up driving circuit 111 and the second amplifier circuit 122; or, considering the first pull-up driving circuit 111 and the second pull-up driving circuit 112 between adjacent amplifier circuits 12 as the overall pull-up driving circuit 11, the fifth pre-charge circuit 175 is located between the pull-up driving circuit 11 and the first amplifier circuit 121, and the sixth pre-charge circuit 176 is located between the pull-up driving circuit 11 and the second amplifier circuit 122. Among them, the arrangement direction of the fifth pre-charge circuit 175 and the sixth pre-charge circuit 176 is the first direction D1, which is the same as the arrangement direction of the local equalization circuit 13.

[0033] Further, the fifth pre-charge circuit 175 is located between the first pull-up driving circuit 111 and the corresponding first local equalization circuit 131, and the sixth pre-charge circuit 176 is located between the second pull-up driving circuit 112 and the corresponding second local equalization circuit 132. When considering the first pull-up driving circuit 111 and the second pull-up driving circuit 112 as a whole, the fifth pre-charge circuit 175 is located between the pull-up driving circuit 11 and the corresponding first local equalization circuit 131, and the sixth pre-charge circuit 176 is located between the pull-up driving circuit 11 and the corresponding second local equalization circuit 132.

[0034] In addition, the amplifier further includes: an equalization driving circuit 18, connected to the input / output equalization circuit 16 and the pre-charge circuit 17 respectively. The equalization driving circuit 18 is configured to output a local input / output equalization signal to the input / output equalization circuit 16 and the pre-charge circuit 17, so that the pre-charge circuit 17 charges the local input / output line LIO and the local complementary input / output line LIOB, and controls the voltage values of the local input / output line LIO and the local complementary input / output line LIOB to be equal through the input / output equalization circuit 16.

[0035] In some embodiments, the equalization driving circuit 18 is located between the first pull-up driving circuit 111 and the second pull-up driving circuit 112. It should be noted that different sense amplifiers may share the same equalization driving circuit 18 or have their own equalization driving circuits 18. If different sense amplifiers have their own equalization driving circuits 18, for example, the first sense amplifier has a first equalization driving circuit and the second sense amplifier has a second equalization driving circuit, then in some embodiments, both the first equalization driving circuit and the second equalization driving circuit are located between the first pull-up driving circuit 111 and the second pull-up driving circuit 112, and the arrangement directions of the first equalization driving circuit and the second equalization driving circuit can be perpendicular or parallel to the arrangement direction of the pull-up driving circuit 11.

[0036] In the embodiments of the present application, the first pull-up driving circuit and the second pull-up driving circuit are arranged between the first amplifying circuit and the second amplifying circuit, which is beneficial to making the number of like circuit devices between the first amplifying circuit and the second amplifying circuit an even number. The like circuit devices include the pull-up driving circuit and other connected circuit devices, such as the local equalization circuit. Setting the like circuit devices to an even number is beneficial to improving the layout, enhancing the symmetry of the layout, and improving the corresponding electrical performance.

[0037] The embodiments of the present application further provide a memory, including the amplifier according to any one of the above.

[0038] Reference Figure 3, the memory includes a plurality of memory banks 21 arranged in an array, the memory banks 21 are arranged along a first direction D1 and a second direction D2, a sub-word line driver SWD is provided between adjacent memory banks 21 arranged along the first direction D1, and a sense amplifier circuit 22 is provided between adjacent memory banks 21 arranged along the second direction D2, and a switching circuit SWC is provided between adjacent sense amplifier circuits 22 and adjacent sub-word line drivers SWD.

[0039] Reference Figure 1 and Figure 3 , Figure 1 As shown, the pull-up drive circuit 11, the local equalization circuit 13, the input / output equalization circuit 16, the pre-charge circuit 17, and the equalization drive circuit 18 are located Figure 3 inside the switching circuit SWC shown, Figure 1 the amplifier circuit shown is located Figure 3 inside the sense amplifier circuit 22 shown. That is to say, the above-mentioned sensitive amplifier includes at least part of the switching circuit SWC and part of the sense amplifier circuit 22. Since the local equalization circuit 13 and part of the pre-charge circuit 17 are located between the pull-up drive circuit 11 and the amplifier circuit 12, the switching circuit SWC presents a cross shape, and part of the switching circuit SWC extends into the sense amplifier circuit 22, or rather, part of the switching circuit SWC is located between adjacent memory banks 21 extending along the second direction D2. Setting part of the switching circuit SWC to extend into the sense amplifier circuit 22 is beneficial to reserve a larger adjustment space for the switching circuit SWC in the second direction D2, thereby improving the layout of the switching circuit SWC and the critical dimensions of the internal components of the switching circuit SWC, and further improving the electrical performance of the switching circuit SWC, such as the conduction rate.

[0040] Those of ordinary skill in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A memory, characterized in that, it includes: a plurality of memory banks arranged in an array, the memory banks are arranged along a first direction and a second direction, a sub-word line driver is provided between adjacent memory banks arranged along the first direction, an amplifier circuit is provided between adjacent memory banks arranged along the second direction, and a switching circuit is provided between adjacent amplifier circuits arranged along the first direction; the switching circuit includes a pull-up drive circuit, one end of the pull-up drive circuit is connected to a supply voltage, and the other end is connected to the power supply terminal of the amplifier circuit; the amplifier circuit includes a first amplifier circuit and a second amplifier circuit, the first amplifier circuit and the second amplifier circuit are arranged along the first direction and are arranged on opposite sides of the switching circuit, the pull-up drive circuit includes a first pull-up drive circuit and a second pull-up drive circuit, the first pull-up drive circuit and the first amplifier circuit belong to the first sense amplifier together, the second pull-up drive circuit and the second amplifier circuit belong to the second sense amplifier together, the first pull-up drive circuit and the second pull-up drive circuit are both located between the first amplifier circuit and the second amplifier circuit and are located between adjacent sub-word line drivers arranged along the second direction; the switching circuit further includes a local equalization circuit, one end is connected to the power supply terminal of the amplifier circuit, and the other end is connected to the ground terminal of the amplifier circuit for connecting the power supply terminal and the ground terminal; the first sense amplifier further includes a first local equalization circuit, the second sense amplifier further includes a second local equalization circuit, the first local equalization circuit and the first amplifier circuit are jointly provided between two adjacent memory banks arranged along the second direction, and the second local equalization circuit and the second amplifier circuit are jointly provided between another two adjacent memory banks arranged along the second direction; the arrangement directions of the first pull-up drive circuit and the second pull-up drive circuit are perpendicular to the arrangement directions of the first local equalization circuit and the second local equalization circuit.

2. The memory according to claim 1, characterized in that, a column switching circuit, connected to a bit line and a complementary bit line, and connected to a local input / output line and a local complementary input / output line, for receiving a column selection signal and connecting or disconnecting the local input / output line and the bit line based on the column selection signal, and connecting or disconnecting the local complementary input / output line and the complementary bit line based on the column selection signal.

3. The memory according to claim 2, characterized in that, the column switching circuit includes a first transistor and a second transistor, the first transistor is used to connect the local input / output line and the bit line, the second transistor is used to connect the local complementary input / output line and the complementary bit line, and the gates of the first transistor and the second transistor receive the column selection signal.

4. The memory according to claim 2, characterized in that, it further includes: A precharge circuit, one end of which is connected to the local input / output line and the other end of which is connected to the local complementary input / output line, is configured to precharge the local input / output line and the local complementary input / output line.

5. The memory according to claim 4, wherein, it further comprises: An input / output equalization circuit, one end of which is connected to the local input / output line and the other end of which is connected to the local complementary input / output line, is configured to connect the local input / output line and the local complementary input / output line.

6. The memory according to claim 5, wherein, the input / output equalization circuit includes a first input / output equalization circuit and a second input / output equalization circuit. The first sense amplifier further includes the first input / output equalization circuit, and the second sense amplifier further includes the second input / output equalization circuit. In the second direction, the first input / output equalization circuit, the first pull-up drive circuit, the second pull-up drive circuit, and the second input / output equalization circuit are arranged in sequence.

7. The memory according to claim 6, wherein, the precharge circuit includes a first precharge circuit, a second precharge circuit, a third precharge circuit, and a fourth precharge circuit. The first sense amplifier further includes the first precharge circuit and the second precharge circuit, and the second sense amplifier further includes the third precharge circuit and the fourth precharge circuit. In the first direction, the first precharge circuit and the second precharge circuit are located on opposite sides of the first input / output equalization circuit, and the third precharge circuit and the fourth precharge circuit are located on opposite sides of the second input / output equalization circuit.

8. The memory according to claim 4, wherein, at least a part of the precharge circuit is disposed between adjacent memory banks arranged along the second direction.

9. The memory according to claim 8, wherein, the precharge circuit includes a fifth precharge circuit and a sixth precharge circuit. The first sense amplifier further includes the fifth precharge circuit, and the second sense amplifier further includes the sixth precharge circuit. The fifth precharge circuit and the first amplifier circuit are jointly disposed between two adjacent memory banks arranged along the second direction, and the sixth precharge circuit and the second amplifier circuit are jointly disposed between another two adjacent memory banks arranged along the second direction.

10. The memory according to claim 1, wherein, The amplifier circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The drains of the first PMOS transistor and the second PMOS transistor are connected to the power supply terminal. The sources of the first NMOS transistor and the second NMOS transistor are connected to the ground terminal of the amplifier circuit. The gates of the first PMOS transistor, the first NMOS transistor, the source of the second PMOS transistor, and the drain of the second NMOS transistor are connected to the bit line. The gates of the second PMOS transistor, the second NMOS transistor, the source of the first PMOS transistor, and the drain of the first NMOS transistor are connected to the complementary bit line.

11. The memory according to claim 1, wherein, further comprising: a bit line equalization circuit, having one end connected to the bit line and the other end connected to the complementary bit line, for connecting the bit line and the complementary bit line.

12. The memory according to claim 1, wherein, further comprising: an equalization driving circuit, connected to the input / output equalization circuit and the pre-charge circuit respectively, and the equalization driving circuit is located between the first pull-up driving circuit and the second pull-up driving circuit.

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