Charge domain memory calculation circuit and memory calculation circuit with positive and negative number calculation function

Abstract

The present invention relates to a charge domain in-memory calculation circuit and a storage calculation circuit with positive and negative number calculation functions. The charge domain in-memory calculation circuit includes four storage units T1 to T4 for storing weight data, a storage unit TSIGN for storing data representing a sign bit, a multiplication accumulation module MAC and a precharge module C‑PRE. When the charge domain in-memory calculation circuit performs a signed multiplication operation, the voltage signal of the external four-bit weight data is input into the multiplication accumulation module MAC through the precharge module C‑PRE after the sign bit operation, and then the voltage signal of the four-bit weight stored in T1 to T4 is input into the multiplication accumulation module MAC, and Vsum[3] to Vsum[0] output the voltage signal representing the calculation result of the multiplication accumulation module MAC. The present invention realizes highly parallel data input on the basis of meeting the accuracy, and meets the requirements of multi-bit signed bit multiplication operation.

Description

Technical Field

[0001] The present invention relates to the field of in-memory computing technology, and in particular to a charge domain in-memory computing circuit and a memory computing circuit with positive and negative number computing functions based on the charge domain in-memory computing circuit. Background Art

[0002] Convolutional Neural Networks (CNNs) play a vital role in various intelligent recognition tasks, such as image recognition, speech recognition, and natural language processing. Since its introduction, the von Neumann architecture has shaped the fundamental architecture of computers and remains in use today. In the traditional von Neumann architecture, instructions and data are first written into memory. Then, after receiving instructions via a control bus, the control unit sends the corresponding data from memory via a data bus to the corresponding processing unit for computation. The results are then written back to the corresponding unit in memory via the data bus. This approach limits data processing speed, and with the introduction of more complex algorithms, the von Neumann architecture is struggling to handle complex, data-intensive computations.

[0003] To address the "memory wall" problem posed by the von Neumann architecture, researchers have proposed the concept of in-memory computing, which performs the logical operations required for intensive data within the memory, effectively reducing the power consumption and latency associated with data migration. Furthermore, because the memory array is a highly reusable structure, large-scale parallel computing can be performed within the memory, thereby increasing computing speed, reducing the number of memory accesses during the computation process, and reducing the area of ​​the processor's logic units, leaving more space for complex operations.

[0004] In-memory computing is carried out using various storage structures, such as SRAM and RRAM. SRAM is widely used in in-memory computing due to its fast data read speed and good compatibility with advanced logic processes. Existing in-memory multiplication methods include current-domain in-memory computing (IMC), which offers higher computational efficiency than digital technologies and can handle multi-bit multiplication operations. However, current-domain in-memory computing operates on unsigned operands and cannot handle multiplication operations with signed operands. This is especially true when both the stored data and the external data have signed bits. The final result cannot accurately reflect the sign bit of the result, resulting in computational errors. Summary of the Invention

[0005] Based on this, it is necessary to provide a charge domain in-memory calculation circuit and a storage calculation circuit with positive and negative number calculation functions based on the charge domain in-memory calculation circuit to address the problem that the existing current domain in-memory calculation method cannot meet the multiplication operation between signed operands.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] A charge domain in-memory computing circuit includes four storage units T1 to T4 for storing weight data, a storage unit TSIGN for storing data representing a sign bit, a multiplication-accumulation module MAC, and a precharge module C-PRE. The sign bit can be a positive sign bit or a negative sign bit.

[0008] The signal outputs of T1 to T4 are connected to the four signal inputs of the multiplication-accumulation module MAC. TSIGN is used to control the sign of the voltage signal input from the precharge module C-PRE to the multiplication-accumulation module MAC. The four result outputs of the multiplication-accumulation module MAC are connected to the output signal lines Vsum[3] to Vsum[0] in a one-to-one correspondence.

[0009] When the charge domain memory calculation circuit performs a signed multiplication operation, the voltage signal of the signed external four-bit weight data and the voltage signal of the sign bit TSIGN of the pre-stored internal weight data are input into the pre-charge module C-PRE, and the voltage signal of the external four-bit weight after the sign bit operation is input into the multiplication accumulation module MAC through the pre-charge module C-PRE, and then the voltage signal of the four-bit weight stored in T1~T4 is input into the multiplication accumulation module MAC, and Vsum[3]~Vsum[0] output the voltage signal representing the operation result of the multiplication accumulation module MAC.

[0010] Furthermore, the multiplication and accumulation module MAC includes NMOS transistors M6, M8, M10, M12, PMOS transistors M7, M9, M11, M13, calculation capacitors C1, C2, C3, C4 and transmission gates W1, W2, W3, W4.

[0011] The drains of M6, M8, M10, and M12 are connected to the data outputs of T4, T3, T2, and T1 as the signal inputs of the multiplication and accumulation module MAC. The sources of M6, M8, M10, and M12 are connected to the gates of M7, M9, M11, and M13. The gates of M6, M8, M10, and M12 are controlled by the control signal line CAL. The two ends of C1, C2, C3, and C4 are connected to the signal lines V1 and V2 respectively. The source and drain of M7 are connected to the two ends of C1 respectively. The source and drain of M9 are connected to the two ends of C2 respectively. The source and drain of M11 are connected to the two ends of C3 respectively. The source and drain of M13 are connected to the two ends of C4 respectively. The two ends of C2 and C4 are connected to the output signal lines Vsum[3] to Vsum[1] respectively as the result outputs of the multiplication and accumulation module MAC. The capacitance values ​​of C1 and C3 are the same, the capacitance values ​​of C2 and C4 are the same, and the capacitance values ​​of C1 and C3 are twice the capacitance values ​​of C2 and C4.

[0012] Signal lines V1 and V2 are connected to transmission gates W1, W2, W3, and W4. W1 is used to control the on-off between C1 and C2, W2 is used to control the on-off between C2 and Vsum[3] and Vsum[2], W3 is used to control the on-off between C3 and C4, and W4 is used to control the on-off between C4 and Vsum[1] and Vsum[0].

[0013] Furthermore, the pre-charge module C-PRE includes six NMOS transistors M1 to M5 and M14. The drain of M14 is connected to signal line V1, and the source of M14 is connected to the drains of M1 and M2. The drain of M5 is connected to signal line V2, and the source of M5 is connected to the drains of M3 and M4. The gates of M14 and M5 are connected to the control signal line PRE.

[0014] The sources of M1 and M3 are connected to the external four-bit weighted data voltage signal Vdac, and the sources of M2 and M4 are connected to 1 / 2 VDD. The gates of M2 and M3 are connected to the signal output line of TSIGN. The gates of M1 and M4 are connected to the inverted signal output line of TSIGN.

[0015] Furthermore, memory cells T1-T4 and TSIGN all employ 6T memory cells, comprising six transistors. The 6T memory cell includes two PMOS transistors, P1 and P2, and four NMOS transistors, N1, N2, N3, and N4. P1 and N1 form an inverter structure, P2 and N2 form another inverter structure, and N3 and N4 serve as transmission transistors. The sources of P1 and P2 are connected to VDD, while the sources of NM1 and NM2 are grounded. The drain of P1, the drain of N1, the gate of P2, and the gate of N2 are connected to form the storage node Q and are also connected to the drain of N3. The drain of P2, the drain of N2, the gate of P1, and the gate of N1 are connected to form the storage node QB and are also connected to the drain of N4. The gates of N3 and N4 are connected to the word line WL. The source of N3 is connected to the bit line BL, and the source of N4 is connected to the bit line BLB. The bit line BL serves as the signal output terminal of the 6T memory cell.

[0016] Furthermore, the sign of the multiplication result of the charge domain memory calculation circuit is determined by the stored data of the storage unit TSIGN and the voltage signal Vdac. If the data stored in the storage unit TSIGN is "1", it means that the sign bit of the weight data stored in the storage units T4 to T1 is a negative sign bit. If the data stored in the storage unit TSIGN is "0", it means that the sign bit of the weight data stored in the storage units T4 to T1 is a positive sign bit.

[0017] When the data stored in the memory cell TSIGN is "1", the voltage difference between the signal lines V1 and V2 is V1-V2=1 / 2VDD-Vdac. When the data stored in the memory cell TSIGN is "0", the voltage difference between the signal lines V1 and V2 is V1-V2=Vdac-1 / 2VDD.

[0018] Furthermore, the multiplication calculation implemented by the charge domain memory calculation circuit includes a pre-charge stage, a cumulative multiplication stage, and a charge sharing stage performed in sequence. The pre-charge stage is used to pre-charge the voltage signal of the external four-bit weight data to both ends of the calculation capacitors C1, C2, C3, and C4. The cumulative multiplication stage is used to multiply the stored weight data with the external four-bit weight data. The charge sharing stage is used to charge share the multiplication results of T4, T3 and T2, T1 with the external four-bit weight data to realize weighted and accumulated operations.

[0019] Furthermore, the specific operations of the pre-charge stage are as follows:

[0020] A high-level signal is input to M14 and M5 via the control signal line PRE, and a high-level signal is also input to transmission gates W1 and W3. A low-level signal is input to M6, M8, M10, and M12 via the control signal line CAL, and a low-level signal is also input to transmission gates W2 and W4. This calculates that the voltages across capacitors C1, C2, C3, and C4 are equal to the voltages of signal lines V1 and V2, respectively.

[0021] Furthermore, the specific operations of the accumulation stage are as follows:

[0022] A low-level signal is input to M14 and M5 via the control signal line PRE. A high-level signal is input to M6, M8, M10, and M12 via the control signal line CAL, and a low-level signal is input to transmission gates W1-W4. This disconnects the computational capacitors C1, C2, C3, and C4 from one another and connects them to the corresponding storage cells T1-T4.

[0023] Furthermore, the specific operations of the charge sharing stage are as follows:

[0024] A low-level signal is input to M6, M8, M10, and M12 through the control signal line CAL, and a high-level signal is input to the transmission gates W1 to W4. This connects the calculation capacitors C1, C2, C3, and C4, and disconnects them from the storage units T1 to T4. The voltage difference between the output signal lines Vsum[3] and Vsum[2] represents the multiplication result of T4 and T3 with the external four-bit weight data. The voltage difference between the output signal lines Vsum[1] and Vsum[0] represents the multiplication result of T2 and T1 with the external four-bit weight data.

[0025] The present invention also relates to a storage and calculation circuit with positive and negative number calculation functions, including a storage and calculation array, an output signal line group, a digital-to-analog conversion module, a timing control module, an analog-to-digital conversion module, and a digital weighting and accumulation module.

[0026] The storage and computation array is composed of a plurality of identical storage and computation units in an N×M array format, where N represents the number of rows and M represents the number of columns of the storage and computation array.

[0027] The output signal line group includes M groups of output signal lines Vsum[3] to Vsum[0], and each storage and calculation unit in each column is connected to the same group of output signal lines Vsum[3] to Vsum[0].

[0028] The digital-to-analog conversion module is used to convert the signed external four-bit weight data into the corresponding analog voltage signal and input it into any storage and calculation unit in the storage and calculation array.

[0029] The timing control module is used to generate control signals required for computing operations.

[0030] The analog-to-digital conversion module is used to convert the analog voltage signal output by any column in the storage and calculation array through the output signal line group into a corresponding digital signal.

[0031] The digital weighting and accumulation module is used to perform weighting and accumulation operations on the digital signal output by the analog-to-digital conversion module, and then output the digital quantity result of the multiplication operation between the storage and calculation unit in any column and the external four-bit weight data.

[0032] In particular, the storage and calculation unit adopts the circuit structure of the aforementioned charge domain memory calculation circuit and realizes the complete functions of the circuit.

[0033] The technical solution provided by the present invention has the following beneficial effects:

[0034] The charge domain in-memory calculation circuit designed by the present invention can realize the multiplication operation of 5-bit stored weight data including the sign bit and the external input 4-bit weight data; the in-memory multiplication operation is realized through digital-to-analog conversion, and highly parallel data input is achieved on the basis of meeting the accuracy, which has great advantages in energy efficiency and calculation cycle, and meets the requirements of multi-bit multiplication operation with a signed bit. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a circuit structure diagram of a charge domain memory computing circuit according to embodiment 1 of the present invention;

[0036] Figure 2 Based on Figure 1 Circuit structure diagram of 6T memory cell;

[0037] Figure 3 1 is an overall structural diagram of a storage and calculation circuit with positive and negative number operation functions according to embodiment 2 of the present invention;

[0038] Figure 4 Based on Figure 3 The circuit structure diagram of the digital-to-analog conversion module;

[0039] Figure 5 Based on Figure 1 Figure 1. Timing diagram of the control signals required to perform a charge domain multiplication operation with the internally stored weight data as “1010”. DETAILED DESCRIPTION

[0040] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0041] Example 1

[0042] See also Figure 1 This embodiment introduces a charge domain in-memory computing circuit, comprising four memory cells T1-T4 for storing weight data, a memory cell TSIGN for storing data representing a sign bit, a multiplication-accumulation module MAC, and a precharge module C-PRE. The sign bit can be a positive sign bit or a negative sign bit.

[0043] The signal outputs of T1 to T4 are connected to the four signal inputs of the multiplication-accumulation module MAC. TSIGN is used to control the sign of the voltage signal input from the precharge module C-PRE to the multiplication-accumulation module MAC. The four result outputs of the multiplication-accumulation module MAC are connected to the output signal lines Vsum[3] to Vsum[0].

[0044] When the charge domain memory calculation circuit performs a signed multiplication operation, the voltage signal of the signed external four-bit weight data and the voltage signal of the sign bit TSIGN of the pre-stored internal weight data are input into the pre-charge module C-PRE, and the voltage signal of the external four-bit weight after the sign bit operation is input into the multiplication accumulation module MAC through the pre-charge module C-PRE, and then the voltage signal of the four-bit weight stored in T1~T4 is input into the multiplication accumulation module MAC, and Vsum[3]~Vsum[0] output the voltage signal representing the operation result of the multiplication accumulation module MAC.

[0045] Based on the above circuit structure, please refer to Figure 1 . The data stored in the storage unit TSIGN represents the sign bit of the internally stored weight data, and is placed in the first column. If the data stored in the storage unit TSIGN is "1", it indicates that the sign bit of the internally stored weight data is a negative number. If the data stored in the storage unit TSIGN is "0", it indicates that the sign bit of the internally stored weight data is a positive number. The four-bit internally stored weight data for multiplication with the external weight data is stored in the storage units T4 to T1 in sequence from high to low. The implementation principle of the multiplication operation is to first multiply each bit of the internally stored weight data with the external four-bit weight data, and finally perform weighted sum accumulation to obtain the final operation result.

[0046] To facilitate the further calculation circuit of the charge domain memory of this embodiment, the following is combined with Figure 1 The specific structure of each module and storage unit is described in detail.

[0047] The multiplication-accumulation module MAC includes NMOS transistors M6, M8, M10, and M12; PMOS transistors M7, M9, M11, and M13; computation capacitors C1, C2, C3, and C4; and transmission gates W1, W2, W3, and W4. The drains of M6, M8, M10, and M12, serving as the signal inputs of the multiplication-accumulation module MAC, are connected to the data outputs of T4, T3, T2, and T1. The sources of M6, M8, M10, and M12 are connected to the gates of M7, M9, M11, and M13. The gates of M6, M8, M10, and M12 are controlled by a control signal line, CAL. The two ends of C1, C2, C3, and C4 are connected to the signal lines V1 and V2 respectively. The source and drain of M7 are connected to the two ends of C1 respectively. The source and drain of M9 are connected to the two ends of C2 respectively. The source and drain of M11 are connected to the two ends of C3 respectively. The source and drain of M13 are connected to the two ends of C4 respectively. The two ends of C2 and C4 are connected to the output signal lines Vsum[3] to Vsum[1] respectively as the result output ends of the multiplication and accumulation module MAC. The capacitance values ​​of C1 and C3 are the same. The capacitance values ​​of C2 and C4 are the same. The capacitance values ​​of C1 and C3 are twice the capacitance values ​​of C2 and C4. Signal lines V1 and V2 are connected to transmission gates W1, W2, W3, and W4. W1 is used to control the on-off between C1 and C2, W2 is used to control the on-off between C2 and Vsum[3] and Vsum[2], W3 is used to control the on-off between C3 and C4, and W4 is used to control the on-off between C4 and Vsum[1] and Vsum[0].

[0048] The precharge module C-PRE includes six NMOS transistors, M1 to M5, and M14. M14's drain is connected to signal line V1, and its source is connected to the drains of M1 and M2. M5's drain is connected to signal line V2, and its source is connected to the drains of M3 and M4. The gates of M14 and M5 are connected to the control signal line PRE. The sources of M1 and M3 are connected to the external four-bit weighted data voltage signal Vdac, while the sources of M2 and M4 are connected to 1 / 2 VDD. The gates of M2 and M3 are connected to the TSIGN signal output line. The gates of M1 and M4 are connected to the inverted signal output line of TSIGN.

[0049] The memory cells T1 to T4 and TSIGN all use 6T memory cells containing 6 transistors. Figure 2 , Figure 2The circuit structure of a 6T memory cell is shown. The 6T memory cell includes two PMOS transistors, P1 and P2, and four NMOS transistors, N1, N2, N3, and N4. P1 and N1 form an inverter structure, P2 and N2 form another inverter structure, and N3 and N4 serve as transmission transistors. The sources of P1 and P2 are both connected to VDD, while the sources of NM1 and NM2 are both grounded. The drain of P1, the drain of N1, the gate of P2, and the gate of N2 are connected to form the storage node Q and are also connected to the drain of N3. The drain of P2, the drain of N2, the gate of P1, and the gate of N1 are connected to form the storage node QB and are also connected to the drain of N4. The gates of N3 and N4 are connected to the word line WL. The source of N3 is connected to the bit line BL, and the source of N4 is connected to the bit line BLB. The bit line BL serves as the signal output terminal of the 6T memory cell.

[0050] Based on the specific circuit structure of the charge domain memory computing circuit, combined with Figure 1 It can be seen that the calculation results of the storage units T4, T3 and the calculation capacitors C1, C2 are output by the output signal lines Vsum[3] and Vsum[2]. On the basis that the capacitance value of C1 is twice the capacitance value of C2, T4, M6, M7, and C1 constitute a high-order multiplication and accumulation unit M-MAC, and T3, M8, M9, and C2 constitute a low-order multiplication and accumulation unit L-MAC. The multiplication result of the stored weight data of T4 and T3 and the external weight data is output through Vsum[3] and Vsum[2]. That is, the multiplication result of the stored weight data of T4 and T3 and the external weight data can be known through the voltage difference between Vsum[3] and Vsum[2].

[0051] The calculation results of storage units T2, T1 and calculation capacitors C3, C4 are output via output signal lines Vsum[1], Vsum[0]. Based on the fact that the capacitance value of C3 is twice that of C4, T2, M10, M11, and C3 form a high-order multiplication and accumulation unit M-MAC, and T1, M12, M14, and C4 form a low-order multiplication and accumulation unit L-MAC. The multiplication results of the stored weight data of T2 and T1 and the external weight data are output via Vsum[1] and Vsum[0]. That is, the multiplication results of the stored weight data of T2 and T1 and the external weight data can be known through the voltage difference between Vsum[1] and Vsum[0].

[0052] Since M1 and M3 are connected to Vdac, and M2 and M4 are connected to 1 / 2VDD, the calculation of the sign bit is explained below. Figure 1 It can be seen that when the data stored in the memory cell TSIGN is "1", the voltage difference between the signal lines V1 and V2 is V1-V2=1 / 2VDD-Vdac. When the data stored in the memory cell TSIGN is "0", the voltage difference between the signal lines V1 and V2 is V1-V2=Vdac-1 / 2VDD.

[0053] For the positive and negative sign bits of the external weight data, 1 / 2VDD is used as the reference point. If Vdac>1 / 2VDD, it indicates that the sign bit of the external weight data is positive. If Vdac<1 / 2VDD, it indicates that the sign bit of the external weight data is negative. The principle of sign bit operation can be seen in the following table:

[0054] Logic table for the operation of the sign bit of external weight data and internally stored weight data

[0055]

[0056]

[0057] As shown in the table above, when the data stored in TSIGN is "1" and Vdac > 1 / 2VDD, V1-V2 = 1 / 2VDD-Vdac < 0, and the sign bit of the final calculation result is negative. When the data stored in TSIGN is "1" and Vdac < 1 / 2VDD, V1-V2 = 1 / 2VDD-Vdac > 0, and the sign bit of the final calculation result is positive. When the data stored in TSIGN is "0" and Vdac > 1 / 2VDD, V1-V2 = Vdac-1 / 2VDD > 0, and the sign bit of the final calculation result is positive. When the data stored in TSIGN is "0" and Vdac < 1 / 2VDD, V1-V2 = Vdac-1 / 2VDD < 0, and the sign bit of the final calculation result is negative.

[0058] Therefore, the pre-charge module C-PRE input signal includes the data stored in Vdac and TSIGN, and can determine the charge value pre-charged to the calculation capacitor based on the input Vdac and the sign bit data stored in TSIGN, thereby determining the sign corresponding to the calculation result.

[0059] The multiplication operation of the charge domain memory calculation circuit of this embodiment is described in conjunction with the calculation logic of the sign bit. The charge domain multiplication operation includes three stages: the pre-charge stage, the cumulative multiplication stage, and the charge sharing stage. The specific operations of each stage are described in detail below:

[0060] 1. Pre-charge stage

[0061] Set the control signal line PRE, transmission gates W1 and W3 signals to a high level, and the control signal line CAL, transmission gates W2 and W4 to a low level. Since the transmission gates W1 to W4 are turned on at a high level and turned off at a low level, the signal lines V1 and V2 are connected to the pre-charge module C-PRE, and the analog voltage signal of the external weight data is transmitted to V1 and V2. V1 and V2 are disconnected from the output signal lines Vsum[3] to Vsum[0] and the storage units T1 to T4. At this time, the voltages across the capacitors C1 to C4 are calculated to be the voltages of V1 and V2, respectively, achieving the pre-charge purpose.

[0062] 2. Multiplication stage

[0063] Pull the control signal line PRE low to disconnect the pre-charge module C-PRE. Set W1, W2, W3, and W4 to a low level and pull the CAL signal high. At this time, C1 is connected to T4, C2 is connected to T3, C3 is connected to T2, and C4 is connected to T1. C1-C4 are disconnected from each other. At this time, the voltage difference between C1-C4 represents the multiplication result of the external weight data and the data stored in the storage unit.

[0064] 3. Charge sharing stage: After completing the accumulation stage, the calculation capacitors C1~C4 store different calculation voltage signals, set W1, W2, W3, and W4 to high levels, and pull the control signal line CAL low. At this time, the multiplication accumulation module MAC is disconnected from the storage units T1~T4, and V1, V2 are connected to Vsum[3]~Vsum[0] to perform charge sharing operations, realizing the high-bit weighting and accumulation operations of partial multiplication in the analog domain.

[0065] In order to further understand the calculation principle of the charge domain memory calculation circuit of this embodiment, specific numerical values ​​are used for explanation below.

[0066] First, the analog logic of the external weight data is explained. Taking 1 / 2VDD as the analog value of 0, the value increases by 1 for every increase of 1 / 16VDD, and decreases by 1 for every decrease of 1 / 16VDD. Therefore, the value above 1 / 2VDD is positive, and the value below 1 / 2VDD is negative. Therefore, the input range of the external weight data is -7 to 7.

[0067] Take the external input weight data as +5 and the internal storage weight data as -6 as an example. +5 is converted to analog quantity as 13 / 16VDD, and the binary data corresponding to the internal storage weight data is 11010, so it is stored in the corresponding storage unit. The first is the SIGN bit, "1" indicates that the data is a negative number, and the remaining four bits of weight data W[3]W[2]W[1]W[0] are 1010 respectively. "1" is stored in the storage unit TSIGN, the weight data W[3]=1 is stored in the storage unit T4, the weight data W[2]=0 is stored in the storage unit T3, the weight data W[1]=1 is stored in the storage unit T2, and the weight data W[0]=0 is stored in the storage unit T1.

[0068] When performing precharge operation, PRE, W1, and W3 signals are set to high levels, CAL, W2, and W4 are set to low levels, and the voltage difference between V1 and V2 is V1-V2=1 / 2VDD-Vdac=-5 / 16VDD.

[0069] During the accumulation phase, W1, W2, W3, and W4 are set to a low level, and the CAL signal is pulled high. The weighted data bits W[3] and W[2] form one group, and W[1] and W[0] form another group. When the stored weighted data bit is 0, the two ends of the capacitor are short-circuited, making the voltage difference between the capacitors approximately 0. When the stored weighted data bit is 1, the voltage difference between the capacitors is approximately equal to the voltage difference between V1 and V2, that is, -5 / 16VDD. At this stage, the input analog quantity and the weighted data W[3], W[2], W[1], and W[0] are multiplied by -5 / 16VDD, 0, and -5 / 16VDD, 0, respectively. Therefore, the multiplication of the data bit and the analog signal is achieved.

[0070] During the charge sharing phase, W1, W2, W3, and W4 are set to high levels, and the CAL signal is pulled low to perform charge sharing operations, thereby implementing partial multiplication and high-order weighting and accumulation operations in the analog domain. The formula for the entire calculation process is equivalent to:

[0071] Vsum[3]-Vsum[2]=2×W[3]×(Vdac-1 / 2VDD)+W[2]×(Vdac-1 / 2VDD),

[0072] Vsum[1]-Vsum[0]=2×W[1]×(Vdac-1 / 2VDD)+W[0]×(Vdac-1 / 2VDD).

[0073] The final result can be weighted and accumulated in the digital domain to obtain the final calculated value. The calculation operation formula in the digital domain is equivalent to:

[0074] Vsum=4×(Vsum[3]-Vsum[2])+(Vsum[1]-Vsum[0]).

[0075] Therefore, it implements the multiplication and accumulation calculation of signed 4-bit external weight data and 5-bit weight including the sign bit. It achieves highly parallel data input, has great advantages in energy efficiency and computing cycle, and meets the needs of multi-bit signed multiplication operations.

[0076] Example 2

[0077] See also Figure 3 , Figure 3 This embodiment introduces a storage circuit with positive and negative number operation functions, including a storage array, an output signal line group, a digital-to-analog conversion module, a timing control module, an analog-to-digital conversion module, and a digital weighting and accumulation module.

[0078] The storage and computation array is composed of a plurality of identical storage and computation units in an N×M array format, where N represents the number of rows and M represents the number of columns of the storage and computation array.

[0079] The output signal line group includes M groups of output signal lines Vsum[3] to Vsum[0], and each storage and calculation unit in each column is connected to the same group of output signal lines Vsum[3] to Vsum[0].

[0080] The digital-to-analog conversion module is used to convert the signed external four-bit weighted data into a corresponding analog voltage signal and input it into any storage and computing unit in the storage and computing array. The timing control module is used to generate the control signals required for the computing operation. The analog-to-digital conversion module is used to convert the analog voltage signal output by any column in the storage and computing array through the output signal line group into a corresponding digital signal. The digital weighting and accumulation module is used to perform weighted and accumulation operations on the digital signals output by the analog-to-digital conversion module, and then output the digital value result of the multiplication operation between the storage and computing unit in any column and the external four-bit weighted data.

[0081] Among them, the storage and calculation unit adopts the circuit structure of the aforementioned charge domain memory calculation circuit and realizes the complete functions of the circuit.

[0082] See below Figure 4 , the structure of the digital-to-analog conversion module DAC is described in detail. Referring to the conversion logic of the external weight data in Example 1, the digital-to-analog conversion module includes four capacitors, C X 、4C X , 2C X 、C X , three switch tubes SW2, SW1, SW0 and a PMOS tube Pr. Among them, C X 、4C X , 2C X 、C XOne end of the C is connected together and serves as the output end of the analog voltage corresponding to the external weight data, that is, the output Vdac. X The other end is connected to 1 / 2VDD, 4C X , 2C X 、C X The other end is connected to one end of SW2, SW1, and SW0 respectively. The other end of SW2, SW1, and SW0 is connected to VDD, 1 / 2VDD, or VSS. The connection object is determined according to the switching of SW2, SW1, and SW0. The source of Pr is connected to VSS, and the drain is connected to C X 、4C X , 2C X 、C X The common ends are connected and the gate is controlled by Rstn.

[0083] The digital-to-analog conversion module (DAC) converts signed digital inputs into analog quantities. Before the digital signal arrives, Rstn is set low, and all switches are set to VDD / 2. At this point, the corresponding voltage of Vdac is approximately VDD / 2. When the digital signal arrives, Rstn is pulled high, and the DAC control circuit controls the SW0-SW2 voltage switches to convert the digital signal into an analog signal. For example, if the input signal is 0, it converts to a four-bit binary value of 0000, and the corresponding analog signal is VDD / 2. SW0-SW2 are connected to VDD / 2, and Vdac = 1 / 2VDD. If the input signal is +5, it converts to a digital value of 0101. SW[0] and SW[2] are set to VDD, and the digital-to-analog conversion result is approximately 13 / 16VDD. If the input signal is -5, it converts to a digital value of -0101, and the digital-to-analog conversion result is approximately 3 / 16VDD. The output of the DAC module is input to the precharge module PRE.

[0084] In this embodiment, every five storage columns form a block. The first column of each block stores the SIGN bit (SIGN is 1, the weight is negative. SIGN is 0, the weight is positive), and the other columns store data bits (decreasing from left to right). During the convolutional layer calculation process of the neural network, the storage method of the weight needs to be determined according to the size of the convolution kernel. For example, for a 3*3*3 convolution kernel, it is necessary to activate an array of three blocks to participate in the convolution layer operation.

[0085] In the CNN convolution layer, each block corresponds to a convolution kernel, and the trained weight data is stored in each column of storage units from high to low. The entire circuit is set to calculation mode, and the specific operation method of multiplication calculation is the same as that of Example 1.

[0086] When performing charge sharing operations, partial multiplication is performed in the analog domain to perform high-order weighting and accumulation operations. The formula for the entire calculation process is equivalent to:

[0087]

[0088]

[0089] Among them, n is the size of the convolution kernel, i refers to the specific row involved in the multiplication operation, and the value range of i is 1 <i<N。

[0090] All of the above calculations are implemented in the charge domain, generating analog quantities. The corresponding digital quantities are quantized using a successive approximation ADC, and weighted and accumulated in the digital domain to obtain the final calculated value. The calculation formula in the digital domain is equivalent to:

[0091] Vsum=4×(Vsum[3]-Vsum[2])+(Vsum[1]-Vsum[0]).

[0092] This embodiment has the same beneficial effects as embodiment 1. At the same time, in the array constructed on the basis of embodiment 1, full array operations can be performed to realize multiplication and accumulation calculations of signed 4-bit external weight data and 5-bit weight including the sign bit.

[0093] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The above embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A charge domain memory computing circuit, characterized in that: It includes four storage units T1 to T4 for storing weight data, a storage unit TSIGN for storing data representing a sign bit, a multiplication and accumulation module MAC and a precharge module C-PRE; wherein the sign bit includes a positive sign bit or a negative sign bit; The signal output terminals of T1 to T4 are connected to the four signal input terminals of the multiplication and accumulation module MAC. TSIGN is used to control the sign bit of the voltage signal input from the pre-charge module C-PRE to the multiplication and accumulation module MAC. The four result output terminals of the multiplication and accumulation module MAC are connected to the output signal lines Vsum[3] to Vsum[0] in a one-to-one correspondence. When the charge domain memory calculation circuit performs a signed multiplication operation, the voltage signal of the signed external four-bit weight data and the voltage signal of the sign bit TSIGN of the pre-stored internal weight data are input into the pre-charge module C-PRE, and the voltage signal of the external four-bit weight after the sign bit operation is input into the multiplication and accumulation module MAC through the pre-charge module C-PRE, and then the voltage signal of the four-bit weight stored in T1~T4 is input into the multiplication and accumulation module MAC, and Vsum[3]~Vsum[0] output the voltage signal representing the operation result of the multiplication and accumulation module MAC.

2. The charge domain in-memory computing circuit according to claim 1, characterized in that: The multiplication and accumulation module MAC includes NMOS tubes M6, M8, M10, M12, PMOS tubes M7, M9, M11, M13, calculation capacitors C1, C2, C3, C4 and transmission gates W1, W2, W3, W4; The drains of M6, M8, M10, and M12 are connected to the data outputs of T4, T3, T2, and T1 as the signal inputs of the multiplication and accumulation module MAC. The sources of M6, M8, M10, and M12 are connected to the gates of M7, M9, M11, and M13. The gates of M6, M8, M10, and M12 are controlled by the control signal line CAL. The two ends of C1, C2, C3, and C4 are connected to the signal lines V1 and V2 respectively. The source and drain of M7 are connected to the two ends of C1 respectively. The source and drain of M9 are connected to the two ends of C2 respectively, the source and drain of M11 are connected to the two ends of C3 respectively, and the source and drain of M13 are connected to the two ends of C4 respectively; the two ends of C2 and C4 are connected to the output signal lines Vsum[3]~Vsum[1] respectively as the result output ends of the multiplication and accumulation module MAC; the capacitance values ​​of C1 and C3 are the same, the capacitance values ​​of C2 and C4 are the same, and the capacitance values ​​of C1 and C3 are twice the capacitance values ​​of C2 and C4; Signal lines V1 and V2 are connected to transmission gates W1, W2, W3, and W4. W1 is used to control the on-off between C1 and C2, W2 is used to control the on-off between C2 and Vsum[3] and Vsum[2], W3 is used to control the on-off between C3 and C4, and W4 is used to control the on-off between C4 and Vsum[1] and Vsum[0].

3. The charge domain in-memory computing circuit according to claim 2, characterized in that: The pre-charge module C-PRE includes six NMOS transistors M1 to M5 and M14; the drain of M14 is connected to the signal line V1, the source of M14 is connected to the drains of M1 and M2; the drain of M5 is connected to the signal line V2, the source of M5 is connected to the drains of M3 and M4, and the gates of M14 and M5 are connected to the control signal line PRE; The sources of M1 and M3 are connected to the voltage signal Vdac of the external four-bit weight data, and the sources of M2 and M4 are connected to 1 / 2VDD; The gates of M2 and M3 are connected to the signal output line of TSIGN; the gates of M1 and M4 are connected to the inverse signal output line of TSIGN.

4. The charge domain in-memory computing circuit according to claim 3, characterized in that: Memory cells T1-T4 and TSIGN all employ 6T memory cells comprising six transistors. The 6T memory cell comprises two PMOS transistors P1 and P2, and four NMOS transistors N1, N2, N3, and N4. P1 and N1 form an inverter structure, P2 and N2 form another inverter structure, and N3 and N4 serve as transmission transistors. The sources of P1 and P2 are both connected to VDD, and the sources of NM1 and NM2 are both grounded. The drain of P1, the drain of N1, the gate of P2, and the gate of N2 are connected to form a storage node Q and are also connected to the drain of N3. The drain of P2, the drain of N2, the gate of P1, and the gate of N1 are connected to form a storage node QB and are also connected to the drain of N4. The gates of N3 and N4 are connected to a word line WL. The source of N3 is connected to a bit line BL, and the source of N4 is connected to a bit line BLB. The bit line BL serves as a signal output terminal of the 6T memory cell.

5. The charge domain in-memory computing circuit according to claim 4, characterized in that: The sign of the multiplication result of the charge domain memory calculation circuit is determined by the storage data of the storage unit TSIGN and the voltage signal Vdac; if the data stored in the storage unit TSIGN is "1", it means that the sign bit of the weight data stored in the storage units T4 to T1 is a negative sign bit; if the data stored in the storage unit TSIGN is "0", it means that the sign bit of the weight data stored in the storage units T4 to T1 is a positive sign bit; When the data stored in the memory cell TSIGN is "1", the voltage difference between the signal lines V1 and V2 is V1-V2=1 / 2VDD-Vdac; when the data stored in the memory cell TSIGN is "0", the voltage difference between the signal lines V1 and V2 is V1-V2=Vdac-1 / 2VDD.

6. The charge domain in-memory computing circuit according to claim 5, characterized in that: The charge domain memory calculation circuit implements multiplication calculation, including a pre-charge stage, a cumulative multiplication stage, and a charge sharing stage performed in sequence; the pre-charge stage is used to pre-charge the voltage signal of the external four-bit weight data to the two ends of the calculation capacitors C1, C2, C3, and C4; the cumulative multiplication stage is used to multiply the stored weight data with the external four-bit weight data; the charge sharing stage is used to charge share the multiplication results of T4, T3 and T2, T1 with the external four-bit weight data to realize weighted and accumulation operations.

7. The charge domain in-memory computing circuit according to claim 6, characterized in that: The specific operations of the pre-charge stage are as follows: A high-level signal is input to M14 and M5 through the control signal line PRE, and a high-level signal is input to the transmission gates W1 and W3; a low-level signal is input to M6, M8, M10, and M12 through the control signal line CAL, and a low-level signal is input to the transmission gates W2 and W4; so that the voltages across the calculation capacitors C1, C2, C3, and C4 are the voltages of the signal lines V1 and V2, respectively.

8. The charge domain in-memory computing circuit according to claim 6, characterized in that: The specific operations of the multiplication stage are as follows: A low-level signal is input to M14 and M5 through the control signal line PRE; a high-level signal is input to M6, M8, M10, and M12 through the control signal line CAL, and a low-level signal is input to the transmission gates W1 to W4; so that the calculation capacitors C1, C2, C3, and C4 are disconnected from each other and connected to the storage units T1 to T4 one by one.

9. The charge domain in-memory computing circuit according to claim 6, characterized in that: The specific operations of the charge sharing stage are as follows: A low-level signal is input to M6, M8, M10, and M12 through the control signal line CAL, and a high-level signal is input to the transmission gates W1 to W4; so that the calculation capacitors C1, C2 and C3, C4 are connected and disconnected from the storage units T1 to T4; the voltage difference between the output signal lines Vsum[3] and Vsum[2] represents the multiplication result of T4, T3 with the external four-bit weight data; the voltage difference between the output signal lines Vsum[1] and Vsum[0] represents the multiplication result of T2, T1 with the external four-bit weight data.

10. A storage circuit with positive and negative number operation function, characterized in that: It includes: A storage and computation array, which is formed by a plurality of identical storage and computation units in an N×M array format; wherein N represents the number of rows of the storage and computation array, and M represents the number of columns of the storage and computation array; An output signal line group, comprising M groups of output signal lines Vsum[3] to Vsum[0], wherein each storage and calculation unit in each column is connected to the same group of output signal lines Vsum[3] to Vsum[0]; A digital-to-analog conversion module, which is used to convert the signed external four-bit weight data into a corresponding analog voltage signal and input it into any storage and calculation unit in the storage and calculation array; A timing control module, which is used to generate control signals required for computing operations; an analog-to-digital conversion module, configured to convert the analog voltage signal outputted by any column of the storage and computing array through the output signal line group into a corresponding digital signal; A digital weighting and accumulation module, which is used to perform weighting and accumulation operations on the digital signal output by the analog-to-digital conversion module, and then output a digital quantity result of the multiplication operation between the storage and calculation unit in any column and the external four-bit weight data; The storage and calculation unit adopts the circuit structure of the charge domain in-memory calculation circuit as described in any one of claims 1 to 9, and realizes the complete functions of the circuit.

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