Semiconductor device and method of manufacturing the same

Abstract

The method includes forming a stack of channel layers and sacrificial layers on a substrate. The channel layers and the sacrificial layers have different material compositions and are arranged alternately in a vertical direction. The method further includes patterning the stack to form a semiconductor fin, forming an isolation feature on a sidewall of the semiconductor fin, recessing the semiconductor fin to form a source / drain recess such that a recessed top surface of the semiconductor fin is below a top surface of the isolation feature, growing a base epitaxial layer from the recessed top surface of the semiconductor fin, depositing an insulating layer in the source / drain recess, and forming an epitaxial feature in the source / drain recess, wherein the epitaxial feature is on the insulating layer. The insulating layer is on the base epitaxial layer and on a bottommost channel layer. Embodiments of the present application also relate to semiconductor devices and methods of manufacturing the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This scaling down process typically provides benefits through increased production efficiency and reduced associated costs. This shrinkage also increases the complexity of handling and manufacturing ICs.

[0003] For example, as IC technology has evolved to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). Multi-gate devices typically refer to devices with gate structures or portions thereof disposed above more than one side of the channel region. Gate-all-around (GAA) transistors are an example of multi-gate devices that have become popular and promising candidates for high-performance and low-leakage applications. GAA transistors are named for their gate structure, which extends around the channel region, providing access to stacked semiconductor channel layers on all four sides. Compared to planar transistors, this configuration provides better channel control and significantly reduces SCE (particularly by reducing subthreshold leakage). The number of stacked semiconductor channel layers is selected based on device performance considerations, particularly the transistor's current drive capability.

[0004] IC devices comprise transistors that provide different functions, such as input / output (I / O) functions and core functions. These different functions require transistors with different structures. Simultaneously, it is advantageous to have similar processes and similar process windows to manufacture these different transistors to reduce costs and improve yield. While existing GAA transistors and processes are generally sufficient for their intended purpose, they are not entirely satisfactory in every aspect. For example, in an IC chip, there are different regions providing different functions, such as high-power regions for high-performance computing (HPC) units or central processing units (CPUs), which require GAA transistors with strong current drive capabilities to achieve high operating speeds, and low-power regions for I / O or system-on-chip (SoC) units, which require GAA transistors with lower current drive capabilities to achieve low leakage performance. Therefore, the required number of stacked semiconductor channel layers in GAA transistors in different regions of an IC chip may vary. Thus, in the development of integrated circuits, how to achieve an adjustable number of stacked semiconductor channel layers on a single chip to adapt to different applications is a challenge facing the semiconductor industry. This invention aims to solve the above-mentioned problems and other related issues. Summary of the Invention

[0005] Some embodiments of this application provide a method for manufacturing a semiconductor device, comprising: forming a stack of a channel layer and a sacrificial layer on a substrate, the channel layer and the sacrificial layer having different material compositions and being alternately disposed in a vertical direction; patterning the stack to form a semiconductor fin; forming an isolation member on the sidewall of the semiconductor fin; recessing the semiconductor fin to form a source / drain trench, such that the recessed top surface of the semiconductor fin is located below the top surface of the isolation member; growing a substrate epitaxial layer from the recessed top surface of the semiconductor fin; depositing an insulating layer in the source / drain trench, wherein the insulating layer is located above the substrate epitaxial layer and above the bottommost channel layer; and forming an epitaxial member in the source / drain trench, wherein the epitaxial member is located above the insulating layer.

[0006] Other embodiments of this application provide a method for manufacturing a semiconductor device, comprising: forming an epitaxial stack of a channel layer and a sacrificial layer on a semiconductor substrate, the channel layer and the sacrificial layer having different material compositions and being stacked alternately in a vertical direction; patterning the epitaxial stack to form a first semiconductor fin in a first region of the semiconductor substrate and a second semiconductor fin in a second region of the semiconductor substrate; recessing the first semiconductor fin in a first source / drain region; recessing the second semiconductor fin in a second source / drain region; and recessing the first semiconductor fin in the first source / drain region and the second source / drain region. An epitaxial layer is formed; a dielectric layer is formed on the epitaxial layer in the first source / drain region and the second source / drain region, wherein the top surface of the dielectric layer in the first source / drain region is located above the top surface of the dielectric layer in the second source / drain region; and a first source / drain component is formed in the first source / drain region and a second source / drain component is formed in the second source / drain region, wherein the second source / drain component is in contact with the bottommost channel layer in the second semiconductor fin, and the first source / drain component is not in contact with the bottommost channel layer in the first semiconductor fin.

[0007] Further embodiments of this application provide a semiconductor device comprising: a channel layer disposed above a substrate; a gate structure covering each of the channel layer, wherein the gate structure includes a gate dielectric layer and a gate electrode layer; a first epitaxial member adjacent to the topmost channel layer; a second epitaxial member located below the first epitaxial member; an internal spacer between the first epitaxial member and the gate structure; and a dielectric layer disposed between the first epitaxial member and the second epitaxial member, wherein the dielectric layer and the second epitaxial member separate the first epitaxial member from at least the bottommost channel layer such that the first epitaxial member does not contact at least the bottommost channel layer. Attached Figure Description

[0008] The invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1A A flowchart illustrating an embodiment of a method for forming a multi-gate device according to one or more aspects of the present invention is shown.

[0010] Figure 1B A flowchart illustrating an alternative embodiment of a method for forming a multi-gate device according to one or more aspects of the present invention is shown.

[0011] Figure 2 , Figure 3 and Figure 4 The invention illustrates the basis of one or more aspects thereof. Figure 1A and Figure 1B A three-dimensional view of the semiconductor structure during the manufacturing process of an embodiment of the method.

[0012] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 15A , Figure 15B , Figure 15C , Figure 15D , Figure 16A , Figure 16B , Figure 16C , Figure 16D , Figure 17A , Figure 17B , Figure 17C , Figure 17D , Figure 18A , Figure 18B , Figure 18C , Figure 18D , Figure 19A , Figure 19B , Figure 19C , Figure 19D , Figure 20A , Figure 20B, Figure 20C , Figure 20D , Figure 21A , Figure 21B , Figure 21C , Figure 21D , Figure 22A , Figure 22B , Figure 22C , Figure 22D , Figure 23A , Figure 23B , Figure 23C , Figure 23D , Figure 24A , Figure 24B , Figure 24C and Figure 24D The invention illustrates the basis of one or more aspects thereof. Figure 1A and Figure 1B A cross-sectional view of the semiconductor structure during the manufacturing process of an embodiment of the method. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. Furthermore, when using terms such as “about,” “approximately,” etc., to describe numbers or ranges of numbers, the term is intended to include numbers within + / - 10% of the described number, unless otherwise stated. For example, the term “about 5 nm” includes dimensions in the range of 4.5 nm to 5.5 nm.

[0015] This application generally relates to semiconductor structures and manufacturing processes, and more specifically to integrated circuit (IC) chips having multi-gate transistors with an adjustable number of stacked semiconductor channel layers in different regions to accommodate different applications on a single chip. A multi-gate transistor generally refers to a device having a gate structure or portion thereof disposed above more than one side of a channel region. Multi-bridge channel (MBC) transistors are examples of multi-gate devices that have become popular and promising candidates for high-performance and low-leakage applications. MBC transistors have gate structures that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because their gate structures surround the channel region, MBC transistors can also be referred to as gate-around transistors (SGT) or gate-all-around (GAA) transistors. In various embodiments, at least two gate-all-around (GAA) transistors with different (also referred to as adjustable or variable) numbers of stacked semiconductor channel layers (also referred to as channel layers) are placed on the same substrate in the core region (e.g., for high-power applications) and the I / O region (for low-leakage applications) of an IC chip, respectively. According to various aspects of the invention, an adjustable number of stacked channel layers can be achieved by isolating one or more bottom channel layers from epitaxial source / drain (S / D) components, thereby preventing one or more bottom channel layers from contacting the epitaxial S / D components.

[0016] The details of the structure and manufacturing method of the present invention are described below with reference to the accompanying drawings, which illustrate the process of manufacturing a GAA device according to some embodiments. The GAA device has horizontally oriented channel layers stacked vertically. The channel layers may be referred to as “nanostructures” or “nanosheets,” which herein are used to denote any portion of material having nanoscale or even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the terms “nanostructure” or “nanosheet” as used herein refer to elongated material portions with circular and substantially circular cross-sections, as well as beam-shaped or rod-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. GAA devices are promising candidates for bringing CMOS to the next stage of the roadmap due to their superior gate control capabilities, lower leakage current, and complete FinFET device layout compatibility. For simplicity, the present invention uses a GAA device as an example. Those skilled in the art will understand that they can readily use the present invention as a basis to design or modify other processes and structures (such as other types of MBC transistors) to perform the same purposes and / or achieve the same advantages as the embodiments described herein.

[0017] Embodiments of the present invention offer advantages over the prior art; however, it should be understood that other embodiments may offer different advantages, and not all advantages need to be discussed herein, nor is any particular advantage necessary for all embodiments. For example, embodiments discussed herein include methods and structures for providing an insulating layer between an epitaxial source / drain component and one or more bottom channel layers to adjust the number of available functional channel layers. The insulating layer is also between the epitaxial source / drain component and the underlying semiconductor substrate. Gate structures extending around the stacked channel layers also directly bond to the top surface of the semiconductor substrate below the bottommost channel layer, which may allow leakage current to flow into the semiconductor substrate. The insulating layer also helps suppress leakage current.

[0018] Various aspects of the invention will now be described in more detail with reference to the accompanying drawings. Figure 1A and Figure 1B Flowcharts of method 100 and alternative method 100' for forming a semiconductor device are shown respectively. Each method is merely an example and is not intended to limit the invention to what is explicitly shown in the method. Additional steps may be provided before, during, and after the respective method, and some steps described may be replaced, eliminated, or moved for additional embodiments of the respective method. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 2 to 24D Description methods 100 and 100' Figures 2 to 24D Schematic perspective and partial cross-sectional views of workpiece 200 at different manufacturing stages according to embodiments of methods 100 and 100' are shown. Since a semiconductor device will be formed from workpiece 200, workpiece 200 may be referred to as semiconductor device 200 or device 200 as needed by the context. Figures 2 to 4 This is a schematic perspective view of a workpiece 200 at various manufacturing stages according to some embodiments. Figures 5A to 24D In order to better illustrate various aspects of the invention, each figure ending with the capital letter A shows a partial cross-sectional view in the channel region of the transistor to be formed (i.e., as shown in the figure). Figure 4 As shown in the diagram, each figure ending with the capital letter B illustrates a partial cross-sectional view of the source / drain region of the transistor to be formed (i.e., as shown in the diagram). The cut along line AA in the channel region (the channel region is along the longitudinal direction of the gate structure and perpendicular to the longitudinal direction of the channel layer) utilizes a cut along line AA in the channel region. Figure 4 As shown, a cut of the BB line in the source / drain region along the longitudinal direction perpendicular to the channel layer. Each figure ending with a capital C shows a partial cross-sectional view of the first fin along the first region (i.e., as shown). Figure 4 As shown, the first fin in the first region is cut along the CC line. Each figure ending with a capital letter D shows a partial cross-sectional view of the second fin in the second region (i.e., as shown). Figure 4As shown, the second fin in the second region is cut along the DD line. (Through) Figures 2 to 24D The X, Y, and Z directions are perpendicular to each other and used consistently. Furthermore, throughout this invention, the same reference numerals are used to denote the same components. Embodiments of this invention are described using MBC transistor structures, particularly GAA transistor structures, for illustrative purposes only and should not be construed as limiting the scope of the invention; for example, the invention can also be applied to other multi-gate devices, including FinFET transistors.

[0019] refer to Figure 1A and Figure 2 Method 100 includes block 102, wherein a workpiece 200 is received. Workpiece 200 includes a substrate 202. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. In some embodiments, substrate 202 includes a single-crystal semiconductor layer at least on its surface portion. Substrate 202 may include single-crystal semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Optionally, substrate 202 may include compound semiconductors and / or alloy semiconductors. Substrate 202 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 202 includes a first region 204 and a second region 206. First region 204 may be an I / O region including I / O cells, ESD cells, and other circuitry. Transistors formed in first region 204 are used for low-power and / or low-leakage applications. The second region 206 may be a core region including high-performance computing (HPC) units, central processing unit (CPU) logic circuitry, memory circuitry, and other core circuitry. Transistors formed in the second region 206 are used for high-power and / or high-speed applications. Typically, the transistors in the second region 206 require a stronger current drive capability than the transistors in the first region 204 due to their power-intensive applications. It should be noted that although regions 204 and 206 are depicted as adjacent to each other in the illustrated embodiment, this is for illustrative purposes only. In various embodiments, regions 204 and 206 may be adjacent to each other or separated from each other, with one or more other regions disposed between them, as well as the transistors formed in regions 204 and 206.

[0020] refer to Figure 3 Method 100 includes box 104 ( Figure 1AAn epitaxial stack 212 is formed over a substrate 202, wherein one or more epitaxial layers are formed thereon. In some embodiments, an epitaxial stack 212 is formed over regions 204 and 206. The epitaxial stack 212 includes an epitaxial layer 214 of a first component, with an epitaxial layer 216 of a second component interposed therebetween, and a top epitaxial layer 214T of the first component located above the top epitaxial layer 216. The first component and the second component may be different. In an embodiment, epitaxial layer 214 is silicon germanium (SiGe) and epitaxial layer 216 is silicon (Si). However, other embodiments are also possible, including those providing a first component and a second component with different oxidation rates and / or etch selectivity. It should be noted that Figure 3 The diagram shows three (3) layers of each of epitaxial layers 214 and 216, which are for illustrative purposes only and are not intended to limit the scope beyond what is specifically set forth in the claims. It will be understood that any number of epitaxial layers may be formed in the epitaxial stack 212; the number of epitaxial layers depends on the desired number of channel layers for forming the transistor. In some embodiments, the number of epitaxial layers 216 is between 2 and 10.

[0021] In some embodiments, epitaxial layer 214 has a thickness ranging from about 8 nm to about 12 nm. Epitaxial layer 214 may be substantially uniform in thickness. In some embodiments, epitaxial layer 216 has a thickness ranging from about 8 nm to about 10 nm. In some embodiments, epitaxial layer 216 may be substantially uniform in thickness. As described in more detail below, epitaxial layer 216 may be used as a channel layer (or channel component) for subsequently formed GAA transistors, and its thickness is selected based on device performance considerations. Epitaxial layer 214 may be used to maintain a gap (or spacing) between adjacent channel layers, and its thickness is selected based on device performance considerations. Epitaxial layer 214 will then be removed and may also be referred to as sacrificial layer 214. Like epitaxial layer 214, top epitaxial layer 214T may be formed of silicon germanium (SiGe). Top epitaxial layer 214T may be thicker than epitaxial layer 214 and is used to protect epitaxial stack 212 from damage during the manufacturing process. In some cases, the thickness of the top epitaxial layer 214T can be between approximately 20 nm and approximately 40 nm.

[0022] For example, the epitaxially grown epitaxial stack 212 can be implemented using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layers (such as epitaxial layer 216) comprise the same material as the substrate 202, such as silicon (Si). In some embodiments, the top epitaxial layer 214T and epitaxial layer 214 have substantially the same composition. In some embodiments, epitaxial layers 214 and 216 comprise materials different from the substrate 202. As noted above, in at least some instances, epitaxial layer 214 comprises epitaxially grown Si.1-x Ge x The epitaxial layer 214 (e.g., x is about 25-55%) comprises an epitaxially grown Si layer. Alternatively, in some embodiments, either of the epitaxial layers 214 and 216 may comprise: other materials, such as germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. As discussed, the materials of the epitaxial layers 214 and 216 can be selected based on providing different oxidation and etch selectivity characteristics. In various embodiments, the epitaxial layers 214 and 216 are substantially dopant-free (i.e., having a dopant content from about 0 cm⁻¹). -3 To approximately 1×10 17 cm -3 (non-inherent dopant concentration), where, for example, no intended doping is performed during the epitaxial growth process.

[0023] Furthermore, a mask layer 218 is formed over the epitaxial stack 212. In some embodiments, the mask layer 218 includes a first mask layer 218A and a second mask layer 218B. The first mask layer 218A is a pad oxide layer made of silicon oxide, which can be formed by a thermal oxidation process. The second mask layer 218B is made of silicon nitride (SiN), which is formed by chemical vapor deposition (CVD) (including low-pressure CVD (LPCVD) and plasma-enhanced CVD (PECVD)), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable processes.

[0024] refer to Figure 4 and Figures 5A to 5D Method 100 includes box 106 ( Figure 1A The patterned epitaxial stack 212 forms a first semiconductor fin 220-1 in a first region 204 and a second semiconductor fin 220-2 (collectively referred to as fin 220) in a second region 206, as shown below. Figure 4 and Figures 5A to 5DAs shown in the diagram. In various embodiments, each of the fins 220 includes an upper portion 220A (also referred to as epitaxial portion 220A) of the staggered epitaxial layers 214 / 216 and the top epitaxial layer 214T, and a base portion 220B formed by the top portion of the patterned substrate 202. The base portion 220B still has a fin shape protruding from the substrate 202 and is also referred to as finned substrate 220B. The mask layer 218 is patterned into a mask pattern using patterning operations including photolithography and etching. In some embodiments, the operations in block 106 use a suitable process including dual patterning or multiple patterning processes to pattern the epitaxial stack 212. Typically, dual patterning or multiple patterning processes combine photolithography and self-aligned processes, thereby allowing the creation of patterns with, for example, a spacing smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a material layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can then be used in an etching process to pattern the epitaxial stack 212 through openings defined in the patterned mask layer 218, such as dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes. Thus, the stacked epitaxial layers 214 and 216 are patterned as fins 220, with trenches between adjacent fins. Each fin 220 projects upward from the substrate 202 in the Z direction and extends longitudinally in the Y direction. Figure 4 In the diagram, two (2) fins 220 are spaced apart along the X direction, one fin being disposed on the first region 204 and the other on the second region 206. However, the number of fins is not limited to two and may be as few as one or more than two. It should be noted that although in the illustrated embodiment the two fins 220 are depicted as adjacent to each other, this is for illustrative purposes only. In various embodiments, the fins 220 may be adjacent to each other or separated from each other, with other fins disposed between them.

[0025] refer to Figures 6A to 6D Method 100 includes box 108 ( Figure 1AThe trenches between adjacent fins 220 are filled with dielectric material to form isolation members 222. Isolation members 222 may include one or more dielectric layers. Suitable dielectric materials for isolation members 222 may include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low-k dielectric materials, and / or other suitable dielectric materials. The dielectric material may be deposited by any suitable technique including thermal growth, CVD, HDP-CVD, PVD, ALD, and / or spin coating. A planarization operation, such as a chemical mechanical polishing (CMP) method, is then performed to expose the upper surface of the top epitaxial layer 214T from the isolation member 222. The operation in block 108 then recesses the isolation member 222 to form a shallow trench isolation (STI) member (also referred to as STI member 222). Any suitable etching technique can be used to recess the isolation member 222, including dry etching, wet etching, RIE, and / or other etching methods. In an exemplary embodiment, anisotropic dry etching is used to selectively remove the dielectric material of the isolation member 222 without etching the fin 220. In the illustrated embodiment, the mask layer 218 is removed by a CMP process performed prior to recessing the isolation member 222. In some embodiments, the mask layer 218 is removed by an etchant used to recess the isolation member 222. In the illustrated embodiment, the STI member 222 is disposed on the sidewall of the fin substrate 220B. The top surface of the STI member 222 may be coplanar with the bottom surface of the epitaxial portion 220A (or the top surface of the fin substrate 220B), or may be located approximately 1 nm to approximately 10 nm below the bottom surface of the epitaxial portion 220A (or the top surface of the fin substrate 220B). In some embodiments, a pad layer 223 is blanket-deposited over the fin 220 prior to depositing the isolation member 222. In some embodiments, the padding layer 223 is made of SiN or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN). Then, as... Figure 6A and Figure 6B As shown, the padding layer 223 is recessed, so that the extension portion 220A of the fin 220 (and the top portion of the fin base 220B in the illustrated embodiment) is exposed.

[0026] refer to Figures 7A to 7D Method 100 includes box 110 ( Figure 1AA cladding layer 226 is deposited on the sidewalls of fin 220. In some embodiments, the cladding layer 226 may have a composition similar to that of epitaxial layer 214 or top epitaxial layer 214T. In one example, the cladding layer 226 may be formed of silicon germanium (SiGe). Their common composition allows for selective and simultaneous removal of epitaxial layer 214 and cladding layer 226 in a subsequent etching process. In some embodiments, the cladding layer 226 may be conformally grown on workpiece 200 and epitaxially as a blanket layer using vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE). Depending on the extent of selective growth of the cladding layer 226, an etch-back process may be performed to expose the isolation component 222.

[0027] refer to Figures 8A to 8D Method 100 includes box 112 ( Figure 1AA dielectric fin 228 is formed in a trench between fins 220. An exemplary process for forming the dielectric fin 228 includes conformally depositing a first dielectric layer 230 and subsequently depositing a second dielectric layer 232 in the trench between the fins 220. The second dielectric layer 232 is surrounded by the first dielectric layer 230. The first dielectric layer 230 can be conformally deposited using CVD, ALD, or a suitable method. The first dielectric layer 230 lines the sidewalls and bottom surface of the trench between the fins 220. The second dielectric layer 232 is then deposited over the first dielectric layer 230 using CVD, high-density plasma CVD (HDPCVD), and / or other suitable processes. In some cases, the dielectric constant of the second dielectric layer 232 is less than that of the first dielectric layer 230. The first dielectric layer 230 may include silicon, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, aluminum zirconium oxide, hafnium oxide, or a suitable dielectric material. In one embodiment, the first dielectric layer 230 includes aluminum oxide. The second dielectric layer 232 may include silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, or a suitable dielectric material. In one embodiment, the second dielectric layer 232 includes silicon oxide. Dielectric layers 230 and 232 are then etched back. The etch-back process may include a dry etching process using oxygen, nitrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases, and / or plasma and / or combinations thereof. Subsequently, a third dielectric layer 234 is deposited over dielectric layers 230 and 232 using CVD, high-density plasma CVD (HDPCVD), and / or other suitable processes. The third dielectric layer 234 comprises a high-k dielectric material (e.g., k > 7) and is also referred to as the high-k dielectric layer 234. In some embodiments, the high-k dielectric layer 234 may comprise hafnium oxide (HfO2), zirconium oxide (ZrO2), or hafnium aluminum oxide (HfAlO2). x Hafnium silicate (HfSiO) x Alumina (Al2O3) or other suitable high-k dielectric materials are used. After depositing the dielectric layer 234, the workpiece 200 is planarized using a chemical mechanical polishing (CMP) process to expose the top epitaxial layer 214T. Figure 8A and Figure 8B As shown, at the end of the CMP process, dielectric layers 230, 232, and 234 together define dielectric fins 228 between fins 220. Dielectric fins 228 may also be referred to as hybrid fins 228.

[0028] refer to Figures 9A to 9D Method 100 includes box 114 ( Figure 1AIn block 114, workpiece 200 is etched to selectively remove portions of the top epitaxial layer 214T and cladding layer 226 to expose the topmost epitaxial layer 216, without substantially damaging the dielectric fin 228. In some cases, because the top epitaxial layer 214T and cladding layer 226 are formed of silicon germanium (SiGe), the etching process in block 114 can be selective for silicon germanium (SiGe). For example, the cladding layer 226 and the top epitaxial layer 214T can be etched using a selective wet etching process including ammonium hydroxide (NH4OH), hydrogen fluoride (HF), hydrogen peroxide (H2O2), or combinations thereof. After removing portions of the top epitaxial layer 216T and cladding layer 226, the dielectric fin 224, particularly the third dielectric layer 234, rises above the topmost epitaxial layer 216.

[0029] refer to Figures 10A to 10D Method 100 includes box 116 ( Figure 1A A dummy gate stack 240 is formed above the channel region of fin 220. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein the dummy gate stack 240 serves as a reserved location for a functional gate structure. Other processes and configurations are possible. In the illustrated embodiment, the dummy gate stack 240 includes a dummy dielectric layer and a dummy electrode disposed above the dummy dielectric layer. For patterning purposes, a gate top hard mask 242 is deposited above the dummy gate stack 240. The gate top hard mask 242 may be multilayered and includes a silicon nitride mask layer 242A and a silicon oxide mask layer 242B located above the silicon nitride mask layer 242A. The region of fin 220 located below the dummy gate stack 240 may be referred to as a channel region. Each channel region of either fin 220-1 or fin 220-2 is sandwiched between two source / drain regions for source / drain formation. In an exemplary process, a dummy dielectric layer in the dummy gate stack 240 is deposited over workpiece 200 via CVD blanket deposition. A material layer for dummy electrodes is then blanket-deposited over the dummy dielectric layer. The dummy dielectric layer and the material layer for the dummy electrodes are then patterned using a photolithography process to form the dummy gate stack 240. In some embodiments, the dummy dielectric layer may comprise silicon oxide, and the dummy electrodes may comprise polysilicon.

[0030] refer to Figures 11A to 11D Method 100 includes box 118 ( Figure 1AThe dummy gate stack 240 has sidewall spacers 244 formed on its sidewalls. In some embodiments, the sidewall spacers 244 may have a thickness between about 2 nm and about 10 nm. In some embodiments, the sidewall spacers 244 may include dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, low-k materials, and / or combinations thereof. In some embodiments, the sidewall spacers 244 include multiple layers, such as a liner spacer layer 244A and a main spacer layer 244B. For example, the sidewall spacers 244 may be formed by conformally depositing dielectric material over the device 200 using a process such as CVD, subatmospheric pressure CVD (SACVD), flowable CVD, ALD, PVD, or other suitable processes. After conformally depositing the dielectric material, the portion of the dielectric material used to form the sidewall spacers 244 can be etched back to expose portions of the fin 220 not covered by the dummy gate stack 240 (e.g., in the source / drain regions). In some cases, the etch-back process removes the portion of the dielectric material used to form the sidewall spacers 244 along the top surface of the dummy gate stack 240, thereby exposing the gate top hard mask 242. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof. It should be noted that after the etch-back process, the sidewall spacers 244 remain on the sidewalls of the dummy gate stack 240.

[0031] refer to Figures 12A to 12D Method 100 includes box 120 ( Figure 1A The source / drain regions of fin 220 are recessed to form source / drain recesses 250-1 in a first region 204 and source / drain recesses 250-2 in a second region 206 (collectively referred to as source / drain recesses 250). With the dummy gate stack 240 and sidewall spacers 244 serving as etching masks, anisotropic etching workpiece 200 is performed to form source / drain recesses 250 over the source / drain regions of fin 220. In some embodiments, the operation in block 120 removes epitaxial layers 214 and 216, cladding layer 226, and the top portion of fin substrate 220B from the source / drain regions, thereby exposing isolation members 222 in the source / drain recesses 250. In the illustrated embodiment, the source / drain recesses 250 extend into the fin substrate 220B and are located below the top surface of the isolation member 222. The anisotropic etching in block 120 may include a dry etching process. For example, dry etching processes can be implemented with hydrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma and / or combinations thereof.

[0032] refer to Figures 13A to 13D Method 100 includes box 122 ( Figure 1A The epitaxial layer 214 is etched laterally (or recessed) to form a cavity at its lateral ends. In some embodiments, lateral etching (or horizontal recessing) is performed to recess the epitaxial layer 214 to form a cavity at its lateral ends. The etching depth of the epitaxial layer 214 can range from about 2 nm to about 10 nm. When the epitaxial layer 214 is SiGe, the lateral etching process can use etchants such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution. Subsequently, an insulating layer is deposited in the source / drain trench 250 to fill the cavity at the lateral ends of the epitaxial layer 214. The insulating layer may include a dielectric material such as SiN, SiOC, SiOCN, SiCN, SiO2, and / or other suitable materials. In some embodiments, the insulating layer is conformally deposited, for example, by ALD or any other suitable method. After conformally depositing the insulating layer, an etch-back process is performed to remove the insulating layer from the outer portion of the cavity. Through this etching, the insulating layer is essentially retained inside the cavity, thereby forming the internal spacer 252.

[0033] refer to Figures 14A to 14D Method 100 includes box 124 ( Figure 1A The substrate epitaxial layer 254 is epitaxially grown from the recessed top surface of the finned substrate 220B in a first region 204 and a second region 206. For example, the epitaxial growth of the substrate epitaxial layer 254 can be implemented by vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. In some embodiments, the substrate epitaxial layer 254 comprises the same material as the substrate 202, such as silicon (Si). In some alternative embodiments, the substrate epitaxial layer 254 comprises a different semiconductor material than the substrate 202, such as silicon germanium (SiGe). Figure 14B As shown, the epitaxial layer 254 can exhibit planar growth as it rises above the top surface of the isolation member 222, such that the width of the epitaxial layer 254 above the isolation member 222 is greater than the width of the finned substrate 220B above the isolation member 222 (below the dummy gate stack 240). In some embodiments, the epitaxial layer 254 is substantially dopant-free (i.e., has a width from about 0 cm²). -3 To approximately 1×10 17 cm -3 (Non-intrinsic dopant concentration). For comparison, in one case, the fin substrate 220B is lightly doped and has a higher dopant concentration than the epitaxial layer 254. Reference Figure 14C and Figure 14DThe growth of the substrate epitaxial layer 254 is performed under time control, such that the top surface of the substrate epitaxial layer 254 is located above the top surface of the fin substrate 220B below the dummy gate stack 240. In other words, in the illustrated embodiment, the substrate epitaxial layer 254 partially covers the sidewall of the bottom inner spacer 252.

[0034] refer to Figures 15A to 15D Method 100 includes box 126 ( Figure 1A An insulating layer 256 is formed over a substrate epitaxial layer 254 in the first region 204 and the second region 206. In some embodiments, the insulating layer 256 comprises silicon oxide (SiO2) or aluminum oxide (AlO2). x The silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiCON), silicon carbide (SiC), silicon oxycarbide (SiOC), or combinations thereof. The insulating layer 256 insulates the substrate epitaxial layer 254 from the epitaxial source / drain components to be formed in subsequent processes, thereby preventing the substrate epitaxial layer 254 from contacting the epitaxial source / drain components and suppressing leakage current into the buck substrate. In some embodiments, the insulating layer 256 is first deposited in the source / drain trench 250 using a plasma-enhanced chemical vapor deposition (PECVD) process, covering the substrate epitaxial layer 254 and the sidewalls of the source / drain trench 250. Because PECVD deposition typically forms a thicker layer at the bottom of the trench but a thinner layer on its sidewalls, a subsequent etch-back process is performed to remove the insulating layer 256 from the sidewalls of the source / drain trench 250 and also to slightly recess the insulating layer 256 to a defined height h1 (e.g., by controlling the etch time), so that the sidewalls of the bottommost epitaxial layer 216 are completely covered by the insulating layer 256, as shown below. Figure 15C and Figure 15D As shown in the figure. In some embodiments, the height h1 is in the range of about 20 nm to about 28 nm. Removing the insulating layer 256 from the sidewalls of the source / drain trench 250 may include a suitable etching process, such as a dry etching process, a wet etching process, or a RIE process. In various embodiments, the top surface of the insulating layer 256 is located below the bottom surface of the second epitaxial layer 216. Reference Figure 15B An air gap 258 covered by an insulating layer 256 can be trapped at the corner region of the source / drain recess 250. The height h2 of the air gap 258 can range from about 4 nm to about 6 nm. The term "air gap" is used to describe a void defined by surrounding substantial components, wherein the void may contain air, nitrogen, ambient gases, gaseous chemicals used in previous or current processes, or combinations thereof.

[0035] In some embodiments, the source / drain recess 250 may have a high aspect ratio and prevent dielectric material from covering the top opening of the source / drain recess 250 during the deposition of the insulating layer 256. The operation in block 126 may employ a cyclic deposition process. In a cyclic deposition process, the operation in block 126 alternates between dielectric material deposition and etching processes to remove dielectric material accumulated at the edges of the top opening of the source / drain recess 250 and to gradually grow the thickness of the insulating layer 256 through cycles. The etching process also helps to remove dielectric material from the sidewalls of the source / drain recess 250. In some cases, the cyclic deposition process may require approximately one to approximately five cycles.

[0036] refer to Figures 16A to 16D Method 100 includes box 128 ( Figure 1A In the etch-back process, the insulating layer 256 is recessed in the second region 206. A mask layer 260 with openings exposing source / drain grooves 250-2 in the second region 206 restricts the etching process on the insulating layer 256 in the second region 206. The mask layer 260 may be a bottom anti-reflective coating (BARC) layer and patterned using a photolithography process, which may include forming a resist layer on the mask layer 260, exposing the resist by a photolithographic exposure process, performing a post-exposure baking process, developing the resist layer to form a patterned resist layer exposing a portion of the mask layer 260, patterning the mask layer 260, and finally removing the patterned resist layer. The etch-back process may use a suitable etching process, such as dry etching, wet etching, or RIE. The etch-back process recesses the insulating layer 256 in the source / drain trench 250-2 to a defined height h3 (e.g., by controlling the etch time), thereby fully exposing the sidewalls of the bottom epitaxial layer 216. In some embodiments, the height h3 ranges from about 4 nm to about 6 nm. In various embodiments, the top surface of the insulating layer 256 in the second region 206 is located below the bottom surface of the bottom epitaxial layer 216, and the bottom inner spacer 252 is partially exposed, such as... Figure 16D As shown in the image. Reference Figure 16B By thinning the insulating layer 256 in the source / drain recess 250-2, the air gap 258 previously trapped in the corner region of the source / drain recess 250-2 can be released. The mask layer 260 is then removed in a suitable process such as etching, resist stripping, or plasma ashing.

[0037] refer to Figures 17A to 17D Method 100 includes box 130 ( Figure 1AThe epitaxial source / drain component 264-1 is formed in source / drain recess 250-1, and a second epitaxial source / drain component 264-2 (collectively referred to as source / drain component 264) is formed in source / drain recess 250-2. In embodiments, forming the epitaxial source / drain component 264 includes epitaxially growing one or more semiconductor layers using an MBE process, a chemical vapor deposition process, and / or other suitable epitaxial growth processes. In further embodiments, the epitaxial source / drain component 264 is in-situ or out-of-situ doped with an n-type dopant or a p-type dopant. For example, in some embodiments, the epitaxial source / drain component 264 comprises phosphorus-doped silicon for forming an epitaxial source / drain component for an n-type FET. In some embodiments, the epitaxial source / drain component 264 comprises boron-doped silicon germanium (SiGe) for forming an epitaxial source / drain component for a p-type FET. The semiconductor layers of the epitaxial source / drain components 264 are selectively grown on different semiconductor surfaces exposed in the source / drain trenches, such as the lateral ends of the epitaxial layer 216. Because the insulating layer 256 covers the top surface of the substrate epitaxial layer 254, the epitaxial growth of the epitaxial source / drain components 264 does not occur from there. In other words, the insulating layer 256 blocks possible current paths from the bottom of the epitaxial source / drain components 264 to the finned substrate 220B (or substrate 202). Therefore, the substrate leakage current is significantly reduced. Furthermore, the epitaxial source / drain components 264-1 in the first region 204 have a smaller height and smaller volume than the epitaxial source / drain components 264-2 in the second region 206. The epitaxial source / drain components 264-1 contact the top epitaxial layer 216 but not the bottom epitaxial layer (e.g., as shown in the image). Figure 17C (The bottom one shown). For comparison, the epitaxial source / drain component 264-2 contacts all available epitaxial layers 216 in the second region 206. Therefore, the GAA transistor formed in the first region 204 in a subsequent process will have fewer functional channel layers than the GAA transistor formed in the second region 206.

[0038] refer to Figure 17BThe epitaxial source / drain component 264 can exhibit a faceted growth. An air gap 266 can be formed between the bottom surface of the epitaxial source / drain component 264-1 and the top surface of the insulating layer 256. The air gap 266 is stacked on top of the air gap 258. The air gap 266 can have a height h4 ranging from about 12 nm to about 24 nm. An air gap 268 can be formed between the bottom surface of the epitaxial source / drain component 264-2 and the top surface of the insulating layer 256. The air gap 268 is positioned below the air gap 266. However, because the air gap 268 extends upward from the corner region of the source / drain recess 250-2, the air gap 268 has the largest height and the largest volume among the air gaps 258, 266, and 268. The air gap 268 can have a height h5 ranging from about 15 nm to about 30 nm.

[0039] refer to Figures 18A to 18D Method 100 includes box 132 ( Figure 1A A contact etch stop layer (CESL) 270 and an interlayer dielectric layer (ILD) 272 are deposited on the front side of a workpiece 200. In an exemplary process, the CESL 270 is first conformally deposited over the workpiece 200, and then the ILD layer 272 is deposited over the CESL 270. The CESL 270 may comprise silicon nitride, silicon oxide, silicon oxynitride, and / or other materials known in the art. The CESL 270 may be deposited using an ALD, plasma-enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 272 comprises materials such as SiCN, SiON, SiOCN, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide and / or other suitable dielectric materials such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG). The ILD layer 272 may be deposited using spin coating, FCVD, or other suitable deposition techniques. In some embodiments, after forming the ILD layer 272, the workpiece 200 may be annealed to improve the integrity of the ILD layer 272. To remove excess material (including the gate top hard mask 242) and to expose the top surface of the dummy gate stack 240, a planarization process (such as a CMP process) may be performed on the workpiece 200 to provide a flat top surface. The top surface of the dummy gate stack 240 is exposed on the flat top surface.

[0040] refer to Figures 19A to 19D Method 100 includes box 134 ( Figure 1AThe process involves selectively removing the dummy gate stack 240, epitaxial layer 214, and cladding layer 226. The dummy gate stack 240, exposed at the end of frame 132, is removed from workpiece 200 using a selective etching process. This selective etching process can be a selective wet etching process, a selective dry etching process, or a combination thereof. In the depicted embodiment, the selective etching process selectively removes the dummy dielectric layer and dummy electrodes without substantially damaging the epitaxial layer 216 and sidewall spacers 244. Removal of the dummy gate stack 240 creates a gate trench 274 over the channel region. After removal of the dummy gate stack 240, the epitaxial layer 214, epitaxial layer 216, and cladding layer 226 in the channel region are exposed in the gate trench 274. Subsequently, operations in frame 134 selectively remove the epitaxial layer 214 and cladding layer 226 from the gate trench 274 to release the epitaxial layer 216. The selective removal of the epitaxial layer 214 and cladding layer 226 can be achieved using selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, selective wet etching includes ammonium hydroxide (NH4OH), hydrogen fluoride (HF), hydrogen peroxide (H2O2), or combinations thereof (e.g., APM etching including an ammonium hydroxide-hydrogen peroxide-water mixture). In some alternative embodiments, selective removal includes silicon germanium oxidation followed by silicon germanium oxide removal. For example, oxidation can be provided by ozone cleaning, and then the silicon germanium oxide is removed by an etchant such as NH4OH. The released epitaxial layer 216 is also referred to as a channel layer (or channel member) 216, or, due to the nanoscale of the component, a nanostructure 216. In the described embodiments where the channel layer 216 resembles a sheet or nanosheet, the channel layer release process can also be referred to as a wafer forming process. The channel layer 216 may have rounded corners at the end of the wafer forming process. The channel layers 216 are stacked perpendicularly along the Z-direction. All channel layers 216 are spaced from the dielectric fins 228 by a distance maintained by the overlay layer 226. However, as Figure 19C and Figure 19D As shown, in region 204, at least the bottommost channel layer 216 is laterally sandwiched in the middle by an insulating layer 256 and does not contact the epitaxial source / drain component 264-1. Therefore, the GAA transistor formed in region 204 has one less functional channel layer than its counterpart in region 206. In an alternative embodiment, the insulating layer 256 in region 204 may be deposited at a greater height to prevent two or more bottom channel layers 216 from contacting the epitaxial source / drain component 264-1. Therefore, the GAA transistor formed in region 204 may have two or more fewer functional channel layers than its counterpart in region 206.

[0041] refer to Figures 20A to 20D Method 100 includes box 136 ( Figure 1AThe gate structure 276 (also referred to as functional gate structure 276 or metal gate structure 276) is formed in the gate trench 274 to engage each of the channel layers 216. Each of the gate structures 276 includes an interface layer 278 disposed above the channel layer 216, a high-k dielectric layer 280 disposed above the interface layer 278, and a gate electrode layer 282 disposed above the high-k dielectric layer 280. The interface layer 278 and the high-k dielectric layer 280 are collectively referred to as the gate dielectric layer. The interface layer 278 may include silicon oxide and is formed due to a pre-cleaning process. Exemplary pre-cleaning processes may include using RCA SC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The pre-cleaning process oxidizes the exposed semiconductor surfaces of the channel layer 216 and the exposed semiconductor surfaces of the fin substrate 202B to form the interface layer. That is, the exposed dielectric surface of the isolation member 222 may not be covered by the interface layer 278. A high-k dielectric layer 280 is then deposited over the interface layer 278 using ALD, CVD, and / or other suitable methods. The high-k dielectric layer 280 also covers the exposed surface of the isolation component 222. The high-k dielectric layer 280 comprises a high-k dielectric material. In one embodiment, the high-k dielectric layer 280 may comprise hafnium oxide. Optionally, the high-k dielectric layer 280 may include other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials.

[0042] After forming the high-k dielectric layer 280, a gate electrode layer 282 is deposited on top of the high-k dielectric layer 280. The gate electrode layer 282 may be a multilayer structure comprising at least one work function layer and a metal filling layer. For example, the at least one work function layer may comprise titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), or tantalum carbide (TaC). The metal filling layer may comprise aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metallic materials, or combinations thereof. In various embodiments, the gate electrode layer 282 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Although not explicitly shown in the figures, gate structure 276 is deposited as a joint gate structure and then etched back until dielectric fins 228 separate the joint gate structure into gate structures 276 that are spaced apart from each other. Dielectric fins 228 also provide electrical isolation between adjacent gate structures 276. Etching back the gate structures 276 may include a selective wet etching process using nitric acid, hydrochloric acid, sulfuric acid, ammonium hydroxide, hydrogen peroxide, or combinations thereof. In the depicted embodiment, each of the channel layers 216 is enclosed by a corresponding gate structure 276. At the end of block 136, protrusions of the dielectric fins 228 in the channel region, particularly the third dielectric layer 234, may be etched back. Figure 20A As shown in the image.

[0043] refer to Figures 21A to 21D Method 100 includes box 138 ( Figure 1AA metal capping layer 284, a self-aligned capping (SAC) layer 286, a gate dicing member 288, and source / drain contacts 290 are formed on the front side of workpiece 200. In some embodiments, the metal capping layer 284 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), ruthenium (Ru), cobalt (Co), or nickel (Ni), and may be deposited using PVD, CVD, or metal-organic chemical vapor deposition (MOCVD). In one embodiment, the metal capping layer 284 includes tungsten (W), such as fluorine-free tungsten (FFW), and is deposited via PVD. The metal capping layer 284 is electrically connected to the gate structure 276. After depositing the metal capping layer 284, the SAC layer 286 is deposited over workpiece 200 via CVD, PECVD, or a suitable deposition process. The SAC layer 286 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, aluminum zirconium oxide, hafnium oxide, or a suitable dielectric material. A photolithography and etching process is then performed to etch the deposited SAC layer 286 to form a gate cleaving opening to expose the top surface of the dielectric fins. Subsequently, a dielectric material is deposited and planarized using a CMP process to form a gate cleaving member 288 in the gate cleaving opening. The dielectric material for the gate cleaving member 288 may be deposited using HDPCVD, CVD, ALD, or a suitable deposition technique. In some cases, the gate cleaving member 288 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, aluminum zirconium oxide, hafnium oxide, or a suitable dielectric material. In some embodiments, the gate cleaving member 288 and the SAC layer 286 may have different compositions to introduce etch selectivity. Gate dicing 288 and its corresponding dielectric fin 228 located directly beneath it together divide the metal capping layer 284 into segments. Source / drain contacts 290 may include tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), nickel (Ni), or combinations thereof, and may be deposited using PVD, CVD, or metal-organic chemical vapor deposition (MOCVD). Workpiece 200 may also include a silicide component 292 located between the source / drain contacts 290 and the epitaxial source / drain components 264 to further reduce contact resistance. The silicide component 292 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), combinations thereof, or other suitable compounds.Alternatively, silicide formation can be skipped and the source / drain contact 290 can directly contact the epitaxial source / drain component 264.

[0044] Workpiece 200 may undergo further processing to form various components and regions known in the art. For example, subsequent processing may form on substrate 202 various contacts, vias, metal lines, and multilayer interconnects (e.g., metal layers and interlayer dielectrics) configured to connect the various components to form functional circuitry that may include one or more multi-gate devices. In a further example, the multilayer interconnects may include vertical interconnects such as vias or contacts and horizontal interconnects such as metal lines. The various interconnect components may employ various conductive materials including copper, tungsten, and / or silicides. In one example, damascene and / or dual damascene processes are used to form copper-associated multilayer interconnect structures. Furthermore, additional process steps may be performed before, during, and after method 100, and some of the process steps described above may be replaced or eliminated depending on various embodiments of method 100.

[0045] Now for reference Figure 1B , Figure 1B A flowchart illustrating an alternative embodiment of method 100 is shown, denoted as method 100'. Method 100' proceeds to the operations in blocks 102-124. Following the operations in block 124, method 100' proceeds to the operations in blocks 125 and 127. Following the operation in block 127, method 100' continues to the operations in blocks 130-138. The following is in conjunction with... Figures 22A to 24D Method 100 is described below. For the sake of brevity, the common operations will not be repeated below.

[0046] refer to Figures 22A to 22D Following the operation in box 122, method 100' includes box 125 ( Figure 1B In some embodiments, the substrate epitaxial layer 254 in the first region 204 continues to grow an additional height. In some embodiments, the additional height can be in the range of about 20 nm to about 28 nm, such that the substrate epitaxial layer 254 in the first region 204 completely covers the sidewalls of the bottommost epitaxial layer 216, as shown below. Figure 22C As shown in the diagram, the mask layer 260, with openings exposing the source / drain recesses 250-1 in the first region 204, suppresses additional epitaxial growth into the first region 204, as... Figure 22BAs shown in the diagram. Mask layer 260 may be a bottom anti-reflective coating (BARC) layer and patterned using a photolithography process. The photolithography process may include forming a resist layer on mask layer 260, exposing the resist by a photolithographic exposure process, performing a post-exposure baking process, developing the resist layer to form a patterned resist layer exposing a portion of mask layer 260, patterning mask layer 260, and finally removing the patterned resist layer. Additional epitaxial growth of substrate epitaxial layer 254 in first region 204 can be implemented using substantially the same operations as in block 124, such as by vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. Substrate epitaxial layer 254 may exhibit planar growth as it continues to rise in first region 204, such that the width, height, and volume of substrate epitaxial layer 254 in first region 204 are greater than its counterpart in second region 206. The additional growth of the substrate epitaxial layer 254 in the first region 204 can be performed under time control. The mask layer 260 is then removed in a suitable process such as etching, resist stripping, or plasma ashing.

[0047] refer to Figures 23A to 23D Method 100' includes block 127, wherein an insulating layer 256 is formed over a substrate epitaxial layer 254 in a first region 204 and a second region 206. In some embodiments, the insulating layer 256 includes silicon oxide (SiO2) or aluminum oxide (AlO2). x The silicon may be silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiCON), silicon carbide (SiC), silicon oxycarbide (SiOC), or combinations thereof. An insulating layer 256 isolates the substrate epitaxial layer 254 from the epitaxial source / drain components to be formed in subsequent processes, preventing the substrate epitaxial layer 254 from contacting the epitaxial source / drain components to suppress leakage current from the buck substrate. In some embodiments, the insulating layer 256 is first deposited in the source / drain trench 250 using a plasma-enhanced chemical vapor deposition (PECVD) process, covering the substrate epitaxial layer 254 and the sidewalls of the source / drain trench 250. Because PECVD deposition typically forms a thicker layer at the bottom of the trench but a thinner layer on the sidewalls, a subsequent etch-back process is performed to remove the insulating layer 256 from the sidewalls of the source / drain trench 250 and also slightly recess the insulating layer 256 to a defined height h6 (e.g., by controlling the etch time). This results in the sidewalls of the inner spacer 252, located directly above the bottom epitaxial layer 216 in the first region 204, being partially covered by the insulating layer 256, and in the second region 206, the sidewalls of the bottom inner spacer 252 being partially covered by the insulating layer 256, as... Figure 23C and Figure 23DAs shown in the diagram. In further embodiments, the insulating layer 256 in the first region 204 may also partially cover the sidewalls of the bottommost epitaxial layer 216 (when the top surface of the substrate epitaxial layer 254 in the first region 204 is below the top surface of the bottommost epitaxial layer 216). In some embodiments, the height h6 is in the range of about 4 nm to about 6 nm. The thickness of the insulating layer 256 in the first region 204 and the second region 206 is substantially the same. Removing the insulating layer 256 from the sidewalls of the source / drain trench 250 may include a suitable etching process, such as a dry etching process, a wet etching process, or a RIE process. Reference Figure 23B An air gap 258 covered by an insulating layer 256 can be captured at the corner region of the source / drain groove 250. The height h7 of the air gap 258 can range from about 4 nm to about 6 nm.

[0048] In some embodiments, the source / drain recess 250 may have a high aspect ratio and prevent dielectric material from covering the top opening of the source / drain recess 250 during the deposition of the insulating layer 256. The operation in block 127 may employ a cyclic deposition process. In a cyclic deposition process, the operation in block 126 alternates between dielectric material deposition and etching processes to remove dielectric material accumulated at the edges of the top opening of the source / drain recess 250 and to gradually grow the thickness of the insulating layer 256 through cycles. The etching process also helps to remove dielectric material from the sidewalls of the source / drain recess 250. In examples, the cyclic deposition process may require approximately 5 to approximately 100 cycles.

[0049] Following the operations in box 127, method 100' continues to the operations in boxes 130-138, which are shared with method 100. For the sake of brevity, the shared operations will not be repeated below. After the operations in box 138, the resulting workpiece 200... Figures 24A to 24DAs shown in the diagram, the epitaxial source / drain component 264 is in-situ or out-of-situ doped with n-type or p-type dopant. For example, in some embodiments, the epitaxial source / drain component 264 comprises phosphorus-doped silicon for forming an epitaxial source / drain component for an n-type FET. In some embodiments, the epitaxial source / drain component 264 comprises boron-doped silicon germanium (SiGe) for forming an epitaxial source / drain component for a p-type FET. The semiconductor layer of the epitaxial source / drain component 264 is selectively grown on different semiconductor surfaces exposed in the source / drain trench, such as the lateral ends of the epitaxial layer 216. Because the insulating layer 256 covers the top surface of the substrate epitaxial layer 254, the epitaxial growth of the epitaxial source / drain component 264 does not occur from there. In other words, the insulating layer 256 blocks possible current paths from the bottom of the epitaxial source / drain component 264 to the fin substrate 220B (or substrate 202). Therefore, the substrate leakage current is significantly reduced. Furthermore, the epitaxial source / drain component 264-1 in the first region 204 has a smaller height and volume than the epitaxial source / drain component 264-2 in the second region 206. The epitaxial source / drain component 264-1 contacts the top channel layer 216 but does not contact the bottom channel layer (e.g., as shown in the image). Figure 24C (The bottom one shown). For comparison, the epitaxial source / drain component 264-2 contacts all available channel layers 216 in the second region 206. Therefore, the GAA transistor in the first region 204 has fewer functional channel layers than the GAA transistor formed in the second region 206.

[0050] While not intended to be limiting, embodiments of the invention offer one or more of the following advantages. For example, embodiments of the invention form an adjustable number of stacked channel layers in different regions of an IC chip that provides different functions. This is beneficial for meeting the different current drive capabilities required by individual transistors. Furthermore, some embodiments of the invention provide substrate leakage current suppression. Embodiments of the invention can be readily integrated into existing semiconductor manufacturing processes.

[0051] In one exemplary aspect, the present invention relates to a method. The method includes: forming a stack of channel layers and sacrificial layers on a substrate, the channel layers and sacrificial layers having different material compositions and being alternately disposed in a vertical direction; patterning the stack to form semiconductor fins; forming isolation members on the sidewalls of the semiconductor fins; recessing the semiconductor fins to form source / drain trenches, such that the recessed top surface of the semiconductor fins is below the top surface of the isolation members; growing a substrate epitaxial layer from the recessed top surface of the semiconductor fins; and depositing an insulating layer in the source / drain trenches. The insulating layer is located above the substrate epitaxial layer and above the bottommost channel layer. The method further includes: forming an epitaxial member in the source / drain trench, wherein the epitaxial member is located above the insulating layer. In some embodiments, the insulating layer separates the substrate epitaxial layer from the epitaxial member so that the substrate epitaxial layer does not contact the epitaxial member. In some embodiments, the insulating layer completely covers the sidewalls of the bottommost channel layer. In some embodiments, the top surface of the substrate epitaxial layer is below the bottom surface of the bottommost channel layer and above the top surface of the bottommost sacrificial layer. In some embodiments, the substrate epitaxial layer completely covers the sidewalls of the bottommost channel layer. In some embodiments, the insulating layer and the substrate epitaxial layer together cover the sidewalls of the bottommost channel layer. In some embodiments, depositing the insulating layer includes a cyclic deposition process. In some embodiments, depositing the insulating layer includes a plasma-enhanced chemical vapor deposition (PECVD) process. In some embodiments, the method further includes forming a first dielectric fin and a second dielectric fin sandwiching a semiconductor fin between them, wherein the deposited insulating layer captures a first air gap beneath the insulating layer at the corner region of the first and second dielectric fins. In some embodiments, an epitaxial member is formed to capture a second air gap between the epitaxial member and the insulating layer, and the second air gap is located above the first air gap.

[0052] In another exemplary aspect, the present invention relates to a method of manufacturing a semiconductor device. The method includes: forming an epitaxial stack of a channel layer and a sacrificial layer on a semiconductor substrate, the channel layer and the sacrificial layer having different material compositions and being stacked alternately in a vertical direction; patterning the epitaxial stack to form a first semiconductor fin in a first region of the semiconductor substrate and a second semiconductor fin in a second region of the semiconductor substrate; recessing the first semiconductor fin in a first source / drain region; recessing the second semiconductor fin in a second source / drain region; forming an epitaxial layer in the first source / drain region and the second source / drain region; forming a dielectric layer on the epitaxial layer in the first source / drain region and the second source / drain region, wherein the top surface of the dielectric layer in the first source / drain region is located above the top surface of the dielectric layer in the second source / drain region; and forming a first source / drain component in the first source / drain region and a second source / drain component in the second source / drain region, wherein the second source / drain component contacts the bottommost channel layer in the second semiconductor fin, and the first source / drain component does not contact the bottommost channel layer in the first semiconductor fin. In some embodiments, the first source / drain component does not contact two or more bottom channel layers in the first semiconductor fin. In some embodiments, forming an epitaxial layer includes: growing an epitaxial layer in a first source / drain region and a second source / drain region; depositing a masking layer covering the epitaxial layer in the second source / drain region; continuing to grow an epitaxial layer in the first source / drain region; and removing the masking layer. In some embodiments, forming a dielectric layer includes: depositing a dielectric layer such that the top surface of the dielectric layer in the first source / drain region is above the bottommost channel layer in the first semiconductor fin, and the top surface of the dielectric layer in the second source / drain region is above the bottommost channel layer in the second semiconductor fin; depositing a masking layer covering the dielectric layer in the first source / drain region; recessing the top surface of the dielectric layer in the second source / drain region; and removing the masking layer. In some embodiments, the method further includes: removing a sacrificial layer from the first semiconductor fin and the second semiconductor fin; and forming a gate structure, wherein the gate structure encloses each of the channel layers in the first semiconductor fin and the second semiconductor fin. In some embodiments, the method further includes forming internal spacers of an adjacent gate structure, wherein at least the bottommost internal spacer is laterally stacked between the dielectric layer and the gate structure.

[0053] In another exemplary aspect, the present invention relates to a semiconductor device. The semiconductor device includes: a channel layer disposed above a substrate; a gate structure covering each of the channel layer, the gate structure including a gate dielectric layer and a gate electrode layer; a first epitaxial member adjacent to a topmost channel layer; a second epitaxial member located below the first epitaxial member; an internal spacer between the first epitaxial member and the gate structure; and a dielectric layer disposed between the first epitaxial member and the second epitaxial member. The dielectric layer and the second epitaxial member separate the first epitaxial member from at least the bottommost channel layer such that the first epitaxial member does not contact at least the bottommost channel layer. In some embodiments, the dielectric layer completely covers the sidewalls of the bottommost channel layer. In some embodiments, the second epitaxial member completely covers the sidewalls of the bottommost channel layer. In some embodiments, the width of the first epitaxial member is greater than the width of the second epitaxial member.

[0054] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: A stack of trench layers and sacrificial layers is formed on a substrate, the trench layers and sacrificial layers having different material compositions and being alternately arranged in the vertical direction; Pattern the stack to form semiconductor fins; An isolation component is formed on the sidewall of the semiconductor fin; The semiconductor fin is recessed to form a source / drain groove, such that the recessed top surface of the semiconductor fin is located below the top surface of the isolation component; An epitaxial layer of the substrate is grown from the recessed top surface of the semiconductor fin; An insulating layer is deposited in the source / drain trench, wherein the insulating layer is located above the substrate epitaxial layer and above the bottommost channel layer; and An epitaxial component is formed in the source / drain groove, wherein the epitaxial component is located above the insulating layer. The insulating layer completely covers the sidewalls of the bottommost trench layer.

2. The method according to claim 1, wherein, The insulating layer separates the substrate epitaxial layer from the epitaxial component, preventing the substrate epitaxial layer from contacting the epitaxial component.

3. The method according to claim 1, wherein, The insulating layer comprises silicon oxide (SiO2) and aluminum oxide (AlO2). x Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiCON), silicon carbide (SiC), silicon carbonitride (SiOC), or combinations thereof.

4. The method according to claim 3, wherein, The top surface of the substrate epitaxial layer is located below the bottom surface of the bottommost channel layer and above the top surface of the bottommost sacrificial layer.

5. The method according to claim 1, wherein, The substrate epitaxial layer completely covers the sidewalls of the bottommost channel layer.

6. The method according to claim 1, wherein, The insulating layer and the substrate epitaxial layer together cover the sidewall of the bottommost channel layer.

7. The method according to claim 1, wherein, Depositing the insulating layer includes a cyclic deposition process.

8. The method according to claim 1, wherein, The deposition of the insulating layer includes a plasma-enhanced chemical vapor deposition (PECVD) process.

9. The method according to claim 1, further comprising: A first dielectric fin and a second dielectric fin are formed, sandwiching the semiconductor fins in between, wherein an insulating layer is deposited beneath the insulating layer at the corner region of the first dielectric fin and the second dielectric fin to capture a first air gap.

10. The method according to claim 9, wherein, The epitaxial component is formed to capture a second air gap between the epitaxial component and the insulating layer, and the second air gap is located above the first air gap.

11. A method for manufacturing a semiconductor device, comprising: An epitaxial stack of a channel layer and a sacrificial layer is formed on a semiconductor substrate, wherein the channel layer and the sacrificial layer have different material compositions and are stacked alternately in the vertical direction; The epitaxial stack is patterned to form a first semiconductor fin in a first region of the semiconductor substrate and a second semiconductor fin in a second region of the semiconductor substrate; The first semiconductor fin in the first source / drain region is recessed; The second semiconductor fin in the second source / drain region is recessed; An epitaxial layer is formed in the first source / drain region and the second source / drain region; A dielectric layer is formed on the epitaxial layer in the first source / drain region and the second source / drain region, wherein the top surface of the dielectric layer in the first source / drain region is located above the top surface of the dielectric layer in the second source / drain region; and A first source / drain component is formed in the first source / drain region and a second source / drain component is formed in the second source / drain region, wherein the second source / drain component is in contact with the bottommost channel layer in the second semiconductor fin, and the first source / drain component is not in contact with the bottommost channel layer in the first semiconductor fin. Wherein, the dielectric layer of the first source / drain region completely covers the sidewall of the bottommost channel layer in the first semiconductor fin.

12. The method according to claim 11, wherein, The first source / drain component does not contact the two or more bottom channel layers in the first semiconductor fin.

13. The method according to claim 11, wherein, Forming the epitaxial layer includes: The epitaxial layer is grown in the first source / drain region and the second source / drain region; A masking layer is deposited covering the epitaxial layer in the second source / drain region; Continue growing the epitaxial layer in the first source / drain region; and Remove the masking layer.

14. The method according to claim 11, wherein, Forming the dielectric layer includes: The dielectric layer is deposited such that the top surface of the dielectric layer in the first source / drain region is above the bottommost channel layer in the first semiconductor fin, and the top surface of the dielectric layer in the second source / drain region is above the bottommost channel layer in the second semiconductor fin. A masking layer is deposited covering the dielectric layer in the first source / drain region; The top surface of the dielectric layer in the second source / drain region is recessed; and Remove the masking layer.

15. The method of claim 11, further comprising: Remove the sacrificial layer from the first semiconductor fin and the second semiconductor fin; as well as A gate structure is formed, wherein the gate structure encloses each of the channel layers in the first semiconductor fin and the second semiconductor fin.

16. The method of claim 15, further comprising: An internal spacer is formed adjacent to the gate structure, wherein at least the bottommost internal spacer is laterally stacked between the dielectric layer and the gate structure.

17. A semiconductor device, comprising: The channel layer is disposed above the substrate; A gate structure covering each of the channel layers, wherein the gate structure includes a gate dielectric layer and a gate electrode layer; The first epitaxial component is adjacent to the topmost trench layer; The second epitaxial component is located below the first epitaxial component; An internal spacer, located between the first epitaxial member and the gate structure; and A dielectric layer is disposed between the first epitaxial component and the second epitaxial component. The dielectric layer and the second epitaxial component separate the first epitaxial component from at least the bottommost channel layer, preventing the first epitaxial component from contacting at least the bottommost channel layer. The dielectric layer completely covers the sidewalls of the bottommost channel layer.

18. The semiconductor device according to claim 17, wherein, The dielectric layer includes silicon oxide (SiO2), aluminum oxide (AlOx), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiCON), silicon carbide (SiC), silicon carbonitride (SiOC), or combinations thereof.

19. The semiconductor device according to claim 17, wherein, The second extensional component completely covers the sidewall of the bottommost channel layer.

20. The semiconductor device according to claim 17, wherein, The width of the first epitaxial component is greater than the width of the second epitaxial component.

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