SiC Trench MOSFET device manufacturing method, device, equipment and production method

Abstract

The present invention provides a method for manufacturing a SiC Trench MOSFET device, comprising: providing a substrate; sequentially forming a buffer layer, a first epitaxial layer, and a first gate oxide layer on the substrate; wherein the first epitaxial layer includes a groove; the first gate oxide layer is formed in the groove; forming a second epitaxial layer, a body ion implantation layer, a source ion implantation layer, a p-type ion implantation layer, a p+-type ion implantation layer, a second gate oxide layer, a gate trench, a gate, an interlayer dielectric layer, a contact hole, and a metal layer; wherein the thickness of the formed first gate oxide layer is 200-500nm. The technical solution provided in this application, through a step-by-step epitaxy method, solves the technical problem that the thickness of the formed first gate oxide layer cannot meet the device performance requirements, and further solves the problem of low device breakdown voltage caused by the bottom gate oxide thickness not meeting the requirements, thereby achieving the technical effect of effectively protecting the relatively weak trench bottom of the SiC Trench MOSFET device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a manufacturing method, device, equipment and production method of a SiC Trench MOSFET device. Background Art

[0002] Currently, SiC product failures primarily occur due to the inability of the gate oxide at the bottom of the trench to withstand high Vds. Currently, the mainstream method for trench bottom protection is P Shield. Therefore, developing a process for forming a trench bottom protection layer by other means to ensure that the gate oxide at the bottom of the trench can withstand high gate voltages, thereby increasing the breakdown voltage at the bottom of the device and protecting the device, remains a pressing technical challenge for those skilled in the art. Summary of the Invention

[0003] The present invention provides a manufacturing method, device, equipment and production method of a SiC Trench MOSFET device, so as to solve the problem that the thickness of the formed first gate oxide layer cannot meet the performance requirements of the device.

[0004] According to a first aspect of the present invention, there is provided a method for manufacturing a SiC Trench MOSFET device, comprising:

[0005] providing a substrate;

[0006] forming a buffer layer, a first epitaxial layer, and a first gate oxide layer in sequence on the substrate; wherein the first epitaxial layer includes a groove; and the first gate oxide layer is formed in the groove;

[0007] A second epitaxial layer, a body ion implantation layer, a source ion implantation layer, a p-type ion implantation layer, a p+-type ion implantation layer, a second gate oxide layer, a gate trench, a gate, an interlayer dielectric layer, a contact hole, and a metal layer are formed; wherein the second epitaxial layer is formed on the first epitaxial layer; the body ion implantation layer and the source ion implantation layer are sequentially formed on the surface of the second epitaxial layer; the gate trench is formed at the top of the first gate oxide layer and penetrates the second epitaxial layer, the body ion implantation layer, and the source ion implantation layer; the second gate oxide layer is formed on the sidewall of the gate trench and on the surface of the first gate oxide layer; the gate is formed in the gate trench; the p-type ion implantation layer is formed in a portion of the second epitaxial layer and a portion of the body ion implantation layer on both sides of the first gate oxide layer; the p+-type ion implantation layer is formed at the top of the p-type ion implantation layer and penetrates the source ion implantation layer; the interlayer dielectric layer is formed at the top of the gate and spans the gate; the metal layer is formed in the contact hole and surrounds the interlayer dielectric layer;

[0008] Wherein, the thickness of the formed first gate oxide layer is 200-500 nm.

[0009] Optionally, after forming the contact hole, the method further includes:

[0010] A bonding layer is formed; the bonding layer surrounds the interlayer dielectric layer and covers the bottom of the contact hole; and the metal layer is formed on the bonding layer.

[0011] Optionally, forming a buffer layer, a first epitaxial layer, and a first gate oxide layer in sequence on the substrate specifically includes:

[0012] forming the buffer layer and the first epitaxial layer in sequence on the substrate;

[0013] Depositing a first hard mask on the first epitaxial layer; forming a patterned first hard mask, and etching the first epitaxial layer using the patterned first hard mask as a mask to form the groove in the first epitaxial layer;

[0014] depositing a gate oxide material in the groove and on the surface of the first epitaxial layer;

[0015] The gate oxide material on the surface of the first epitaxial layer is etched away to form the first gate oxide layer in the groove.

[0016] Optionally, forming a second epitaxial layer, a body ion implantation layer, a source ion implantation layer, a p-type ion implantation layer, a p+-type ion implantation layer, a second gate oxide layer, a gate trench, a gate, an interlayer dielectric layer, a contact hole, and a metal layer specifically includes:

[0017] forming the second epitaxial layer and the first oxide layer on the surface of the first epitaxial layer, and sequentially forming the body region ion implantation layer and the source region ion implantation layer on the surface of the second epitaxial layer;

[0018] forming the p+ type ion implantation layer and the p type ion implantation layer;

[0019] forming the gate trench and removing the first oxide layer;

[0020] The gate, the interlayer dielectric layer, the contact hole and the metal layer are formed.

[0021] Optionally, forming a p+ type ion implantation layer and a p type ion implantation layer specifically includes:

[0022] depositing a second hard mask layer on the surface of the first oxide layer;

[0023] forming a patterned second hard mask layer, wherein the patterned second hard mask layer is formed on a surface of the first oxide layer on top of the second gate oxide layer;

[0024] Using the patterned second hard mask layer as a barrier layer, p-type ions are injected into part of the second epitaxial layer and part of the body ion injection layer on both sides of the gate trench to form the p-type ion injection layer; and p+ type ions are injected into part of the body ion injection layer and the source ion injection layer on top of the p-type ion injection layer to form the p+ type ion injection layer.

[0025] Optionally, forming a gate trench and removing the first oxide layer specifically includes:

[0026] forming a third hard mask layer on top of the first oxide layer;

[0027] forming a patterned third hard mask layer;

[0028] Using the patterned third hard mask layer as a mask, etching the second epitaxial layer, the body ion implantation layer, the source ion implantation layer, and the first oxide layer on top of the first gate oxide layer to form the gate trench on top of the first gate oxide layer; wherein the pattern of the patterned third hard mask layer is adapted to the shape of the top of the first gate oxide layer;

[0029] The remaining first oxide layer and the patterned third hard mask layer are removed.

[0030] Optionally, forming a gate, an interlayer dielectric layer, a contact hole, and a metal layer specifically includes:

[0031] growing a gate oxide material on the sidewalls of the gate trench, the top of the first gate oxide layer, the surface of the source ion implantation layer, and the surface of the p+ type ions;

[0032] Depositing a gate material on the surface of the gate oxide material; the gate material covers the surface of the gate oxide material and fills the gate trench;

[0033] Etching the gate material outside the gate trench to expose the gate oxide material, so as to form the gate in the gate trench;

[0034] Depositing an interlayer dielectric layer material on the surface of the gate oxide material outside the gate trench and on the top of the gate;

[0035] Etching the interlayer dielectric layer material and the gate oxide material outside the gate trench to form the second gate oxide layer and the contact hole; the contact hole is formed on both sides of the interlayer dielectric layer;

[0036] A metal material is deposited in the contact hole and on the interlayer dielectric layer to form the metal layer.

[0037] According to a second aspect of the present invention, there is provided a SiC Trench MOSFET device, which is manufactured according to the method for manufacturing a SiC Trench MOSFET according to any one of the first aspects of the present invention, comprising:

[0038] A substrate; and a buffer layer, a first epitaxial layer, and a first gate oxide layer sequentially formed on the substrate; wherein the first epitaxial layer includes a groove; and the gate oxide layer is formed in the groove;

[0039] The second epitaxial layer, the body ion implantation layer, the source ion implantation layer, the p-type ion implantation layer, the p+ type ion implantation layer, the second gate oxide layer, the gate trench, the gate, the interlayer dielectric layer, the contact hole and the metal layer; wherein the thickness of the first gate oxide layer is 200-500nm.

[0040] According to a third aspect of the present invention, an electronic device is provided, comprising the SiC Trench MOSFET device according to the second aspect of the present invention.

[0041] According to a fourth aspect of the present invention, there is provided a method for manufacturing an electronic device, comprising the method for manufacturing a SiC Trench MOSFET device according to any one of the first aspects of the present invention.

[0042] The present invention provides a method for manufacturing a SiC Trench MOSFET device. First, a first epitaxial layer is formed on a buffer layer through step-by-step epitaxy. The surface layer of the first epitaxial layer includes a groove, and a gate oxide material is deposited in the groove to form a first gate oxide layer. Next, a second epitaxial layer and other structural layers are grown. Since the groove is relatively shallow, a thicker first gate oxide layer can be formed in the first epitaxial layer. Thus, the technical solution provided by the present application, through step-by-step epitaxy, solves the technical problem of the thickness of the formed first gate oxide layer failing to meet device performance requirements. Furthermore, it solves the problem of low device breakdown voltage due to the bottom gate oxide thickness not meeting the requirements, thereby achieving the technical effect of effectively protecting the relatively weak trench bottom of the SiC Trench MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 11 is a flow chart of a method for manufacturing a SiC Trench MOSFET device provided by one embodiment of the present invention;

[0045] Figure 2 Schematic diagram of the device structure at different process stages according to the method for manufacturing a SiC Trench MOSFET device provided by one embodiment of the present invention Figure 1 ;

[0046] Figure 3 Schematic diagram of the device structure at different process stages according to the method for manufacturing a SiC Trench MOSFET device provided by another embodiment of the present invention Figure 2 ;

[0047] Figure 4 Schematic diagram of the device structure at different process stages according to the method for manufacturing a SiC Trench MOSFET device provided by one embodiment of the present invention Figure 3 ;

[0048] Figure 5 Schematic diagram of the device structure at different process stages according to the method for manufacturing a SiC Trench MOSFET device provided by one embodiment of the present invention Figure 4 ;

[0049] Figure 6 Schematic diagram of the device structure at different process stages according to the method for manufacturing a SiC Trench MOSFET device provided by one embodiment of the present invention Figure 5 ;

[0050] Figure 7 Schematic diagram of the device structure at different process stages according to the method for manufacturing a SiC Trench MOSFET device provided by one embodiment of the present invention Figure 6 ;

[0051] Figure 8 Schematic diagram of the device structure at different process stages according to the method for manufacturing a SiC Trench MOSFET device provided by one embodiment of the present invention Figure 7 ;

[0052] Figure 9 Schematic diagram of the device structure at different process stages according to the method for manufacturing a SiC Trench MOSFET device provided by one embodiment of the present invention Figure 8 ;

[0053] Description of reference numerals:

[0054] 101-substrate;

[0055] 102- buffer layer;

[0056] 103 first epitaxial layer;

[0057] 104 first gate oxide layer;

[0058] 105-body ion implantation layer;

[0059] 106--Source region ion implantation layer;

[0060] 107-first oxide layer;

[0061] 108-p+ type ion implantation layer;

[0062] 109-p-type ion implantation layer;

[0063] 110-gate oxide material;

[0064] 111- second gate oxide layer;

[0065] 112-gate;

[0066] 113-interlayer dielectric layer;

[0067] 114-adhesive layer;

[0068] 115-contact hole;

[0069] 116-metal layer;

[0070] 117 - Second epitaxial layer. DETAILED DESCRIPTION

[0071] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0072] The terms "first," "second," "third," "fourth," and the like (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0073] Traditional SiC Trench MOSFET device manufacturing methods include:

[0074] 1. Provide a substrate;

[0075] 2. Forming a buffer layer, an epitaxial layer, and an oxide layer on the substrate in sequence; sequentially implanting body ions and source ions into the surface layer of the epitaxial layer, so that a body ion implantation layer and a source ion implantation layer are sequentially formed in the surface layer of the epitaxial layer; and sequentially forming a p-type ion implantation layer and a p+-type ion implantation layer in the body ion implantation layer, the source ion implantation layer, and the epitaxial layer at the edges;

[0076] 3. Etching the body ion implantation layer, source ion implantation layer and epitaxial layer to form a gate trench;

[0077] 4. Implanting p-type ions at the bottom of the gate trench to form a bottom protective layer, or depositing a gate oxide material at the bottom to form a bottom gate oxide layer; wherein the thickness of the bottom gate oxide layer is 10-200 nm;

[0078] 5. Form a gate oxide layer, a gate electrode, an interlayer dielectric layer, an adhesive layer and a metal layer.

[0079] In traditional SiC Trench MOSFET device manufacturing methods, the bottom gate oxide layer is formed after the gate trench is formed. Due to the deep gate trench, the thickness of the gate oxide material deposited in the deep gate trench is limited. Therefore, the bottom gate oxide layer formed by traditional technical means is limited in thickness and cannot achieve the purpose of protecting the weaker bottom of the device.

[0080] In view of this, the inventors of the present application formed epitaxial layers in steps. First, a first epitaxial layer was formed on a buffer layer, a groove was formed in the first epitaxial layer, and a gate oxide material was deposited in the groove to form a bottom gate oxide layer. Then, a second epitaxial layer and other structural layers were grown. Since the groove depth is small, a thicker bottom gate oxide layer can be formed in the first epitaxial layer. The thickness of the formed bottom gate oxide layer can reach 200-500nm.

[0081] It can be seen that the technical solution provided by this application can solve the technical problem that the thickness of the bottom gate oxide cannot meet the requirements of device performance, and thus solves the problem of low device breakdown voltage caused by the bottom gate oxide thickness not meeting the requirements in traditional technical means, thereby achieving protection of the device.

[0082] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0083] Please refer to Figures 1-9 ,in, Figure 1 The present invention provides a method for manufacturing a SiC Trench MOSFET device, comprising:

[0084] S11: providing a substrate 101;

[0085] S12: forming a buffer layer 102, a first epitaxial layer 103, and a first gate oxide layer 104 in sequence on the substrate 101; wherein the first epitaxial layer 103 includes a groove; and the first gate oxide layer 104 is formed in the groove;

[0086] S13: forming a second epitaxial layer 117, a body ion implantation layer 105, a source ion implantation layer 106, a p-type ion implantation layer 109, a p+ type ion implantation layer 108, a second gate oxide layer 111, a gate trench, a gate 112, an interlayer dielectric layer 113, a contact hole 115 and a metal layer 116; wherein the second epitaxial layer 117 is formed on the first epitaxial layer 103; the body ion implantation layer 105 and the source ion implantation layer 106 are sequentially formed on the surface of the second epitaxial layer 117; A gate trench is formed at the top of the first gate oxide layer 104 and penetrates the second epitaxial layer 117, the body ion implantation layer 105 and the source ion implantation layer 106; the second gate oxide layer 111 is formed on the sidewalls of the gate trench and the surface of the first gate oxide layer 104; the gate 112 is formed in the gate trench; the p-type ion implantation layer 109 is formed in a portion of the second epitaxial layer 117 and a portion of the body ion implantation layer 105 on both sides of the first gate oxide layer 104; the p+ type ion implantation layer 108 is formed at the top of the p-type ion implantation layer 109 and penetrates the source ion implantation layer 106; the interlayer dielectric layer 113 is formed at the top of the gate 112 and spans the gate 112; the metal layer 116 is formed in the contact hole 115 and surrounds the interlayer dielectric layer 113; Figure 9 As shown;

[0087] The thickness of the formed first gate oxide layer 104 is 200-500 nm. The first oxide layer 107 with a thickness within the range of 200-500 nm can withstand a higher gate voltage and protect the bottom of the gate trench.

[0088] The present invention provides a method for manufacturing a SiC Trench MOSFET device, wherein a first epitaxial layer 103 and a second epitaxial layer 117 are sequentially formed by step-by-step epitaxy, and a first gate oxide layer 104 is simultaneously formed, and then other structural layers are formed. The first gate oxide layer 104 is formed in a groove in the surface layer of the first epitaxial layer 103. The process of forming the first gate oxide layer 104 by step-by-step epitaxy specifically includes: first, forming the first epitaxial layer 103 on the buffer layer 102, wherein the surface layer of the first epitaxial layer 103 includes a groove, and depositing a gate oxide material in the groove to form the first gate oxide layer 104; second, growing the second epitaxial layer 117 and other structural layers; wherein, due to the small depth of the groove, a first gate oxide layer 104 with a large thickness (200-500nm) can be formed in the first epitaxial layer 103.

[0089] It can be seen that the technical solution provided in the present application solves the technical problem that the thickness of the first gate oxide layer 104 formed cannot meet the device performance requirements through step-by-step epitaxy, and further solves the problem of low device breakdown voltage caused by the bottom gate oxide thickness not meeting the requirements, thereby achieving the technical effect of effectively protecting the relatively weak trench bottom of the SiC Trench MOSFET device.

[0090] In one embodiment, in step S13, after forming the contact hole 115 in the interlayer dielectric layer 113, the step further includes:

[0091] An adhesive layer 114 is formed; the adhesive layer 114 surrounds the interlayer dielectric layer 113 and covers the bottom of the contact hole 115 ; and the metal layer 116 is formed on the adhesive layer 114 .

[0092] In one embodiment, step S12, sequentially forming a buffer layer 102, a first epitaxial layer 103, and a first gate oxide layer 104 on the substrate 101, specifically includes:

[0093] S121: forming the buffer layer 102 and the first epitaxial layer 103 in sequence on the substrate 101;

[0094] S122: depositing a first hard mask on the first epitaxial layer 103; S123: forming a patterned first hard mask, and etching the first epitaxial layer 103 using the patterned first hard mask as a mask to form the groove in the first epitaxial layer 103;

[0095] S124: depositing a gate oxide material in the groove and on the surface of the first epitaxial layer 103; specifically, depositing the gate oxide material by thermal oxidation or depositing an oxide layer, or by a combination of thermal oxidation and depositing an oxide layer;

[0096] S125: etching away the gate oxide material on the surface of the first epitaxial layer 103 to form the first gate oxide layer 104 in the groove. Figure 2 shown.

[0097] Since the gate material in the center of the groove is lower than the edge of the groove after the gate material is filled in the groove and before the gate material is etched, the gate oxide material in the groove is rounded under isotropic etching, forming a bottom arc. Figure 3 As shown;

[0098] After the gate oxide material in the groove is rounded, the surface of the formed first gate oxide layer 104 is arc-shaped; compared with the horizontal surface of the first oxide layer 107, the arc-shaped surface of the first oxide layer 107 makes the bottom electric field of the device more gentle, which is beneficial to increase the breakdown voltage of the device and improve the reliability of the device;

[0099] The technical solution provided by the present invention forms the first oxide layer by depositing gate oxide material. Compared with the prior art method of forming the bottom gate oxide by injecting ions, the method of depositing gate oxide material to form the first oxide layer is more controllable and has fewer device defects. Furthermore, the first oxide layer can better improve the ability of the trench bottom to resist electric field concentration, thereby improving the breakdown voltage and reliability of the device.

[0100] In one embodiment, step S13, forming the second epitaxial layer 117, the body ion implantation layer 105, the source ion implantation layer 106, the p-type ion implantation layer 109, the p+-type ion implantation layer 108, the second gate oxide layer 111, the gate trench, the gate 112, the interlayer dielectric layer 113, the contact hole 115, and the metal layer 116, specifically includes:

[0101] S131: forming the second epitaxial layer 117 and the first oxide layer 107 on the surface of the first epitaxial layer 103, and sequentially forming the body region ion implantation layer 105 and the source region ion implantation layer 106 on the surface of the second epitaxial layer 117, as shown in FIG. Figure 4 As shown;

[0102] S132: forming the p+ type ion implantation layer 108 and the p type ion implantation layer 109, as shown in FIG. Figure 5 As shown;

[0103] In one embodiment, step S132, forming the p+ type ion implantation layer 108 and the p type ion implantation layer 109, specifically includes:

[0104] S1321: depositing a second hard mask layer on the surface of the first oxide layer 107;

[0105] S1322: forming a patterned second hard mask layer, wherein the patterned second hard mask layer is formed on the surface of the first oxide layer 107 on the top of the second gate oxide layer 111;

[0106] S1323: Using the patterned second hard mask layer as a barrier layer, p-type ions are injected into a portion of the second epitaxial layer 117 on both sides of the gate trench and a portion of the body ion injection layer 105 to form the p-type ion injection layer 109; and p+ type ions are injected into a portion of the body ion injection layer 105 and the source ion injection layer 106 at the top of the p-type ion injection layer 109 to form the p+ type ion injection layer 108.

[0107] S133: forming the gate trench and removing the first oxide layer 107, as shown in FIG. Figure 6 As shown;

[0108] In one embodiment, step S133, forming a gate trench and removing the first oxide layer 107, specifically includes:

[0109] S1331: forming a third hard mask layer on top of the first oxide layer 107;

[0110] S1332: forming a patterned third hard mask layer;

[0111] S1333: Using the patterned third hard mask layer as a mask, etching the second epitaxial layer 117, the body ion implantation layer 105, the source ion implantation layer 106, and the first oxide layer 107 on the top of the first gate oxide layer 104 to form the gate trench on the top of the first gate oxide layer 104; wherein the pattern of the patterned third hard mask layer is adapted to the shape of the top of the first gate oxide layer 104;

[0112] S1334: removing the remaining first oxide layer 107 and the patterned third hard mask layer.

[0113] S134 : forming the gate 112 , the interlayer dielectric layer 113 , the contact hole 115 and the metal layer 116 .

[0114] In one embodiment, step S134, forming the gate 112, the interlayer dielectric layer 113, the contact hole 115, and the metal layer 116, specifically includes:

[0115] S1341: growing a gate oxide material 110 on the sidewalls of the gate trench, the top of the first gate oxide layer 104, the surface of the source ion implantation layer 106, and the surface of the p+ type ions;

[0116] In a specific embodiment, the material of the first epitaxial layer and the second epitaxial layer is SIC. When the material of the first epitaxial layer and the second epitaxial layer is SIC, carbon may be deposited on the surfaces of the first epitaxial layer and the second epitaxial layer at high temperature, thereby causing defects. Therefore, to prevent carbon deposition on the surfaces of the first epitaxial layer and the second epitaxial layer, the steps before S1341 include: depositing a carbon film, performing ion activation, and removing the carbon film; S1342: depositing a gate material on the surface of the gate oxide material 110; the gate material covers the surface of the gate oxide material 110 and fills the gate trench;

[0117] S1343: etching the gate material outside the gate trench to expose the gate oxide material 110,

[0118] To form the gate 112 in the gate trench, as shown in FIG. Figure 7 As shown;

[0119] S1344: Depositing an interlayer dielectric layer 113 material on the surface of the gate oxide material 110 outside the gate trench and on the top of the gate 112;

[0120] S1345: Etching the interlayer dielectric layer 113 material and the gate oxide material 110 outside the gate trench to form the second gate oxide layer 111 and the contact hole 115; the contact hole 115 is formed on both sides of the interlayer dielectric layer 113, as shown in FIG. Figure 8 As shown;

[0121] S1346: Depositing metal material in the contact hole 115 and on the interlayer dielectric layer 113 to form the metal layer 116, as shown in FIG. Figure 9 shown.

[0122] According to another embodiment of the present invention, there is further provided a SiC Trench MOSFET device, which is manufactured according to the SiC Trench MOSFET manufacturing method according to any of the aforementioned embodiments of the present invention, comprising:

[0123] A substrate 101; and a buffer layer 102, a first epitaxial layer 103, and a first gate oxide layer 104 sequentially formed on the substrate 101; wherein the first epitaxial layer 103 includes a groove; the gate oxide layer is formed in the groove;

[0124] The second epitaxial layer 117, the body ion implantation layer 105, the source ion implantation layer 106, the p-type ion implantation layer 109, the p+ type ion implantation layer 108, the second gate oxide layer 111, the gate trench, the gate 112, the interlayer dielectric layer 113, the contact hole 115 and the metal layer 116; wherein the thickness of the first gate oxide layer 104 is 200-500nm, the SiC Trench MOSFET device is as follows Figure 9 shown.

[0125] The present application provides a SiC Trench MOSFET device in which the thickness of the first gate oxide layer 104 can reach 200-500 nm. This solves the technical problem that the thickness of the first gate oxide layer 104 cannot meet the device performance requirements. This further solves the problem of low device breakdown voltage caused by the bottom gate oxide thickness not meeting the requirements, thereby achieving the technical effect of effectively protecting the relatively weak trench bottom of the SiC Trench MOSFET device.

[0126] Secondly, according to an embodiment of the present invention, an electronic device is provided, comprising the SiC Trench MOSFET device described in the foregoing embodiment of the present invention.

[0127] In addition, according to an embodiment of the present invention, a method for manufacturing an electronic device is provided, including the method for manufacturing the SiC Trench MOSFET device according to any one of the aforementioned embodiments of the present invention.

[0128] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a SiC Trench MOSFET device, characterized in that: include: providing a substrate; forming a buffer layer, a first epitaxial layer, and a first gate oxide layer in sequence on the substrate; wherein the first epitaxial layer includes a groove; and the first gate oxide layer is formed in the groove; A second epitaxial layer, a body ion implantation layer, a source ion implantation layer, a p-type ion implantation layer, a p+-type ion implantation layer, a second gate oxide layer, a gate trench, a gate, an interlayer dielectric layer, a contact hole, and a metal layer are formed; wherein the second epitaxial layer is formed on the first epitaxial layer; the body ion implantation layer and the source ion implantation layer are sequentially formed on the surface of the second epitaxial layer; the gate trench is formed at the top of the first gate oxide layer and penetrates the second epitaxial layer, the body ion implantation layer, and the source ion implantation layer; the second gate oxide layer is formed on the sidewall of the gate trench and on the surface of the first gate oxide layer; the gate is formed in the gate trench; the p-type ion implantation layer is formed in a portion of the second epitaxial layer and a portion of the body ion implantation layer on both sides of the first gate oxide layer; the p+-type ion implantation layer is formed at the top of the p-type ion implantation layer and penetrates the source ion implantation layer; the interlayer dielectric layer is formed at the top of the gate and spans the gate; the metal layer is formed in the contact hole and surrounds the interlayer dielectric layer; Wherein, the thickness of the formed first gate oxide layer is 200-500 nm; After forming the contact hole, the method further includes: forming a bonding layer; the bonding layer surrounds the interlayer dielectric layer and covers the bottom of the contact hole; and the metal layer is formed on the bonding layer.

2. The method for manufacturing a SiC Trench MOSFET device according to claim 1, wherein: Sequentially forming a buffer layer, a first epitaxial layer, and a first gate oxide layer on the substrate includes: forming the buffer layer and the first epitaxial layer in sequence on the substrate; Depositing a first hard mask on the first epitaxial layer; forming a patterned first hard mask, and etching the first epitaxial layer using the patterned first hard mask as a mask to form the groove in the first epitaxial layer; depositing a gate oxide material in the groove and on the surface of the first epitaxial layer; The gate oxide material on the surface of the first epitaxial layer is etched away to form the first gate oxide layer in the groove.

3. The method for manufacturing a SiC Trench MOSFET device according to claim 2, wherein: Forming a second epitaxial layer, a body ion implantation layer, a source ion implantation layer, a p-type ion implantation layer, a p+-type ion implantation layer, a second gate oxide layer, a gate trench, a gate, an interlayer dielectric layer, a contact hole, and a metal layer, specifically includes: forming the second epitaxial layer and the first oxide layer on the surface of the first epitaxial layer, and sequentially forming the body region ion implantation layer and the source region ion implantation layer on the surface of the second epitaxial layer; forming the p+ type ion implantation layer and the p type ion implantation layer; forming the gate trench and removing the first oxide layer; The gate, the interlayer dielectric layer, the contact hole and the metal layer are formed.

4. The method for manufacturing a SiC Trench MOSFET device according to claim 3, wherein: Forming a p+ type ion implantation layer and a p type ion implantation layer specifically includes: depositing a second hard mask layer on the surface of the first oxide layer; forming a patterned second hard mask layer, wherein the patterned second hard mask layer is formed on a surface of the first oxide layer on top of the second gate oxide layer; Using the patterned second hard mask layer as a barrier layer, p-type ions are injected into part of the second epitaxial layer and part of the body ion injection layer on both sides of the gate trench to form the p-type ion injection layer; and p+ type ions are injected into part of the body ion injection layer and the source ion injection layer on top of the p-type ion injection layer to form the p+ type ion injection layer.

5. The method for manufacturing a SiC Trench MOSFET device according to claim 4, wherein: Forming a gate trench and removing the first oxide layer specifically includes: forming a third hard mask layer on top of the first oxide layer; forming a patterned third hard mask layer; Using the patterned third hard mask layer as a mask, etching the second epitaxial layer, the body ion implantation layer, the source ion implantation layer, and the first oxide layer on top of the first gate oxide layer to form the gate trench on top of the first gate oxide layer; wherein the pattern of the patterned third hard mask layer is adapted to the shape of the top of the first gate oxide layer; The remaining first oxide layer and the patterned third hard mask layer are removed.

6. The method for manufacturing a SiC Trench MOSFET device according to claim 5, wherein: Forming gates, interlayer dielectric layers, contact holes, and metal layers, specifically including: growing a gate oxide material on the sidewalls of the gate trench, the top of the first gate oxide layer, the surface of the source ion implantation layer, and the surface of the p+ type ions; Depositing a gate material on the surface of the gate oxide material; the gate material covers the surface of the gate oxide material and fills the gate trench; Etching the gate material outside the gate trench to expose the gate oxide material, so as to form the gate in the gate trench; Depositing an interlayer dielectric layer material on the surface of the gate oxide material outside the gate trench and on the top of the gate; Etching the interlayer dielectric layer material and the gate oxide material outside the gate trench to form the second gate oxide layer and the contact hole; the contact hole is formed on both sides of the interlayer dielectric layer; A metal material is deposited in the contact hole and on the interlayer dielectric layer to form the metal layer.

7. A SiC Trench MOSFET device, characterized in that: The SiCTrench MOSFET is manufactured according to the manufacturing method of any one of claims 1 to 6, comprising: A substrate; and a buffer layer, a first epitaxial layer, and a first gate oxide layer sequentially formed on the substrate; wherein the first epitaxial layer includes a groove; and the gate oxide layer is formed in the groove; The second epitaxial layer, the body ion implantation layer, the source ion implantation layer, the p-type ion implantation layer, the p+ type ion implantation layer, the second gate oxide layer, the gate trench, the gate, the interlayer dielectric layer, the contact hole and the metal layer; wherein the thickness of the first gate oxide layer is 200-500nm.

8. An electronic device, characterized in that: Including the SiC Trench MOSFET device according to claim 7.

9. A method for manufacturing an electronic device, characterized in that: A method for manufacturing a SiC TrenchMOSFET device comprising the steps of:

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