Stacked nanosheet gaa-fet device and method of fabrication thereof

Abstract

The application provides a stacked nanosheet GAA-FET device and a manufacturing method thereof. A stacked layer of first semiconductor layers and second semiconductor layers is formed on a substrate; a fin is etched from the stacked layer; a partial region at both ends of the first semiconductor layer is etched from outside to inside, and a second sidewall is formed at both ends of the first semiconductor layer; the first semiconductor layer is removed to release a nanosheet channel, and the second semiconductor layer serves as the channel; an overlapping region of the second sidewall and the channel region is laterally etched to form a gap; an interface oxide layer is formed in the gap, and a first high-k dielectric layer and a second high-k dielectric layer are alternately stacked until the gap is completely filled, the interface oxide layer and a third high-k dielectric layer are formed around the channel, and a metal gate surrounding the channel is formed. The superlattice structure of the first high-k dielectric layer and the second high-k dielectric layer maximally inhibits the conduction of the electric field to the overlapping region of the source and the drain and the channel, weakens the electric field intensity of the overlapping region, inhibits band-to-band tunneling leakage, and avoids the leakage of the device in the off state.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a stacked nanosheet GAA-FET device and a manufacturing method thereof. BACKGROUND

[0002] With the continuous scaling of integrated circuit feature size, the traditional three-gate or double-gate fin field-effect transistor (FinFET) is limited at the 3nm node, and the nanoribbon gate transistor (Gate-all-around Field-Effect Transistor, GAA-FET) compatible with the mainstream post-high-k metal gate FinFET process will be the next generation of key structures to achieve size scaling. The channel of the GAA-FET is mainly a stacked nanosheet structure. However, there is band-to-band tunneling (BTBT) leakage in the overlapping area between the source-drain region and the channel of the GAA-FET, which causes the off-state leakage of the device to increase sharply. SUMMARY

[0003] Therefore, the purpose of the present application is to provide a stacked nanosheet GAA-FET device and a manufacturing method thereof, which suppresses the generation of band-to-band tunneling leakage in the overlapping area between the source-drain region and the channel, avoids the off-state leakage of the device, and improves the performance of the device. The specific scheme is as follows:

[0004] In a first aspect, the present application provides a manufacturing method of a stacked nanosheet GAA-FET device, comprising:

[0005] forming a stacked layer of first semiconductor layers and second semiconductor layers alternately stacked on a substrate;

[0006] etching the stacked layer to form a fin, and forming a dummy gate and a first sidewall on the fin;

[0007] etching the first semiconductor layers from the outside to the inside in the partial area at both ends of the first semiconductor layers to form a second sidewall at both ends of the first semiconductor layers;

[0008] removing the first semiconductor layers to release nanosheet channels, and the second semiconductor layers as channels;

[0009] laterally etching the overlapping area of the second sidewall and the channel to form a gap;

[0010] forming an interface oxide layer and alternately stacking a first high-k dielectric layer and a second high-k dielectric layer in the gap until the gap is completely filled;

[0011] An interface oxide layer and a third high-k dielectric layer are formed around the channel, and a metal gate is formed to surround the channel.

[0012] In a second aspect, the embodiments of the present application further provide a stacked nanosheet GAA-FET device, comprising:

[0013] a substrate, a fin located on one side of the substrate; the fin comprising a plurality of second semiconductor layers, the second semiconductor layers serving as channels;

[0014] a high-k metal gate structure comprising an interface oxide layer, alternately stacked first high-k dielectric layers and second high-k dielectric layers, a third high-k dielectric layer, and a metal gate; the metal gate surrounds the second semiconductor layers, and the metal gate has second sidewalls at both ends; the interface oxide layer and the alternately stacked first high-k dielectric layers and second high-k dielectric layers are located between the channels and the second sidewalls; and the interface oxide layer and the third high-k dielectric layer are located at the periphery of the channels.

[0015] The embodiments of the present application provide a stacked nanosheet GAA-FET device and a manufacturing method thereof. A stacked layer of alternately stacked first semiconductor layers and second semiconductor layers is formed on a substrate; the stacked layer is etched to form a fin, and a dummy gate and a first sidewall are formed on the fin; a partial region at both ends of the first semiconductor layers is etched from the outside to the inside to form second sidewalls at both ends of the first semiconductor layers; the first semiconductor layers are removed to release nanosheet channels, and the second semiconductor layers serve as channels; the overlapping regions of the second sidewalls and the channel regions are laterally etched to form voids; an interface oxide layer, and alternately stacked first high-k dielectric layers and second high-k dielectric layers are formed in the voids until the voids are completely filled, an interface oxide layer and a third high-k dielectric layer are formed around the channels, and a metal gate is formed to surround the channels. In this way, compared with the prior art, in which the electric field generated by the metal gate is conducted to the overlapping region of the source-drain region and the channel to cause band-to-band tunneling leakage, in the embodiments of the present application, the overlapping region of the source-drain region and the channel is maximally inhibited from being conducted to by forming alternately stacked multiple layers of first high-k dielectric layers and second high-k dielectric layers between the channels and the second sidewalls to completely fill the voids, forming a superlattice structure, weakening the electric field intensity of the overlapping region of the source-drain region and the channel, changing the electric field distribution of the overlapping region, thereby inhibiting the generation of band-to-band tunneling leakage in the overlapping region of the source-drain region and the channel, avoiding device off-state leakage, and improving device performance. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained on the basis of these drawings without creative labor.

[0017] Figure 1 A flowchart of a manufacturing method of a stacked nanosheet GAA-FET device is shown.

[0018] Figures 2-21 A structure diagram of a stacked nanosheet GAA-FET device is shown. DETAILED DESCRIPTION

[0019] In order to make the above-mentioned purposes, features and advantages of the present application more apparent and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0020] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the connotation of the present application, therefore the present application is not limited by the specific embodiments disclosed below.

[0021] Secondly, the present application is described in detail in combination with the schematic diagram, and in the detailed description of the embodiments of the present application, for the convenience of description, the cross-sectional view showing the device structure will be partially enlarged without general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present application herein. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in actual manufacturing.

[0022] As described in the background, there is band-to-band tunneling (BTBT) leakage in the overlapping area of the source-drain region and the channel of the GAA-FET, which leads to a sharp increase in the off-state leakage of the device.

[0023] To solve the above technical problems, the embodiment of the present application provides a stacked nanosheet GAA-FET device and a manufacturing method thereof. A stacked layer of first semiconductor layers and second semiconductor layers is formed on a substrate. The stacked layer is etched to form a fin, and a dummy gate and a first sidewall are formed on the fin. A portion of the first semiconductor layers at both ends is etched from outside to inside to form a second sidewall at both ends of the first semiconductor layers. The first semiconductor layers are removed to release a nanosheet channel, and the second semiconductor layers serve as the channel. The overlapping area of the second sidewall and the channel is laterally etched to form a gap. An interface oxide layer, a first high-k dielectric layer, and a second high-k dielectric layer are formed in the gap in an alternating manner until the gap is completely filled. The interface oxide layer and a third high-k dielectric layer are formed around the channel, and a metal gate is formed around the channel. In this way, compared with the prior art, the electric field generated by the metal gate can be conducted to the overlapping area of the source-drain region and the channel to cause band-to-band tunneling leakage. In the embodiment of the present application, the gap is completely filled by forming a plurality of layers of the first high-k dielectric layer and the second high-k dielectric layer in an alternating manner between the channel and the second sidewall to form a superlattice structure. The electric field can be conducted to the overlapping area of the source-drain region and the channel to the greatest extent, the electric field intensity of the overlapping area of the source-drain region and the channel is weakened, the electric field distribution of the overlapping area is changed, and the band-to-band tunneling leakage of the overlapping area of the source-drain region and the channel is inhibited, thereby avoiding the off-state leakage of the device and improving the performance of the device.

[0024] To facilitate understanding, the embodiment of the present application provides a stacked nanosheet GAA-FET device and a manufacturing method thereof, which will be described in detail below with reference to the accompanying drawings.

[0025] Reference Figure 1 As shown in the figure, the embodiment of the present application provides a flowchart of a manufacturing method of a stacked nanosheet GAA-FET device, which can include the following steps.

[0026] S101, a stacked layer of first semiconductor layers and second semiconductor layers is formed on a substrate.

[0027] In the embodiment of the present application, a substrate is provided, and the material of the substrate can be Si or SiGe. A bulk silicon Si substrate can be used and the substrate can be doped. Specifically, a high-doped well region is formed in the bulk silicon substrate by implanting impurities, diffusion, and annealing to achieve a desired well depth. For a P-type FET, the high-doped well region is an N well, and the implanted impurities are n-type impurity ions, such as phosphorus (P) ions. For an N-type FET, the high-doped well region is a p well, and the implanted impurities are p-type impurity ions, such as boron (B) ions.

[0028] In the embodiment of the present application, a stacked layer of first semiconductor layers 101 and second semiconductor layers 102 can be formed on a substrate. Specifically, referring to Figure 2As shown in FIG. 1, a structure diagram of a GAA-FET device provided in an embodiment of the present application is shown. A silicon dioxide (SiO2) layer on a surface of a bulk silicon substrate can be removed, and a first semiconductor layer 101 and a second semiconductor layer 102 can be epitaxially grown on the bulk silicon substrate 100.

[0029] The materials of the first semiconductor layer 101 and the second semiconductor layer 102 can be set according to actual requirements. The first semiconductor layer 101 can be a germanium-based film layer, which can include an epitaxial germanium layer, an epitaxial silicon germanium layer, or a combination thereof. The second semiconductor layer 102 can be an epitaxial silicon layer. For example, the first semiconductor layer / second semiconductor layer stack is SiGe / Si, and a SiGe / Si periodic superlattice is epitaxially grown. The epitaxial process can use reduced pressure epitaxy or molecular beam epitaxy.

[0030] In S102, the stack is etched to form a fin, and a dummy gate and a first sidewall are formed on the fin.

[0031] In the embodiment of the present application, the stack can be etched to form a fin, and a dummy gate and a first sidewall are formed on the fin. Specifically, refer to FIG. 2. Figure 3 The nanoscale first sidewall 104 device array can be formed by using a self-aligned spacer image transfer (SIT) process. The first sidewall 104 can be silicon nitride (SiN X ) or silicon oxide. The specific formation process is as follows: a layer of sacrificial layer 103 is covered on the stack, which can be polycrystalline silicon (PolySi, p-si) or amorphous silicon (a-si). Part of the sacrificial layer is etched away, the first sidewall 104 is deposited, which can be a silicon nitride (SiN x ) layer, and then anisotropic etching is used to etch away the remaining sacrificial layer, so that only the periodic silicon nitride first sidewall 104 on the stack is reserved. The first sidewall 104 can act as a hard mask (Hard Mask) in photolithography.

[0032] The epitaxially grown stack is etched into a plurality of periodically distributed fins by an etching process. The first sidewall 104 is used as a mask to perform etching, so as to form fins with a stack structure. The upper part of the fin is a conductive channel region formed by the stack, and the lower part is a substrate, forming a fin as shown in FIG. 3. Figure 4 The fin not only includes the stack structure 101 / 102, but also includes a single-crystal silicon structure 100 extending into the substrate. The etching process can be dry etching or wet etching, such as reactive ion etching (RIE). The fin will be used to form one or more horizontal nanosheets of n-type field effect transistors and / or p-type field effect transistors.

[0033] A shallow trench isolation (STI) region 105 can be formed between two adjacent fins to separate transistors on adjacent fins, such as... Figure 5 As shown. First, a dielectric insulating material is deposited, then planarized, for example using a CMP process, followed by selective etching back of the dielectric insulating material to expose a three-dimensional fin structure, forming a shallow trench isolation region 105. The upper surface of the shallow trench isolation region 105 is generally flush with the interface between the stacked layer structure in the fins and the substrate monocrystalline silicon, but may be higher or lower than this interface level. The shallow trench isolation region 105 can be formed of a suitable dielectric material, such as silicon dioxide (SiO2) or silicon nitride (SiN). x )wait.

[0034] refer to Figure 6 This is a schematic diagram of the overall structure of a stacked nanosheet GAA-FET device. Two directions are defined, and two dashed lines, XX and YY, are set. The XX line is along the fin direction and is the center line of the fin, while the YY line is perpendicular to the fin direction and is the center line of the fin. The following figures are cross-sectional schematic diagrams with the XX and YY lines.

[0035] Next, a false fence 106 and a third sidewall 107 can be formed on the fin, such as Figure 7 As shown, Figure 6 In the cross-sectional view along the YY direction, a false grid 106 is formed on the exposed fin in a direction perpendicular to the fin line (i.e., the YY direction). The false grid spans the stacked layers at the top of the fin. Figure 8 for Figure 6 Cross-sectional view in the XX direction. The material used for the dummy gate 106 can be polycrystalline silicon (p-si) or amorphous silicon (a-si).

[0036] Silicon nitride (SiN) is disposed on both sides of the dummy gate along the fin direction (i.e., the XX direction). x The thickness of the third side wall 107 on both sides can be the same, such as... Figure 9 As shown.

[0037] S103, etching a portion of the two ends of the first semiconductor layer from the outside in to form a second sidewall at both ends of the first semiconductor layer.

[0038] In this embodiment, the dummy gate 106 and the third sidewall 107 can be used as masks to perform source / drain etching on the fins using an etching process, as shown in the reference. Figure 10 As shown, only the stacked layers below the dummy grid 106 and the third sidewall 107 are retained.

[0039] Next, partial areas at both ends of the first semiconductor layer 101 are etched from the outside in, forming second sidewalls 108 at both ends of the first semiconductor layer 101. Specifically, as shown...Figure 11 As shown, a pull-back etching is performed to etch away part of the first semiconductor layer 101 from the outside to the center direction, so as to form the second sidewall 108 in the area of the etched first semiconductor layer 101.

[0040] Then, silicon nitride (SiN x ) is deposited on the periphery of the fin, and the second sidewall 108 is formed. Figure 12 As shown, then, the second sidewall 108 is etched to be flush with the second semiconductor layer 102 in the vertical direction, that is, the second sidewall 108 is formed at both ends of the first semiconductor layer 101, as shown in Figure 13 .

[0041] Epitaxial formation of source-drain regions and source-drain doping are performed, as shown in Figure 14 , for PMOS, the source-drain region material is boron (B) doped SiGe (SiGe:B), for NMOS, the source-drain region material is phosphorus (P) doped silicon (Si) (Si:P), and finally the source-drain region 110 is formed. The isolation layer 111 is deposited on the surface of the dummy gate 106 and the source-drain region 110 to prevent interconnection short circuit between the dummy gate layer 106 and the source-drain region 110 in the subsequent steps, and the isolation layer 111 is chemically mechanically polished to be planarized.

[0042] Then, as shown in Figure 15 , the dummy gate 106 formed by polycrystalline silicon (PolySi, p-si) or amorphous silicon (a-si) is etched or corroded by a selective etching or corrosion process, that is, the dummy gate 106 is removed.

[0043] S104, the first semiconductor layer is removed to release the nanosheet channel, and the second semiconductor layer serves as the channel.

[0044] In the embodiments of the present application, the first semiconductor layer 101 can be removed to release the nanosheet channel, and the second semiconductor layer 102 serves as the channel, as shown in Figure 16 . Specifically, the first semiconductor layer 101 in the stack layer is selectively etched to release the second semiconductor layer 102, that is, the nanosheet channel is released. The width of each nanosheet 202 can range from 1 to 100 nm, the thickness can range from 1 to 30 nm, and the spacing between each nanosheet 202 can range from 3 to 30 nm.

[0045] S105, the overlapping area of the second sidewall and the channel is etched laterally to form a gap.

[0046] In the embodiments of the present application, the overlapping area of the second sidewall 108 and the nanosheet (NS) channel 102 can be trimmed laterally to form a gap 115, as shown in Figure 17The superlattice structure is formed between the second sidewall 108 and the second semiconductor layer 102, so as to fill the gap between the second sidewall 108 and the second semiconductor layer 102, and to inhibit the electric field from conducting to the overlapping area of the source-drain region and the channel, and to inhibit the leakage current in the off state of the device.

[0047] S106, forming an interface oxide layer in the gap, and alternately stacking a first high-k dielectric layer and a second high-k dielectric layer until the gap is completely filled.

[0048] In the embodiments of the present application, an interface oxide layer (IL) can be deposited in the gap, which is not shown in the figure. Then, a first high-k dielectric layer (HK1) 201 and a second high-k dielectric layer (HK2) 202 are alternately stacked on the surface of the interface oxide layer. A plurality of groups of HK1 / HK2 can be deposited to form a superlattice structure until the gap is completely filled. For reference, see Figure 19 As shown in the figure, the superlattice structure includes two groups of HK1 / HK2.

[0049] The materials of the first high-k dielectric layer 201 and the second high-k dielectric layer 202 include at least one of the following materials: AlOx, MnOx, ZrOx, TiOx, MoOx, LaOx, MgOx, ScOx, YOx, and NdOx. The sum of the thicknesses of the alternately stacked first high-k dielectric layer and the second high-k dielectric layer can be greater than or equal to 0.1 nm and less than or equal to 5 nm.

[0050] In this way, by forming the alternately stacked plurality of first high-k dielectric layers and second high-k dielectric layers between the channel and the second sidewall to completely fill the gap and form a superlattice structure, the electric field can be maximally inhibited from conducting to the overlapping area of the source-drain region and the channel, the electric field intensity of the overlapping area of the source-drain region and the channel can be weakened, the electric field distribution of the overlapping area can be changed, and the band-to-band tunneling leakage current of the overlapping area of the source-drain region and the channel can be inhibited, thereby avoiding the leakage current in the off state of the device and improving the performance of the device.

[0051] In a possible implementation, when the interface oxide layer and the alternately stacked first high-k dielectric layer and second high-k dielectric layer are formed in the gap, the interface oxide layer and the alternately stacked first high-k dielectric layer and second high-k dielectric layer surrounding the channel can be formed, and the alternately stacked first high-k dielectric layer and second high-k dielectric layer between the channels can be removed, and the interface oxide layer and the alternately stacked first high-k dielectric layer and second high-k dielectric layer in the gap between the channel and the second sidewall are retained.

[0052] Specifically, refer to Figure 18As shown, during the deposition process, an interface oxide layer IL (not shown in the figure) surrounding the channel can be formed, and the first high-k dielectric layer 201 and the second high-k dielectric layer 202 are alternately stacked, and the groups of HK1 / HK2 between adjacent channels are not desired to exist, and then the groups of HK1 / HK2 between the channels can be selectively etched to avoid affecting the device performance, and the interface oxide layer and the groups of HK1 / HK2 in the gap are reserved, and the device structure after the groups of HK1 / HK2 between the channels are removed is shown in Figure 19

[0053] In the embodiments of the present application, the overlapping region of the third sidewall 107 and the channel can also be laterally etched to form a gap 115, and the groups of HK1 / HK2 are deposited in the gap, so as to further inhibit the electric field from conducting to the overlapping region of the source / drain region and the channel, weaken the electric field intensity of the overlapping region of the source / drain region and the channel, inhibit the band-to-band tunneling leakage of the overlapping region of the source / drain region and the channel, and avoid the off-state leakage of the device.

[0054] S107, forming an interface oxide layer and a third high-k dielectric layer around the channel, and forming a metal gate surrounding the channel.

[0055] In the embodiments of the present application, the interface oxide layer (not shown in the figure) and the third high-k dielectric layer (HK3) 203 can be formed around the channel, and the metal gate 204 surrounding the channel is formed, so as to form a high-k metal gate structure, and the device structure after the groups of HK1 / HK2 between the channels are removed is shown in Figure 20 As shown, the electric field generated by the metal gate can conduct to the overlapping region of the source / drain region and the channel to cause the band-to-band tunneling leakage, and through the superimposed structure of the groups of HK1 / HK2, the electric field can be maximally inhibited from conducting to the overlapping region of the source / drain region and the channel, the electric field intensity of the overlapping region of the source / drain region and the channel can be weakened, the electric field distribution of the overlapping region can be changed, so as to inhibit the band-to-band tunneling leakage of the overlapping region of the source / drain region and the channel, avoid the off-state leakage of the device, and improve the device performance.

[0056] It can be understood that the superimposed structure of the groups of HK1 / HK2 can be formed in the partial NMOS region and the PMOS region of the GAA-FET device at the same time to inhibit the band-to-band tunneling leakage of the overlapping region of the source / drain and the channel, or the superimposed structure of the groups of HK1 / HK2 can be formed only in the NMOS region or the PMOS region, or the superimposed structure of the groups of HK1 / HK2 can be formed in all the NMOS region and the PMOS region of the GAA-FET device.

[0057] The material of the third high-k dielectric layer includes at least one of the following materials: AlO x , MnO x , ZrO x , TiO x , MoO x , LaO​x MgO x ScO x 、YO x NdO x .

[0058] The metal gate 204 is used to form the gate and may include a multilayer structure such as a capping layer TiN, a barrier layer TaN, a work function layer WFL, and a fill layer W. Figure 20 The specific film structure is not shown. Specifically, a TiN capping layer and a TaN barrier layer can be deposited to form a TiN / TaN barrier-I. Then, PMOS WFLs are deposited in both the NMOS and PMOS regions. The PMOS WFLs can be made of TiN or TiSiN. Next, the PMOS WFLs are selectively etched away in all NMOS regions, leaving the PMOS WFLs in the PMOS regions. Then, depending on actual needs, barrier-I can be selectively etched in some NMOS regions to control the residual TiN thickness. Then, the PMOS WFLs are selectively etched in some PMOS regions to control the residual PMOS WFL thickness. Finally, NMOS WFLs are deposited in both NMOS and PMOS regions. The NMOS WFLs can be made of TiAlC. x Finally, TiN / TaN barrier-II and W conductive filler metal deposition are performed to form a high-k metal gate structure, and CMP planarization is performed.

[0059] Next, ILD dielectric deposition is performed on top, referencing... Figure 21 A dielectric CMP layer 116 is formed, and contact hole photolithography and etching are performed on the dielectric CMP layer 116 to deposit hole silicide 117, and contact electrodes are led out. Subsequently, multilayer back-end interconnection and passivation protection processes are completed to complete the fabrication of GAA-FET device.

[0060] The embodiment of the present application provides a stacked nanosheet GAA-FET device and a manufacturing method thereof. A stacked layer of first semiconductor layers and second semiconductor layers is formed on a substrate; the stacked layer is etched to form a fin, and a dummy gate and a first sidewall are formed on the fin; a partial region at both ends of the first semiconductor layer is etched from outside to inside, and a second sidewall is formed at both ends of the first semiconductor layer; the first semiconductor layer is removed to release a nanosheet channel, and the second semiconductor layer serves as the channel; an overlapping region of the second sidewall and the channel region is laterally etched to form a gap; an interface oxide layer, a first high-k dielectric layer and a second high-k dielectric layer which are alternately stacked are formed in the gap until the gap is completely filled, the interface oxide layer and a third high-k dielectric layer are formed around the channel, and a metal gate surrounding the channel is formed. In this way, compared with the prior art, the electric field generated by the metal gate can be conducted to the overlapping region of the source-drain region and the channel to cause band-to-band tunneling leakage. In the embodiment of the present application, the overlapping region of the source-drain region and the channel is completely filled by forming the first high-k dielectric layer and the second high-k dielectric layer which are alternately stacked between the channel and the second sidewall to form a superlattice structure, so that the electric field conducted to the overlapping region of the source-drain region and the channel can be maximally inhibited, the electric field intensity of the overlapping region of the source-drain region and the channel can be weakened, the electric field distribution of the overlapping region can be changed, and the band-to-band tunneling leakage of the overlapping region of the source-drain region and the channel can be inhibited, thereby avoiding the off-state leakage of the device and improving the performance of the device.

[0061] Based on the manufacturing method of the stacked nanosheet GAA-FET device, the embodiment of the present application further provides a stacked nanosheet GAA-FET device, which refers to Figure 21 as shown, comprising:

[0062] a substrate 100, a fin located on one side of the substrate; the fin comprises a plurality of second semiconductor layers 102, and the second semiconductor layers serve as channels;

[0063] a high-k metal gate structure comprising an interface oxide layer, a first high-k dielectric layer 201 and a second high-k dielectric layer 202 which are alternately stacked, a third high-k dielectric layer 203 and a metal gate 204; the metal gate 204 surrounds the second semiconductor layer 102, and the metal gate 204 has a second sidewall 108 at both ends; the interface oxide layer and the first high-k dielectric layer 201 and the second high-k dielectric layer 202 which are alternately stacked are located between the channel 102 and the second sidewall 108; and the interface oxide layer and the third high-k dielectric layer 203 are located at the periphery of the channel.

[0064] Specifically, the materials of the first high-k dielectric layer and the second high-k dielectric layer comprise at least one of the following materials: AlOx, MnOx, ZrOx, TiOx, MoOx, LaOx, MgOx, ScOx, YOx and NdOx.

[0065] Specifically, the third high-k dielectric layer is a Hf-based high-k material, and the material of the third high-k dielectric layer includes at least one of HfO2, HfSiOx, HfON, HfSiON, HfAlOx, and HfLaOx.

[0066] Specifically, the sum of the thicknesses of the first high-k dielectric layer and the second high-k dielectric layer is greater than or equal to 0.1 nm and less than or equal to 5 nm.

[0067] In the embodiments of the present application, the superlattice structure is formed by forming the alternately stacked first high-k dielectric layer and second high-k dielectric layer between the channel and the second sidewall to completely fill the gap, which can maximally inhibit the conduction of the electric field to the overlapping area of the source / drain region and the channel, weaken the electric field intensity of the overlapping area of the source / drain region and the channel, change the electric field distribution of the overlapping area, thereby inhibiting the band-to-band tunneling leakage of the overlapping area of the source / drain region and the channel, avoiding the off-state leakage of the device, and improving the performance of the device.

[0068] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts of each of the embodiments can be referred to each other. Each of the embodiments mainly describes the difference from other embodiments. Especially, the device embodiments are described more simply because they are basically similar to the method embodiments, and the related parts can be referred to the part of the method embodiments.

[0069] The above only describes the preferred embodiments of the present application. Although the present application has been disclosed as above with the preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solutions of the present application or modify equivalent embodiments with the above disclosed methods and technical contents without departing from the scope of the technical solutions of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the scope of the technical solutions of the present application are still within the scope of protection of the technical solutions of the present application.

Claims

1. A method for fabricating a stacked nanosheet GAA-FET device, characterized in that, include: A stacked layer of alternating first and second semiconductor layers is formed on a substrate; The stacked layers are etched to form fins, and a dummy gate and a first sidewall are formed on the fins; Etch a portion of the two ends of the first semiconductor layer from the outside in to form a second sidewall at both ends of the first semiconductor layer; Remove the first semiconductor layer to release the nanosheet channel, and use the second semiconductor layer as the channel; Laterally etch the overlapping area of ​​the second sidewall and the trench to form a gap; An interface oxide layer is formed in the void, and alternating layers of a first high-k dielectric layer and a second high-k dielectric layer are formed until the void is completely filled. An interface oxide layer and a third high-k dielectric layer are formed around the channel, and a metal gate is formed surrounding the channel.

2. The manufacturing method according to claim 1, characterized in that, The formation of an interface oxide layer in the voids, and alternating layers of a first high-k dielectric layer and a second high-k dielectric layer, includes: An interface oxide layer is formed surrounding the channel, and alternating layers of a first high-k dielectric layer and a second high-k dielectric layer are formed. Remove the alternating stacked first high-k dielectric layer and second high-k dielectric layer between the channels, retain the interface oxide layer in the gap between the channel and the second sidewall, and the alternating stacked first high-k dielectric layer and second high-k dielectric layer.

3. The manufacturing method according to claim 1, characterized in that, The materials of the first high-k dielectric layer and the second high-k dielectric layer include at least one of the following materials: AlOx, MnOx, ZrOx, TiOx, MoOx, LaOx, MgOx, ScOx, YOx, and NdOx.

4. The manufacturing method according to claim 1, characterized in that, The third high-k dielectric layer is an Hf-based high-k material, and the material of the third high-k dielectric layer includes at least one of the following materials: HfO2, HfSiOx, HfON, HfSiON, HfAlOx, and HfLaOx.

5. The manufacturing method according to any one of claims 1-4, characterized in that, The sum of the thicknesses of the alternatingly stacked first high-k dielectric layer and the second high-k dielectric layer is greater than or equal to 0.1 nm and less than or equal to 5 nm.

6. The manufacturing method according to any one of claims 1-4, characterized in that, The substrate is made of Si or SiGe.

7. A stacked nanosheet GAA-FET device, characterized in that, include: A substrate, and a fin located on one side of the substrate; the fin includes a plurality of second semiconductor layers, the second semiconductor layers serving as channels; A high-k metal gate structure includes an interface oxide layer, alternating layers of a first high-k dielectric layer and a second high-k dielectric layer, a third high-k dielectric layer, and a metal gate; the metal gate surrounds a second semiconductor layer, and the metal gate has second sidewalls at both ends; the interface oxide layer and the alternating layers of the first and second high-k dielectric layers are located between the channel and the second sidewalls; the interface oxide layer and the third high-k dielectric layer are located around the channel.

8. The stacked nanosheet GAA-FET device according to claim 7, characterized in that, The materials of the first high-k dielectric layer and the second high-k dielectric layer include at least one of the following materials: AlOx, MnOx, ZrOx, TiOx, MoOx, LaOx, MgOx, ScOx, YOx, and NdOx.

9. The stacked nanosheet GAA-FET device according to claim 7, characterized in that, The third high-k dielectric layer is an Hf-based high-k material, and the material of the third high-k dielectric layer includes at least one of the following materials: HfO2, HfSiOx, HfON, HfSiON, HfAlOx, and HfLaOx.

10. The stacked nanosheet GAA-FET device according to any one of claims 7-9, characterized in that, The sum of the thicknesses of the alternatingly stacked first high-k dielectric layer and the second high-k dielectric layer is greater than or equal to 0.1 nm and less than or equal to 5 nm.

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