Chip packaging structure and packaging method

Abstract

This invention provides a chip packaging structure and packaging method thereof. The chip packaging structure includes a silicon substrate, a passivation layer on the front side of the silicon substrate, a dielectric layer on the front side of the passivation layer, and a molding compound layer covering at least the sidewalls of the silicon substrate. Chip electrodes are embedded on the front side of the silicon substrate. The passivation layer and the dielectric layer have vias for exposing the chip electrodes to the outside. Metal bumps are connected to the front side of the chip electrodes. One end of the molding compound layer near the front side of the silicon substrate is bonded to the passivation layer. Compared with the existing method where the molding compound layer is bonded to the dielectric layer, this method increases the bonding force between the molding compound layer and the chip, making the molding compound layer less prone to detachment due to force. At the same time, during the packaging process, the passivation layer fixes the chips together, preventing chip displacement during the molding process, improving the reliability and yield of the final product.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure and packaging method thereof. Background Technology

[0002] Traditional four- or five-sided encapsulated chip packaging methods typically involve first creating dicing grooves on the wafer using dry etching or similar techniques. These dicing grooves divide the wafer into several independent chips. The passivation layer within the dicing grooves is completely etched, meaning the bottom of the dicing grooves extends to the dielectric layer. At this point, the chips cannot be properly secured, leading to significant displacement of the chips when subsequent molding processes are used to form the encapsulation layer covering the sidewalls and back of the chips. This results in difficulties in subsequent alignment processes, or even complete failure to align the chips.

[0003] Meanwhile, the molded layer formed is bonded to the dielectric layer at one end near the front side of the wafer. However, the molded layer is made of epoxy resin molding compound, and the dielectric layer is made of polyimide or phenolic resin photoresist (low temperature or high temperature). It is known that there are gaps between the cross-linked polymer chains in the dielectric layer, which makes the photoresist exposed to the air prone to absorbing water. Moreover, the water molecules that enter the photoresist are not easy to evaporate, affecting the bonding force with the molded layer. In addition, some photoresists have poor bonding force with the molded layer due to the special functional groups on their surface, resulting in poor wettability. The poor bonding force between the photoresist and the molded layer makes it easy for the molded layer and the dielectric layer to delaminate, affecting the reliability of the packaging and easily producing defective products.

[0004] In view of this, it is necessary to provide a new chip packaging structure and packaging method to solve the above problems. Summary of the Invention

[0005] The purpose of this invention is to provide a chip packaging structure and packaging method thereof, which can improve the reliability of the chip packaging structure.

[0006] To achieve the above-mentioned objectives, the present invention adopts the following technical solution: a chip packaging structure, comprising a silicon substrate, a passivation layer on the front side of the silicon substrate, a dielectric layer on the front side of the passivation layer, and a molding compound layer covering at least the sidewalls of the silicon substrate. Chip electrodes are embedded on the front side of the silicon substrate. The passivation layer and the dielectric layer are provided with vias for exposing the chip electrodes to the outside. Metal bumps are connected to the front side of the chip electrodes. One end of the molding compound layer near the front side of the silicon substrate is bonded to the passivation layer.

[0007] As a further improvement of the present invention, the passivation layer has a groove on its periphery, and one end of the molding layer near the front side of the silicon substrate is located in the groove.

[0008] As a further improvement of the present invention, the thickness of the passivation layer forming the groove is at least 25% of the thickness of the passivation layer that mates with the silicon substrate.

[0009] As a further improvement of the present invention, the chip packaging structure further includes a conductive reinforcement layer disposed on the back side of the silicon substrate.

[0010] As a further improvement of the present invention, the molding layer covers the sidewalls and back side of the silicon substrate.

[0011] As a further improvement of the present invention, the chip packaging structure further includes a first back protective layer located on the back side of the molding layer.

[0012] As a further improvement of the present invention, the molding compound covers the sidewall of the silicon substrate; the chip packaging structure further includes a second back protective layer, which covers the back side of the silicon substrate and the side of the molding compound close to the back side of the silicon substrate.

[0013] To achieve the above-mentioned objectives, the present invention also provides a chip packaging structure packaging method, comprising the following steps:

[0014] S1: Take a wafer, the front side of which has a chip electrode and a passivation layer, and the passivation layer has a first via for exposing the chip electrode to the outside;

[0015] S2: A dielectric layer covering the wafer is formed on the front side of the wafer, the dielectric layer having a second via that is disposed through the wafer and connected to the first via;

[0016] S3: Form metal bumps on the front side of the chip electrode;

[0017] S4: Bond a support carrier covering the dielectric layer to the front side of the dielectric layer;

[0018] S5: Etch from the back side of the wafer to the front side of the wafer to the passivation layer to form a dicing groove and a silicon substrate separated by the dicing groove;

[0019] S6: A molding compound is formed on a wafer having dicing grooves, the molding compound covering at least the sidewalls of the silicon substrate;

[0020] S7: Remove the supporting carrier;

[0021] S8: Cut along the dicing groove to form an independent chip packaging structure.

[0022] As a further improvement of the present invention, in the process of "etching from the back side of the wafer to the front side of the wafer to the passivation layer to form a dicing groove", the depth of etching to the passivation layer is no greater than 75% of the thickness of the passivation layer.

[0023] As a further improved technical solution of the present invention, the following step is also included between steps S4 and S5: performing a thinning process on the back side of the wafer to thin the wafer to a preset thickness.

[0024] As a further improvement of the present invention, the following step is also included between steps S4 and S5: forming a conductive reinforcement layer on the back side of the wafer.

[0025] As a further improved technical solution of the present invention, in step S6, the molding compound encapsulates the exposed sidewall of the silicon substrate. Between steps S6 and S7, the packaging method of the chip packaging structure further includes the following step: forming a second back protective layer on the back side of the wafer and on the side of the molding compound corresponding to the back side of the wafer; or, in step S6, the molding compound encapsulates the exposed sidewall and back side of the silicon substrate. Between steps S6 and S7, the packaging method of the chip packaging structure further includes the following step: forming a first back protective layer on the back side of the molding compound.

[0026] The beneficial effects of this invention are as follows: In the chip packaging structure of this invention, the molding layer is configured to be bonded to the passivation layer. Compared with the existing molding layer being bonded to the dielectric layer, this increases the bonding force between the molding layer and the chip, plays a stress buffering role, prevents stress extension, and makes the molding layer less likely to fall off due to force. At the same time, during the packaging process, the passivation layer fixes the chips together, preventing chip displacement during the molding process, improving the reliability of the final product, and improving the yield of the final product. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the chip packaging structure in the first embodiment of the present invention.

[0028] Figure 2 This is a schematic diagram of the chip packaging structure in the second embodiment of the present invention.

[0029] Figure 3 This is a schematic diagram of the chip packaging structure in the third embodiment of the present invention.

[0030] Figure 4 This is a schematic diagram of the chip packaging structure in the fourth embodiment of the present invention.

[0031] Figures 5a-5i This is a step diagram of the packaging method of the chip packaging structure in the first embodiment of the present invention. Detailed Implementation

[0032] The present invention will now be described in detail with reference to the embodiments shown in the accompanying drawings. Please refer to the accompanying drawings for further details. Figure 1 Figure 5 illustrates a preferred embodiment of the present invention. However, it should be noted that these embodiments are not intended to limit the present invention. Any equivalent modifications or substitutions in function, method, or structure made by those skilled in the art based on these embodiments are within the scope of protection of the present invention.

[0033] Please refer to Figure 1 and combined Figure 5a As shown, this is a chip packaging structure 10 in the first embodiment of the present invention. The chip packaging structure 10 includes a chip 1. The chip 1 includes a silicon substrate 11 and a passivation layer 12 located on the front side of the silicon substrate 11. A chip electrode 13 is embedded on the front side of the silicon substrate 11. A first through hole 121 is provided on the passivation layer 12 to expose the chip electrode 13 to the outside.

[0034] The chip packaging structure 10 also includes a dielectric layer 2 located on the front side of the passivation layer 12 and a molding compound 3 covering at least the sidewalls of the silicon substrate 11.

[0035] Combination Figure 5b As shown, a second through hole 21 is provided on the dielectric layer 2 at a position corresponding to the first through hole 121. The first through hole 121 and the second through hole 21 are connected to each other so that the front side of the chip electrode 13 is exposed to the outside.

[0036] The front side of the chip electrode 13 is connected to a metal bump 4. The metal bump 4 extends to the outside of the dielectric layer 2 through the first through hole 121 and the second through hole 21, so as to realize the connection and fixation of the chip packaging structure 10 through the metal bump 4.

[0037] Furthermore, the end of the molding compound 3 closest to the front side of the silicon substrate 11 is bonded to the passivation layer 12. The material of the molding compound 3 is epoxy resin molding compound. On the one hand, the passivation layer 12 is formed of relatively dense inorganic materials silicon oxide / silicon nitride, and the contact area between the passivation layer 12 and the outside world is small, resulting in poor moisture absorption. On the other hand, silicon oxide / silicon nitride has good mechanical properties, high temperature resistance, and good oxidation resistance. Therefore, the molding compound 3 and the passivation layer 12 have good bonding force. Compared with the existing molding compound 3 bonded to the dielectric layer 2, this increases the bonding force between the molding compound 3 and the chip 1, playing a stress buffering role and preventing stress extension. The molding compound 3 is not easy to fall off due to force, improving the reliability of the final product and improving the yield of the final product.

[0038] Meanwhile, it is understood that during the process of forming the chip packaging structure 10, before molding, the passivation layer 12 fixes the chips 1 together, which can prevent the chips 1 from shifting during the molding process, improve the reliability of the final product, and improve the yield of the final product.

[0039] In one specific implementation method, combined with Figure 5f As shown, the passivation layer 12 has a groove 122 on its periphery. One end of the molding compound 3 near the front side of the silicon substrate 11 is located within the groove 122, which can enhance the bonding area between the molding compound 3 and the passivation layer 12, further enhance the bonding force between the molding compound 3 and the chip 1, and improve the reliability of the final product. Of course, this is not a limitation.

[0040] Specifically, the passivation layer 12 includes a middle portion 123 corresponding to the silicon substrate 11 and an edge portion 124 located at the periphery of the middle portion 123. The groove 122 is formed on the edge portion 124, that is, the molding layer 3 is bonded to the edge portion 124.

[0041] It is understood that in embodiments where the passivation layer 12 has a groove 122 around its periphery that mates with the molding compound 3, the thickness of the passivation layer 12 forming the groove 122 is less than the thickness of the passivation layer 12 mates with the silicon substrate 11. That is, the thickness of the edge portion 124 is less than the thickness of the middle portion 123. During the formation of the chip package structure 10, the bottom of the dicing groove extends into the passivation layer 12. In embodiments where the passivation layer 12 does not have the groove 122, the thickness of the edge portion 124 and the middle portion 123 of the passivation layer 12 are the same.

[0042] Furthermore, the thickness of the passivation layer 12 forming the groove 122 is at least 25% of the thickness of the passivation layer 12 that mates with the silicon substrate 11, increasing the bonding area between the molding layer 3 and the passivation layer 12, further enhancing the bonding force between the molding layer 3 and the chip 1, and improving the reliability of the final product; at the same time, before molding, the passivation layer 12 fixes the chips 1 together, which can prevent the chips 1 from shifting during the molding process.

[0043] Furthermore, in this embodiment, the molding layer 3 covers the sidewalls and back of the silicon substrate 11, so that all five sides of the silicon substrate 11 are physically and electrically protected, preventing the sidewalls of the chip 1 from contacting the metal bumps 4 on other chips 1 and causing failure, avoiding external interference and improving its reliability; at the same time, it provides insulation protection for the sidewalls, making them less prone to leakage or short circuit, and improving the mounting yield of the chip packaging structure 10.

[0044] In one specific embodiment, the molding layer 3 is an integral structure, but this is not the only possible embodiment.

[0045] Further, please refer to Figure 2 As shown, this is a chip packaging structure 10a in the second embodiment of the present invention. The difference between this embodiment and the first embodiment is that, in addition to the molding layer 3 covering the sidewalls and back side of the silicon substrate 11, the chip packaging structure 10a also includes a first back protective layer 5 located on the back side of the molding layer 3, so as to further improve the reliability of the final product.

[0046] The second embodiment of the present invention is the same as the first embodiment except for the differences mentioned above, and will not be repeated here.

[0047] Please refer to Figure 3 As shown, this is a chip packaging structure 10b in the third embodiment of the present invention. The difference between this embodiment and the first embodiment is that the chip packaging structure 10b further includes a conductive reinforcement layer 6 disposed on the back side of the silicon substrate 11, so as to make the electric field of the chip packaging structure 10b uniform throughout.

[0048] Specifically, the conductive reinforcement layer can completely cover the back side of the silicon substrate 11, making the electric field of the chip packaging structure 10b sufficiently uniform. Of course, the conductive reinforcement layer can also partially cover the back side of the silicon substrate 11, as long as the requirements are met, thus saving material costs.

[0049] It is understood that, in this embodiment, the molding layer 3 covering the sidewalls and back surface of the silicon substrate 11 means that the molding layer 3 covers the sidewalls of the silicon substrate 11 and the back surface of the conductive reinforcement layer.

[0050] Furthermore, it can be understood that, depending on process requirements, the chip packaging structure 10b in this embodiment may also include a back protective layer 5 disposed on the back side of the molding layer 3.

[0051] The third embodiment of the present invention is the same as the first embodiment except for the differences mentioned above, and will not be repeated here.

[0052] Please refer to Figure 4 As shown, this is a chip packaging structure 10c in the fourth embodiment of the present invention. The difference between this embodiment and the first embodiment is that the molding layer 3 only covers the sidewall of the silicon substrate 11; the chip packaging structure 10c also includes a second back protective layer 5c, which covers the back of the silicon substrate 11 and the side of the molding layer 3 near the back of the silicon substrate 11.

[0053] The fourth embodiment of the present invention is the same as the first embodiment except for the differences mentioned above, and will not be repeated here.

[0054] Further, please refer to Figure 5a – Figure 5i As shown, the present invention also provides a packaging method for a chip packaging structure, wherein the chip packaging structure is the chip packaging structure 10 in the first embodiment described above.

[0055] The packaging method for the chip packaging structure includes the following steps:

[0056] S1: As Figure 5a As shown, a wafer is taken, and the front side of the wafer has a chip electrode 13 and a passivation layer 12. The passivation layer 12 has a first via 121 for exposing the chip electrode 13 to the outside.

[0057] S2: As Figure 5b As shown, a dielectric layer 2 covering the wafer is formed on the front side of the wafer, and the dielectric layer 2 has a second via 21 that is disposed through the wafer and communicates with the first via 121.

[0058] S3: As Figure 5c As shown, a metal bump 4 is formed on the front side of the chip electrode 13;

[0059] S4: As Figure 5d As shown, a support carrier 7 is bonded to the front side of the dielectric layer 2, covering the dielectric layer 2;

[0060] S5: As Figure 5f As shown, the wafer is etched from the back side to the front side to the passivation layer 12 to form a dicing groove 8 and a silicon substrate 11 separated by the dicing groove 8.

[0061] S6: As Figure 5g As shown, a molding compound 3 is formed on a wafer having a dicing groove 8, the molding compound 3 covering at least the sidewalls of the silicon substrate 11;

[0062] S7: As Figure 5h As shown, the supporting carrier 7 is removed;

[0063] S8: As Figure 5i As shown, the chip is cut along the dicing groove 8 to form an independent chip packaging structure 10.

[0064] Specifically, in step S2, a dielectric layer 2 having the second via 21 can be formed on the front side of the wafer by photolithography.

[0065] Step S3 specifically involves: depositing a metal seed layer on the surface of the wafer using sputtering or chemical plating; then sequentially using photolithography and electroplating processes to form metal pillars and a solder layer at the top of the metal pillars on the front side of the chip electrode 13; removing the remaining photoresist; and etching away the invalid metal seed layer outside the metal pillars to form the metal bump 4. That is, the metal bump 4 includes the metal seed layer, the metal pillars, and the solder layer.

[0066] Step S4 specifically involves connecting the support carrier 7 to the front side of the dielectric layer 2 using temporary bonding adhesive or temporary bonding film.

[0067] Specifically, the temporary bonding film can be a temperature-sensitive thermal release film or a UV release film.

[0068] The support carrier 7 can be a silicon-based reinforcing plate or a glass-based carrier. By temporarily bonding the support carrier 7 to the dielectric layer 2, the risk of fragmentation during the packaging process can be reduced.

[0069] Step S5 specifically involves: forming a dicing groove 8 by dry etching along the dicing path, the bottom of the dicing groove 8 extending to the passivation layer 12, and the dicing groove 8 dividing the wafer into multiple independent silicon substrates 11.

[0070] In step S5, the dicing groove 8 is formed by dry etching. The depth of the dicing groove 8 is controllable and can be controlled by controlling the dry etching time.

[0071] In this invention, the dicing groove 8 does not penetrate the wafer in the depth direction, but only extends to the passivation layer 12. Thus, the passivation layer 12 fixes the chips 1 together and can prevent the chips 1 from shifting during the molding process in step S6.

[0072] In one specific embodiment, in step S5, the depth of etching to the passivation layer 12 from the back side of the wafer to the front side of the wafer to form the dicing groove 8 is no greater than 75% of the thickness of the passivation layer 12. On the one hand, this increases the bonding area between the subsequent molding layer 3 and the passivation layer 12, further enhancing the bonding force between the molding layer 3 and the chip 1, and improving the reliability of the final product; on the other hand, the passivation layer 12 fixes the chips 1 together, preventing the chips 1 from shifting during the molding process.

[0073] Furthermore, such as Figure 5e As shown, between steps S4 and S5, the following steps are also included: performing a thinning process on the back side of the wafer to thin the wafer to a preset thickness.

[0074] Specifically, the back side of the wafer is thinned to a preset thickness by physical grinding or wet etching.

[0075] Step S6 specifically involves forming the encapsulation layer 3 in a vacuum environment by injection molding of encapsulation material or by applying an encapsulation film using a film-applying process. The encapsulation layer 3 covers at least the sidewalls of the silicon substrate 11.

[0076] In this embodiment, the molding layer 3 in step S6 molds the exposed sidewalls and back of the silicon substrate 11, so that all five sides of the silicon substrate 11 are physically and electrically protected, preventing the sidewalls of the chip 1 from contacting the metal bumps 4 on other chips 1 and causing failure, avoiding external interference and improving its reliability; at the same time, it provides insulation protection for the sidewalls, making them less prone to leakage or short circuit, and improving the chip 1 mounting yield.

[0077] Furthermore, when the chip packaging structure is the chip packaging structure 10a in the second embodiment described above, between steps S6 and S7, the packaging method of the chip packaging structure further includes the following step: forming a first back protective layer 5 on the back side of the molding compound 3.

[0078] Specifically, a first back protective layer 5 is formed on the back of the plastic sealant 3 through a printing process or a lamination process.

[0079] Furthermore, when the chip packaging structure is the chip packaging structure 10b in the third embodiment described above, between steps S4 and S5, the packaging method of the chip packaging structure 10 further includes the following step: forming a conductive reinforcement layer 6 on the back side of the wafer to make the electric field of the chip packaging structure 10b uniform throughout.

[0080] It is understood that between steps S4 and S5, a thinning process is also included on the back side of the wafer. After the thinning process is performed on the back side of the wafer, a conductive reinforcement layer 6 is formed on the back side of the wafer.

[0081] Specifically, the conductive reinforcement layer 6 can be achieved by first forming a metal seed layer on the back side of the wafer by vapor deposition, and then vapor depositing a conductive metal layer on the metal seed layer, or by printing a polymer conductive material or conductive nanomaterial on the back side of the wafer.

[0082] Specifically, the conductive reinforcement layer 6 can completely cover the back side of the silicon substrate 11, making the electric field of the chip packaging structure 10b sufficiently uniform. Of course, the conductive reinforcement layer 6 can also partially cover the back side of the silicon substrate 11, as long as the requirements are met, thus saving material costs.

[0083] It is understood that in the embodiment where the conductive reinforcing layer 6 is provided on the back side of the silicon substrate 11, the molding layer 3 molding the back side of the silicon substrate 11 refers to the molding layer 3 molding the back side of the conductive reinforcing layer 6.

[0084] Furthermore, when the chip packaging structure is the chip packaging structure 10c in the fourth embodiment above, that is, when the molding compound 3 in step S6 only covers the sidewall of the silicon substrate 11, between steps S6 and S7, the packaging method of the chip packaging structure 10 further includes the following step: forming a second back protective layer 5c on the back side of the wafer and on the side of the molding compound 3 corresponding to the back side of the wafer.

[0085] Specifically, the second back protective layer 5c is formed on the back side of the wafer and on the side of the molding compound 3 corresponding to the back side of the wafer by means of a printing process or a film application process.

[0086] Compared with the prior art, in the chip packaging structure 10 of the present invention, the molding layer 3 is configured to be bonded to the passivation layer 12. Compared with the existing molding layer 3 being bonded to the dielectric layer 2, this increases the bonding force between the molding layer 3 and the chip 1, plays a role in stress buffering, prevents stress extension, and makes the molding layer 3 less likely to fall off due to force. At the same time, before the molding process, the passivation layer 12 fixes the chips 1 together, which can prevent the chips 1 from shifting during the molding process, improve the reliability of the final product, and improve the yield of the final product.

[0087] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0088] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A chip packaging structure, comprising a silicon substrate, a passivation layer on the front side of the silicon substrate, a dielectric layer on the front side of the passivation layer, and a molding compound layer covering at least the sidewalls of the silicon substrate, wherein chip electrodes are embedded on the front side of the silicon substrate, and vias are provided on the passivation layer and the dielectric layer for exposing the chip electrodes to the outside, and metal bumps are connected to the front side of the chip electrodes; characterized in that: The molding layer is bonded to the passivation layer at one end near the front side of the silicon substrate; the passivation layer has a groove at its periphery, and the molding layer at one end near the front side of the silicon substrate is located in the groove.

2. The chip packaging structure as described in claim 1, characterized in that: The thickness of the passivation layer forming the groove is at least 25% of the thickness of the passivation layer that mates with the silicon substrate.

3. The chip packaging structure as described in claim 1, characterized in that: The chip packaging structure also includes a conductive reinforcement layer disposed on the back side of the silicon substrate.

4. The chip packaging structure as described in claim 1 or 3, characterized in that: The molding compound covers the sidewalls and back side of the silicon substrate.

5. The chip packaging structure as described in claim 4, characterized in that: The chip packaging structure also includes a first back protective layer located on the back side of the molding layer.

6. The chip packaging structure as described in claim 1, characterized in that: The molding compound covers the sidewalls of the silicon substrate; the chip packaging structure further includes a second back cover layer, which covers the back of the silicon substrate and the side of the molding compound layer near the back of the silicon substrate.

7. A packaging method for a chip packaging structure, characterized in that: The packaging method for the chip packaging structure includes the following steps: S1: Take a wafer, the front side of which has a chip electrode and a passivation layer, and the passivation layer has a first via for exposing the chip electrode to the outside; S2: A dielectric layer covering the wafer is formed on the front side of the wafer, the dielectric layer having a second via that is disposed through the wafer and connected to the first via; S3: Form metal bumps on the front side of the chip electrode; S4: Bond a support carrier covering the dielectric layer to the front side of the dielectric layer; S5: Etch from the back side of the wafer to the front side of the wafer to the passivation layer to form a dicing groove and a silicon substrate separated by the dicing groove; S6: A molding compound is formed on a wafer having dicing grooves, the molding compound covering at least the sidewalls of the silicon substrate; S7: Remove the supporting carrier; S8: Cut along the dicing groove to form an independent chip packaging structure.

8. The packaging method for the chip packaging structure as described in claim 7, characterized in that: In the phrase "etching from the back side of the wafer to the front side of the wafer to the passivation layer to form a dicing groove", the depth of etching to the passivation layer is no greater than 75% of the thickness of the passivation layer.

9. The packaging method for the chip packaging structure as described in claim 7, characterized in that: Between steps S4 and S5, the following steps are also included: performing a thinning process on the back side of the wafer to thin the wafer to a preset thickness.

10. The packaging method for the chip packaging structure as described in claim 7, characterized in that: Between steps S4 and S5, the following step is also included: forming a conductive reinforcement layer on the back side of the wafer.

11. The packaging method for the chip packaging structure as described in claim 7, characterized in that: In step S6, the molding compound encapsulates the exposed sidewalls of the silicon substrate. Between steps S6 and S7, the packaging method of the chip packaging structure further includes the following step: forming a second back protective layer on the back side of the wafer and on the side of the molding compound corresponding to the back side of the wafer; or, in step S6, the molding compound encapsulates the exposed sidewalls and back side of the silicon substrate. Between steps S6 and S7, the packaging method of the chip packaging structure further includes the following step: forming a first back protective layer on the back side of the molding compound.

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