A method for improving the performance of a CMOS image sensor

Abstract

The application provides a method for improving the performance of a CMOS image sensor, which comprises the following steps: forming an N well and a P well on a P substrate; forming a first N+ region and a second N+ region in the P well near the upper surface of the P substrate; forming a transfer tube gate between the N well and the P well and a reset tube gate between the first N+ region and the second N+ region on the upper surface of the P substrate; forming an amorphous layer on the side of the N well shallow region near the transfer tube gate; forming a Pin barrier layer on the lower surface of the amorphous layer; and forming a self-aligned silicide barrier layer, which covers the upper surface of the amorphous layer and continuously extends to the surface of the transfer tube gate, the upper surface of the first N+ region, the surface of the reset tube and the upper surface of the second N+ region. The method can reduce the plasma-induced damage caused by subsequent processes, reduce the generation of dark current and white pixels, improve the full well capacity of the photodiode and reduce the dark current generated by the defects at the interface between Si and silicon oxide.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving the performance of CMOS image sensors. Background Technology

[0002] Traditional processes form a self-aligned silicide barrier layer after PIN IMP, but the plasma introduced in subsequent processes can cause plasma-induced damage (PID). This causes electrons generated by the image sensor in dark fields to be collected by photodiodes, resulting in dark current and white pixels that affect image quality.

[0003] Therefore, a new method is needed to improve the performance of image sensors. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for improving the performance of CMOS image sensors, which solves the problem in the prior art that image sensors generate dark currents and white pixels in dark fields, thereby affecting image quality.

[0005] To achieve the above and other related objectives, the present invention provides a method for improving the performance of a CMOS image sensor, comprising at least:

[0006] Step 1: Provide a P-type substrate, and form an N-well and a P-well located on one side of the N-well on the P-type substrate; form a first and a second N+ region in the P-well near the upper surface of the P-type substrate, respectively; form a gate oxide layer and a polysilicon layer on the upper surface of the P-type substrate, and then etch the gate oxide layer and the polysilicon layer to form a transfer transistor gate located between the N-well and the P-well and a reset transistor gate located between the first and second N+ regions, respectively; the transfer transistor gate includes a first gate oxide layer structure on the P-type substrate and a transfer transistor polysilicon structure on the first gate oxide layer structure; the reset transistor gate includes a second gate oxide layer structure on the P-type substrate and a reset transistor polysilicon structure on the second gate oxide layer structure;

[0007] Step 2: Form an amorphous layer in the shallow region of the N-well near the gate of the transfer transistor;

[0008] Step 3: Form a pin barrier layer on the lower surface of the amorphous layer;

[0009] Step 4: Form a self-aligned silicide barrier layer, which covers the upper surface of the amorphous layer and extends continuously to the gate surface of the transfer transistor, the upper surface of the first N+ region, the surface of the reset transistor, and the upper surface of the second N+ region.

[0010] Preferably, the method for forming the amorphous layer in step two is as follows: ion implantation is performed on the side of the N-well shallow region near the gate of the transfer transistor to form the amorphous layer, thereby blocking the ion tunneling path.

[0011] Preferably, in step two, the ions implanted in the shallow region of the N-well near the gate of the transfer tube are any one of Si, C, and Ge.

[0012] Preferably, in step two, the energy of Si ions implanted into one side of the transfer tube gate in the shallow region of the N-well is 9 KeV, and the dose is 5e4 / cm2.

[0013] Preferably, the method for forming the Pin barrier layer in step three is as follows: performing ion implantation to penetrate the amorphous layer and forming the Pin barrier layer on the lower surface of the amorphous layer.

[0014] Preferably, in step three, boron ion implantation is performed to penetrate the amorphous layer.

[0015] Preferably, the self-aligned silicide barrier layer in step four is silicon oxide.

[0016] As described above, the method for improving the performance of a CMOS image sensor according to the present invention has the following beneficial effects: the present invention amorphizes the surface layer, blocks the ion tunneling path, and can effectively reduce plasma-induced damage caused by subsequent processes, reduce dark current and white pixel generation; it can effectively reduce the depth of the pin barrier layer implanted into the silicon surface, increase the depth of the photodiode, and improve the full-well capacity of the photodiode to a certain extent; the pin barrier layer completely depletes the N-well of the photodiode and provides physical isolation of Si, which can further reduce the dark current caused by defects at the Si-silicon oxide interface. Attached Figure Description

[0017] Figures 1 to 4 The diagram shows the structure formed by each step in the method for improving the performance of a CMOS image sensor according to the present invention.

[0018] Figure 5 The diagram shown is a flowchart of the method for improving the performance of a CMOS image sensor according to the present invention. Detailed Implementation

[0019] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0020] Please see Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0021] This invention provides a method for improving the performance of a CMOS image sensor, such as... Figure 5 As shown, Figure 5 The flowchart shown is a method for improving the performance of a CMOS image sensor according to the present invention, which includes at least the following steps:

[0022] Step 1: Provide a P-type substrate, and form an N-well and a P-well located on one side of the N-well on the P-type substrate; form a first and a second N+ region in the P-well near the upper surface of the P-type substrate, respectively; form a gate oxide layer and a polysilicon layer on the upper surface of the P-type substrate, and then etch the gate oxide layer and the polysilicon layer to form a transfer transistor gate located between the N-well and the P-well and a reset transistor gate located between the first and second N+ regions, respectively; the transfer transistor gate includes a first gate oxide layer structure on the P-type substrate and a transfer transistor polysilicon structure on the first gate oxide layer structure; the reset transistor gate includes a second gate oxide layer structure on the P-type substrate and a reset transistor polysilicon structure on the second gate oxide layer structure;

[0023] like Figure 1 As shown, in step one, an N-well and a P-well located on one side of the N-well are formed on the P-type substrate (P-sub); a first N+ region A and a second N+ region B are formed in the P-well near the upper surface of the P-type substrate (P-sub); a gate oxide layer and a polysilicon layer are formed on the upper surface of the P-type substrate (P-sub), and then the gate oxide layer and the polysilicon layer are etched to form a transfer transistor (Tx) gate located between the N-well and the P-well and a reset transistor (RST) gate located between the first and second N+ regions; the transfer transistor gate includes a first gate oxide layer structure 01 located on the P-type substrate (P-sub) and a transfer transistor polysilicon structure 03 located on the first gate oxide layer structure 01; the reset transistor gate includes a second gate oxide layer structure 02 located on the P-type substrate (P-sub) and a reset transistor polysilicon structure 04 located on the second gate oxide layer structure 02.

[0024] Step 2: Form an amorphous layer in the shallow region of the N-well near the gate of the transfer transistor;

[0025] In a further step of this invention, the method for forming the amorphous layer in step two of this embodiment is as follows: ion implantation is performed on the side of the N-well shallow region near the gate of the transfer transistor to form the amorphous layer, thereby blocking the ion tunneling path.

[0026] In a further step of this invention, in step two of this embodiment, the ions implanted in the shallow region of the N-well near the gate of the transfer tube are any one of Si, C, and Ge.

[0027] In a further step of this invention, in step two of this embodiment, the energy of injecting Si ions into the shallow region of the N-well near the gate of the transfer tube is 9 KeV, and the dose is 5e4 / cm2.

[0028] like Figure 2 As shown, in step two, an amorphous layer 05 is formed in the shallow region of the N-well near the gate of the transfer transistor. In this embodiment, the method for forming the amorphous layer 05 in step two is as follows: ion implantation is performed in the shallow region of the N-well near the gate of the transfer transistor to form the amorphous layer 05, thereby blocking the ion tunneling path. In this invention, the ions implanted in the shallow region of the N-well near the gate of the transfer transistor can be any one of Si, C, or Ge. In this embodiment, the energy of Si ions implanted in the shallow region of the N-well near the gate of the transfer transistor is 9 keV, and the dose is 5e⁴ / cm².

[0029] Step 3: Form a pin barrier layer on the lower surface of the amorphous layer;

[0030] In a further embodiment of the present invention, the method for forming the Pin barrier layer in step three is as follows: performing ion implantation to penetrate the amorphous layer, and forming the Pin barrier layer on the lower surface of the amorphous layer.

[0031] In a further step of this invention, boron ion implantation is performed in step three of this embodiment to penetrate the amorphous layer.

[0032] like Figure 3 As shown, step three involves forming a pin barrier layer 06 on the lower surface of the amorphous layer 05. In this embodiment, the method for forming the pin barrier layer 06 in step three is as follows: ion implantation (PIN IMP) is performed to penetrate the amorphous layer 05, and the pin barrier layer 06 is formed on the lower surface of the amorphous layer 05. Boron ion implantation is performed to penetrate the amorphous layer 05.

[0033] Step 4: Form a self-aligned silicide barrier layer, which covers the upper surface of the amorphous layer and extends continuously to the gate surface of the transfer transistor, the upper surface of the first N+ region, the surface of the reset transistor, and the upper surface of the second N+ region.

[0034] Furthermore, in this embodiment, the self-aligned silicide barrier layer in step four is silicon oxide.

[0035] like Figure 4 As shown, in step four, a self-aligned silicide barrier layer 07 is formed. This self-aligned silicide barrier layer 07 covers the upper surface of the amorphous layer 05 and extends continuously to the gate surface of the transfer transistor, the upper surface of the first N+ region A, the surface of the reset transistor, and the upper surface of the second N+ region B. In this embodiment, the self-aligned silicide barrier layer 07 in step four is silicon oxide.

[0036] The image sensor formation method of the present invention reduces the generation of dark current and white pixels, thereby improving the performance of the image sensor.

[0037] In summary, the etching method of this invention amorphizes the surface layer, blocking the ion tunneling path and effectively reducing plasma-induced damage (PID) caused by subsequent processes, thus reducing dark current and white pixel generation. It can also effectively reduce the depth of the pin blocking layer implanted into the silicon surface, increasing the depth of the photodiode and improving the full-well capacity (FWC) of the photodiode to a certain extent. Furthermore, the pin blocking layer completely depletes the N-well region of the photodiode and provides physical isolation of Si, further reducing dark current caused by defects at the Si-SiO2 interface. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0038] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of improving the performance of a CMOS image sensor, characterized by, At least comprising: Step one, providing a P-type substrate, forming an N-well and a P-well on one side of the N-well on the P-type substrate; forming a first and a second N+ region in the P-well near the upper surface of the P-type substrate respectively; forming a gate oxide layer and a polysilicon layer on the upper surface of the P-type substrate, and then etching the gate oxide layer and the polysilicon layer to form a transfer tube gate between the N-well and the P-well and a reset tube gate between the first and second N+ regions respectively; the transfer tube gate comprises a first gate oxide layer structure on the P-type substrate and a transfer tube polysilicon structure on the first gate oxide layer structure; the reset tube gate comprises a second gate oxide layer structure on the P-type substrate and a reset tube polysilicon structure on the second gate oxide layer structure; Step two, forming an amorphous layer on the side of the N-well shallow region near the transfer tube gate; Step three, forming a Pin barrier layer on the lower surface of the amorphous layer; Step four, forming a self-aligned silicide barrier layer, which covers the upper surface of the amorphous layer and continuously extends to the surface of the transfer tube gate, the upper surface of the first N+ region, the surface of the reset tube, and the upper surface of the second N+ region.

2. The method of improving CMOS image sensor performance according to claim 1, wherein: The method for forming the amorphous layer in step two is: ion implantation is performed on the side of the N-well shallow region near the transfer tube gate to form the amorphous layer to block the ion tunneling path.

3. The method of improving CMOS image sensor performance of claim 2, wherein: The ion implanted on the side of the N-well shallow region near the transfer tube gate in step two is any one of Si, C, and Ge.

4. The method of improving CMOS image sensor performance of claim 3, wherein: The energy of the Si ion implanted on the side of the N-well shallow region near the transfer tube gate in step two is 9 Kev, and the dose is 5e4 / cm2.

5. The method of improving CMOS image sensor performance of claim 1, wherein: The method for forming the Pin barrier layer in step three is: ion implantation is performed to penetrate the amorphous layer to form the Pin barrier layer on the lower surface of the amorphous layer.

6. The method of improving CMOS image sensor performance of claim 5, wherein: Boron ion implantation is performed to penetrate the amorphous layer in step three.

7. The method of improving CMOS image sensor performance of claim 1, wherein: The self-aligned silicide barrier layer in step four is silicon oxide.

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