Hybrid conduction mechanism fin-gate field-effect transistor devices

Abstract

The present invention provides a hybrid conduction mechanism fin-gate field-effect transistor device, comprising a fin-gate field-effect transistor, a second source region, and a second drain region. The fin-gate field-effect transistor comprises a substrate, a fin-shaped channel region, a first source region, and a first drain region. The height of the second source region is not less than the height of the substrate between the first source region and the first drain region. The first source region and the first drain region are doped with first ions. The second source region is formed between the substrate and the first source region, and the second drain region is formed between the substrate and the first drain region. The second drain region and the second source region are doped with first ions and second ions, respectively. This solution solves the problem of bottom current leakage in fin-gate field-effect transistors. By adding the second source region and the second drain region, it is equivalent to connecting a tunneling field-effect transistor device structure in parallel at the bottom of the fin-gate field-effect transistor. This solution can achieve hybrid conduction of fin-channel diffusion drift current and bottom-channel band-to-band tunneling current, thereby achieving better ultra-steep switching characteristics.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a fin-type gate field effect transistor device with a hybrid conduction mechanism. Background Art

[0002] Since the birth of integrated circuits, microelectronic integration technology has been developing in accordance with "Moore's Law". With the reduction in the size of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs), the switching speed, density, functionality and cost of microprocessors have been significantly improved. However, device power consumption remains one of the important challenges in the process of device miniaturization. The main technical approach to reducing device power consumption is to enhance the device gate control capability. As a pioneer of three-dimensional integrated devices, the fin-gate field effect transistor FinFET has a three-sided gate structure that has better gate control capability than traditional planar gate devices. It is the mainstream device structure of advanced logic devices. However, conventional FinFET devices have significant sub-Fin leakage channels under the fin channel, which leads to increased static power consumption of FinFET devices. How to suppress the off-state sub-Fin leakage current has become one of the key challenges in the optimization of fin devices.

[0003] Another effective way to reduce device power consumption is to lower the power supply voltage VDD. The subthreshold swing of traditional MOSFET devices is limited by the kT / q thermodynamic distribution and has a theoretical limit of 60mV / dec at room temperature. This makes it impossible to continuously reduce the power supply voltage in ULSI chips based on traditional MOSFET devices. Tunneling field-effect transistors (TFETs), due to their excellent subthreshold characteristics, low off-state leakage current, and low switching power consumption, are highly promising devices for future ultra-low power integrated circuit applications. Because their conduction mechanism is quantum mechanical band-to-band tunneling, they are not subject to thermodynamic temperature constraints, and their subthreshold swing can exceed the 60mV / dec limit at room temperature.

[0004] Therefore, developing a fin-gate field-effect transistor device that can effectively suppress bottom leakage current and significantly improve the subthreshold characteristics of the device has become a technical focus that needs to be urgently addressed by those skilled in the art. Summary of the Invention

[0005] The present invention provides a fin-type gate field effect transistor device with a hybrid conduction mechanism to solve the problem of bottom current leakage of the fin-type gate field effect transistor.

[0006] According to a first aspect of the present invention, there is provided a hybrid conduction mechanism fin-gate field effect transistor device, comprising:

[0007] A fin-gate field-effect transistor, the fin-gate field-effect transistor comprising a substrate, a fin-shaped channel region, a first source region, and a first drain region; the first source region and the first drain region are arranged above the substrate along a first direction; the fin-shaped channel region is formed on the substrate between the first source region and the first drain region; wherein the first source region and the first drain region are doped with first ions; wherein the first direction represents a channel direction of the fin-gate field-effect transistor;

[0008] a second source region and a second drain region, wherein the second source region is formed between the substrate and the first source region, and the second drain region is formed between the substrate and the first drain region;

[0009] The heights of the second source region and the second drain region are not lower than the height of the substrate between the first source region and the first drain region;

[0010] The second drain region is doped with the first ions, the second source region is doped with second ions, and the type of the first ions is different from the type of the second ions.

[0011] Optionally, the thickness of the second source region and / or the second drain region is 5 nm-50 nm.

[0012] Optionally, the first ion is a P-type ion or an N-type ion.

[0013] Optionally, the second ion is a P-type ion or an N-type ion.

[0014] Optionally, the ion concentration of the second source region and / or the second drain region is 1E16 cm-3-1E22 cm-3.

[0015] Optionally, the material of the second source region and the material of the second drain region are binary or ternary compounds of II-VI, III-V or IV-IV groups.

[0016] Optionally, the material of the second source region and the material of the second drain region are Si, SiGe or Ge.

[0017] Optionally, the fin-gate field-effect transistor further includes:

[0018] a gate dielectric layer and a control gate, wherein the gate dielectric layer wraps a portion of the surface of the channel layer and wraps the substrate between the first source region and the first drain region; the control gate wraps the surface of the gate dielectric layer;

[0019] Sidewall spacers formed on both sides of the gate dielectric layer and the control gate along the first direction;

[0020] a source metal layer, a gate metal layer, and a drain metal layer; the source metal layer and the drain metal layer are respectively formed on the surfaces of the first source region and the first drain region, and respectively fully surround the first source region and the second source region and the first drain region and the second drain region; the gate metal layer is formed on top of the control gate;

[0021] an interlayer dielectric layer, covering the source metal layer, the gate metal layer, the drain metal layer and the surface of the sidewalls;

[0022] The metal contact layer penetrates the interlayer dielectric layer and is respectively connected to the source metal layer, the gate metal layer and the drain metal layer.

[0023] According to a second aspect of the present invention, a method for manufacturing a hybrid conduction mechanism fin-gate field effect transistor device is provided, which is used to manufacture the hybrid conduction mechanism fin-gate field effect transistor device according to any one of the first aspects of the present invention, comprising:

[0024] The fin-gate field-effect transistor, the second source region, and the second drain region are formed; wherein the fin-gate field-effect transistor includes the substrate, the fin-shaped channel region, the first source region, and the first drain region; the first source region and the first drain region are arranged above the substrate along a first direction; the fin-shaped channel region is formed on the substrate between the first source region and the first drain region; the second source region is formed between the substrate and the first source region, and the second drain region is formed between the substrate and the first drain region.

[0025] The first source region, the first drain region and the second drain region are doped with the first ions; the second source region is doped with second ions, and the type of the first ions is different from the type of the second ions.

[0026] Optionally, forming the fin-gate field-effect transistor, the second source region, and the second drain region specifically includes:

[0027] providing the substrate;

[0028] forming a dummy gate structure and the sidewall spacer; the dummy gate structure spans the substrate; the sidewall spacer is closely attached to both sidewalls of the dummy gate structure along the first direction;

[0029] Etching the substrate on both sides of the sidewall spacer along the first direction to form the fin-shaped channel region, and over-etching the substrate on both sides of the sidewall spacer along the first direction to form a first cavity and a second cavity; wherein the dummy gate structure and the sidewall spacer wrap the fin-shaped channel region; the first cavity and the second cavity are arranged in sequence along the first direction;

[0030] forming the second source region and the second drain region; the second source region is formed in the first cavity, and the second drain region is formed in the second cavity;

[0031] forming the first source region and the first drain region; wherein the first source region and the first drain region are formed on top of the second source region and the second drain region respectively;

[0032] removing the dummy gate structure;

[0033] The gate dielectric layer, the control gate, the source metal layer, the gate metal layer, the drain metal layer, the interlayer dielectric layer and the metal contact layer are formed.

[0034] Optionally, forming the second source region and the second drain region specifically includes:

[0035] forming a patterned first mask layer; the patterned first mask layer covers the second cavity, the dummy gate structure, and the surface of the sidewall;

[0036] Filling the first cavity with the material of the second source region to form the second source region, and removing the patterned first mask layer;

[0037] forming a patterned second mask layer; the patterned second mask layer covers the second source region, the dummy gate structure, and the surface of the sidewall spacer;

[0038] The material for filling the second drain region is deposited in the second cavity to form the second drain region, and the patterned second mask layer is removed.

[0039] According to a third aspect of the present invention, an electronic device is provided, comprising the hybrid conduction mechanism fin-gate field effect transistor device according to any one of the first aspects of the present invention.

[0040] According to a fourth aspect of the present invention, a method for manufacturing an electronic device is provided, comprising the method for manufacturing a hybrid conduction mechanism fin-gate field effect transistor device according to any one of the second aspects of the present invention.

[0041] The present invention provides a hybrid conduction mechanism fin-gate field-effect transistor device. Compared with the existing fin-gate field-effect transistor, a second source region and a second drain region are respectively arranged between the first source region and the substrate, and between the first drain region and the substrate. The second drain region is doped with a first ion, and the second source region is doped with a second ion, and the type of the first ion is different from the type of the second ion. In the off state, a reverse-biased PIN channel is formed at the bottom. This structure can significantly suppress the leakage of the bottom current of the traditional fin-gate field-effect transistor, thereby enhancing the current switching ratio of the device.

[0042] Furthermore, the present invention provides a hybrid conduction mechanism fin-gate field-effect transistor device. Due to the addition of a second source region and a second drain region, it is equivalent to a tunneling field-effect transistor device structure connected in parallel at the bottom of the fin-gate field-effect transistor device. Therefore, when the device is in the on state, it can achieve a mixed conduction of the fin-channel fin-channel diffusion drift current and the bottom channel quantum mechanical band-to-band tunneling current, thereby achieving an ultra-steep switching characteristic of less than 60mV / dec for the entire device. At the same time, when in the on state, the parallel fin-gate field-effect transistor device above is turned on, providing a large current for the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 1 is a front view schematic structural diagram of a hybrid conduction mechanism fin-gate field effect transistor device provided by one embodiment of the present invention;

[0045] Figure 2 This is a flow chart of a method for manufacturing a hybrid conduction mechanism fin-gate field effect transistor device provided by one embodiment of the present invention;

[0046] Figure 3 1 is a schematic side view of a hybrid conduction mechanism fin-gate field effect transistor device provided by one embodiment of the present invention;

[0047] Figure 4 Schematic diagram of the device structure at different process stages of a method for manufacturing a fin-type gate field effect transistor device with a hybrid conduction mechanism according to an embodiment of the present invention Figure 1 ;

[0048] Figure 5 Schematic diagram of the device structure at different process stages of a method for manufacturing a fin-type gate field effect transistor device with a hybrid conduction mechanism according to an embodiment of the present invention Figure 2 ;

[0049] Description of reference numerals:

[0050] 101-substrate;

[0051] 102-first source region;

[0052] 103-first drain region;

[0053] 104-second source area;

[0054] 105-second drain region;

[0055] 106-fin-type channel region;

[0056] 107-gate dielectric layer;

[0057] 108-control grid;

[0058] 109-drain metal layer;

[0059] 110 - gate metal layer;

[0060] 111-source metal layer;

[0061] 112-interlayer dielectric layer;

[0062] 113-metal contact layer;

[0063] 114-side wall;

[0064] 115-dummy gate structure;

[0065] 116-photoresist;

[0066] 117-STI structure. DETAILED DESCRIPTION

[0067] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0068] The terms "first," "second," "third," "fourth," and the like (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0069] Conventional FinFET devices have significant sub-fin leakage channels beneath the fin channel, increasing static power consumption. Suppressing off-state sub-fin leakage current is a key challenge in fin device optimization. The subthreshold swing of conventional MOSFET devices is limited by the kT / q thermodynamic distribution, with a theoretical limit of 60mV / dec at room temperature. This makes it impossible to continuously reduce the supply voltage in ULSI chips based on conventional MOSFETs.

[0070] In view of this, the inventors of this application added a source region and a drain region at the bottom to form a structure similar to a tunneling transistor at the bottom of the fin-gate field-effect transistor; the hybrid conduction mechanism fin-gate field-effect transistor combining the tunneling transistor and the fin-gate field-effect transistor can effectively suppress the bottom leakage current and significantly improve the subthreshold characteristics of the device at the same time.

[0071] The following specific embodiments are used to describe the technical solution of the present invention in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0072] Please refer to Figure 1-Figure 5 According to an embodiment of the present invention, a hybrid conduction mechanism fin-gate field effect transistor device is provided, comprising:

[0073] A fin-gate field-effect transistor, the fin-gate field-effect transistor comprising a substrate 101, a fin-shaped channel region 106, a first source region 102, and a first drain region 103; the first source region 102 and the first drain region 103 are arranged above the substrate 101 along a first direction; the fin-shaped channel region 106 is formed on the substrate 101 between the first source region 102 and the first drain region 103; wherein the first source region 102 and the first drain region 103 are doped with first ions; wherein the first direction represents a channel direction of the fin-gate field-effect transistor;

[0074] In a specific embodiment, the substrate 101 is selected from bulk silicon (Si), silicon-on-insulator (SOI), Ge, GOI, SiGe, or other semiconductor materials.

[0075] a second source region 104 and a second drain region 105, wherein the second source region 104 is formed between the substrate 101 and the first source region 102, and the second drain region 105 is formed between the substrate 101 and the first drain region 103; and the heights of the second source region 104 and the second drain region 105 are not lower than the height of the substrate 101 between the first source region 102 and the first drain region 103;

[0076] The second drain region 105 is doped with the first ion, the second source region 104 is doped with the second ion, and the type of the first ion is different from the type of the second ion. The front view structural diagram of the hybrid conduction mechanism fin-gate field effect transistor device is as shown in FIG. Figure 1 As shown, the side view structure diagram of the hybrid conduction mechanism fin-gate field effect transistor device is as follows Figure 3 shown.

[0077] The present invention provides a hybrid conduction mechanism fin-gate field-effect transistor device. Compared with the existing fin-gate field-effect transistor, a second source region and a second drain region are respectively arranged between the first source region and the substrate, and between the first drain region and the substrate. The second drain region is doped with a first ion, and the second source region is doped with a second ion, and the type of the first ion is different from the type of the second ion. In the off state, a reverse-biased PIN channel is formed at the bottom. This structure can significantly suppress the leakage of the bottom current of the traditional fin-gate field-effect transistor, thereby enhancing the current switching ratio of the device.

[0078] Furthermore, the present invention provides a hybrid conduction mechanism fin-gate field-effect transistor device. Due to the addition of a second source region and a second drain region, it is equivalent to a tunneling field-effect transistor (TFET) device structure connected in parallel at the bottom of the fin-gate field-effect transistor device. Therefore, when the device is in the on state, it can achieve a mixed conduction of the fin-channel diffusion drift current and the bottom channel quantum mechanical band-to-band tunneling current, thereby obtaining an ultra-steep switching characteristic of less than 60mV / dec for the entire device. At the same time, when in the on state, the parallel fin-gate field-effect transistor device above is turned on, providing a large current for the device.

[0079] In one embodiment, the first ion is a P-type ion or an N-type ion.

[0080] In one embodiment, the second ion is a P-type ion or an N-type ion.

[0081] Specifically, the P-type ions are: hydrides, fluorides or chlorides of boron, specifically one of the following materials or a combination thereof: B2H6, B4H10, B6H10, B10H14, B18H22, BF3 or BCl3; the N-type ions are: hydrides and fluorides of phosphorus and arsenic, specifically one of the following materials or a combination thereof: phosphine, arsine, phosphorus pentafluoride, phosphorus trifluoride, arsenic pentafluoride or arsenic trifluoride.

[0082] The fin-shaped channel region 106 and the bottom Fin region (i.e., the substrate 101 between the second source region 104 and the second drain region 105) are undoped or lightly doped i regions; the range of light doping in the bottom Fin region is: 1E13cm -3 -1E15cm -3 ;

[0083] For an N-type device, the first source region 102 is N-type doped, and its doping concentration is about 1E18cm-3-1E22cm-3, and the first drain region 103 is N-type doped, and its doping concentration is about

[0084] 1E18cm-3-1E22cm-3, the second source region 104 is P-type doped, and its doping concentration is about 1E18cm-3-1E22cm-3, and the second drain region 105 is N-type doped, and its doping concentration is about 1E16cm-3-1E21cm-3;

[0085] For P-type devices, the first source region 102 is P-type doped with a doping concentration of approximately 1E18cm-3-1E22cm-3, the first drain region 103 is P-type doped with a doping concentration of approximately 1E18cm-3-1E20cm-3, the second source region 104 is N-type doped with a doping concentration of approximately 1E18cm-3-1E22cm-3, and the second drain region 105 is P-type doped with a doping concentration of approximately 1E16cm-3-1E21cm-3.

[0086] In the hybrid conduction mechanism fin-gate field effect transistor device, the thickness of the second source region and the second drain region and their doping concentration are important parameters for device design. If the thickness of the second source region or the second drain region is too thin, the bottom tunneling field effect transistor will have little effect on the total current, and the improvement of the subthreshold swing characteristics of the device will be limited; if the thickness of the second source region or the second drain region is too thick, it will increase the difficulty of the process and lead to a decrease in the consistency and reliability of the device. The doping concentration of the second source region cannot be too low. If the doping concentration is too low, the resistance of the second source region will increase. At the same time, the lower doping reduces the tunneling probability of the bottom tunneling transistor, making band-to-band tunneling more difficult to occur and the current decreases. The doping concentration of the second drain region also needs to be controlled within a certain range. If the doping concentration is too low, the resistance of the bottom drain region will increase and the current will decrease; if the doping concentration is too high, the channel bipolar effect of the TFET device will be more significant.

[0087] Therefore: In a preferred embodiment, the thickness of the second source region 104 and / or the second drain region 105 is 5 nm to 50 nm. In an embodiment, the doping ion concentration in the second source region 104 and / or the second drain region 105 is 1E16 cm-3 to 1E22 cm-3.

[0088] In a preferred embodiment, the material of the second source region and the material of the second drain region are binary or ternary compounds of II-VI, III-V or IV-IV groups.

[0089] In one embodiment, the material of the second source region and the material of the second drain region are Si, SiGe or Ge.

[0090] In one embodiment, the fin-gate field-effect transistor further includes:

[0091] a gate dielectric layer 107 and a control gate 108 , wherein the gate dielectric layer 107 wraps a portion of the surface of the channel layer and the substrate 101 between the first source region 102 and the first drain region 103 ; and the control gate 108 wraps the surface of the gate dielectric layer 107 ;

[0092] Sidewall spacers 114 are formed on both sides of the gate dielectric layer 107 and the control gate 108 along the first direction;

[0093] Source metal layer 111, gate metal layer 110 and drain metal layer 109;

[0094] In one embodiment, the source metal layer 111 and the drain metal layer 109 are respectively formed on the surfaces of the first source region 102 and the first drain region 103 , and respectively fully wrap the first source region 102 and the first drain region 103 ; the gate metal layer 110 is formed on the top of the control gate 108 ;

[0095] Since the second source and drain regions are led out with additional parasitic resistance, which is not conducive to the steep subthreshold swing characteristics of the device, in a preferred embodiment, the source metal layer 111 and the drain metal layer 109 are respectively formed on the surfaces of the first source region 102 and the first drain region 103, and fully wrap the first source region 102 and the second source region 104 and the first drain region 103 and the second drain region 105; the gate metal layer 110 is formed on the top of the control gate 108;

[0096] an interlayer dielectric layer 112 covering the source metal layer 111 , the gate metal layer 110 , the drain metal layer 109 and the surface of the sidewall spacer 114 ;

[0097] The metal contact layer 113 penetrates the interlayer dielectric layer 112 and is respectively connected to the source metal layer 111 , the gate metal layer 110 , and the drain metal layer 109 .

[0098] According to other embodiments of the present invention, a method for manufacturing a hybrid conduction mechanism fin-gate field effect transistor device is provided, which is used to manufacture the hybrid conduction mechanism fin-gate field effect transistor device according to any of the aforementioned embodiments of the present invention, comprising:

[0099] The fin-gate field-effect transistor, the second source region 104, and the second drain region 105 are formed; wherein the fin-gate field-effect transistor includes the substrate 101, the fin-shaped channel region 106, the first source region 102, and the first drain region 103; the first source region 102 and the first drain region 103 are arranged above the substrate 101 along a first direction; the fin-shaped channel region 106 is formed on the substrate 101 between the first source region 102 and the first drain region 103; the second source region 104 is formed between the substrate 101 and the first source region 102, and the second drain region 105 is formed between the substrate 101 and the first drain region 103.

[0100] The first source region 102 , the first drain region 103 and the second drain region 105 are doped with the first ions; the second source region 104 is doped with second ions, and the type of the first ions is different from the type of the second ions.

[0101] In one embodiment, the fin-gate field effect transistor, the second source region 104 and the second drain region 105 are formed, and a flow chart of a method for manufacturing a hybrid conduction mechanism fin-gate field effect transistor device is shown as follows: Figure 2 As shown, specifically including:

[0102] S11: providing the substrate 101; and performing STI isolation patterning by photolithography to form an STI structure 117; wherein the depth of the photolithography is about 5nm-50nm, and the material of the STI structure is SiO2;

[0103] S12: forming a dummy gate structure 115 and the sidewall spacer 114; the dummy gate structure 115 spans the substrate 101; the sidewall spacer 114 is closely attached to the two sidewalls of the dummy gate structure 115 along the first direction; specifically, the dummy gate structure 115 is made of polysilicon; the dummy gate structure 115 is formed by atomic layer deposition, chemical vapor deposition, or physical vapor deposition; the thickness of the dummy gate structure 115 is 50 nm;

[0104] S13: Etching the substrate 101 on both sides of the spacer 114 along the first direction to form the fin-shaped channel region 106, controlling the length of the device channel to be approximately 50 nm-100 nm, and over-etching the substrate 101 on both sides of the spacer 114 along the first direction to form a first cavity and a second cavity; wherein the dummy gate structure 115 and the spacer 114 wrap the fin-shaped channel region 106; the first cavity and the second cavity are arranged in sequence along the first direction;

[0105] S14: forming the second source region 104 and the second drain region 105; the second source region 104 is formed in the first cavity, and the second drain region 105 is formed in the second cavity;

[0106] In one embodiment, step S14, forming the second source region 104 and the second drain region 105, specifically includes:

[0107] S141: forming a patterned first mask layer; the patterned first mask layer covers the second cavity, the dummy gate structure 115 , and the surface of the spacer 114 ;

[0108] S142: Filling the first cavity with the material of the second source region 104 to form the second source region 104, and removing the patterned first mask layer, such as Figure 4 As shown;

[0109] In one embodiment, the second source region 104 is doped with B ions at a concentration of about 1E21 cm -3 ;

[0110] S143: forming a patterned second mask layer; the patterned second mask layer covers the surface of the second source region 104 , the dummy gate structure 115 , and the spacer 114 ;

[0111] S144: depositing a material for filling the second drain region 105 in the second cavity to form the second drain region 105, and removing the second patterned mask layer. The second patterned mask layer and the first patterned mask layer are photoresist 116, such as Figure 5 As shown;

[0112] In one embodiment, the materials of the second source region 104 and the second drain region 105 are: SiGe and Si:C;

[0113] The second source region 104 and the second drain region 105 of the device are grown using SiGe / Si:C epitaxy, which is beneficial to increasing the band-to-band tunneling probability of the channel material.

[0114] In one embodiment, the second drain region 105 is doped with As ions at a concentration of about 1E18 cm -3 .

[0115] S15: forming the first source region 102 and the first drain region 103; the first source region 102 and the first drain region 103 are formed on top of the second source region 104 and the second drain region 105 respectively;

[0116] In one embodiment, the second source region 104 or the second drain region 105 is formed by an in-situ epitaxial method, an atomic layer deposition method, or a chemical vapor deposition method.

[0117] In one embodiment, the method of highly doping the first source region 102 or the second source region 104 is selected from one of the following methods: in-situ doping, ion implantation, or solid-state source doping.

[0118] In one embodiment, the materials of the first source region 102 and the first drain region are SiGe and Si:C.

[0119] Among them, since the first source region 102 and the first drain region 103 of the device are grown using SiGe / Si:C epitaxy, stress will be further applied to the gate nanowire / nanosheet channel, which is beneficial to increasing the carrier mobility of the channel material. In one specific embodiment, the first source region 102 and the first drain region 103 are in-situ doped with As ions at a concentration of approximately 1E21cm -3 ;

[0120] After doping ions, the process also includes: a rapid high-temperature annealing to activate the injected impurities (1050°C, 10s)

[0121] S16: removing the dummy gate structure 115;

[0122] S17: Form the gate dielectric layer 107, the control gate 108, the source metal layer 111, the gate metal layer 110, the drain metal layer 109, the interlayer dielectric layer 112 and the metal contact layer 113. Specifically, the material of the gate dielectric layer is: SiO2, Si3N4 or a high-K gate dielectric material; the material of the control gate 108 is selected from doped polysilicon, metal cobalt, nickel and other metals or metal silicides. The growth method of the material of the gate dielectric layer is: conventional thermal oxidation, nitrogen-doped thermal oxidation, atomic layer deposition or chemical vapor deposition. In a specific embodiment, the material of the gate dielectric layer is HfO2 with a thickness of 1 to 5 nm; the gate material is a TiN layer with a thickness of 50 to 200 nm;

[0123] Secondly, according to an embodiment of the present invention, an electronic device is also provided, comprising the hybrid conduction mechanism fin-gate field effect transistor device according to any one of the aforementioned embodiments of the present invention.

[0124] In addition, according to an embodiment of the present invention, a method for manufacturing an electronic device is provided, including the method for manufacturing the hybrid conduction mechanism fin-gate field effect transistor device according to any one of the aforementioned embodiments of the present invention.

[0125] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A hybrid conduction mechanism fin-gate field effect transistor device, characterized in that: include: A fin-gate field-effect transistor, the fin-gate field-effect transistor comprising a substrate, a fin-shaped channel region, a first source region, a first drain region, a gate dielectric layer, and a control gate; the first source region and the first drain region are arranged above the substrate along a first direction; the fin-shaped channel region is formed on the substrate between the first source region and the first drain region; wherein the first source region and the first drain region are doped with first ions, the gate dielectric layer wraps a portion of the surface of the channel layer and wraps the substrate between the first source region and the first drain region; the control gate wraps the surface of the gate dielectric layer; wherein the first direction represents the channel direction of the fin-gate field-effect transistor; a second source region and a second drain region, the second source region is formed between the substrate and the first source region, and the second drain region is formed between the substrate and the first drain region; the height of the second source region and the second drain region is not lower than the height of the substrate between the first source region and the first drain region; The second drain region is doped with the first ions, the second source region is doped with second ions, and the type of the first ions is different from the type of the second ions.

2. The hybrid conduction mechanism fin-gate field effect transistor device according to claim 1, characterized in that: The thickness of the second source region and / or the second drain region is 5 nm-50 nm.

3. The hybrid conduction mechanism fin-gate field effect transistor device according to claim 1, wherein: The first ions are P-type ions or N-type ions.

4. The hybrid conduction mechanism fin-gate field effect transistor device according to claim 1, wherein: The second ion is a P-type ion or an N-type ion.

5. The hybrid conduction mechanism fin-gate field effect transistor device according to claim 1, wherein: The ion concentration of the second source region and / or the second drain region is 1E16 cm-3-1E22 cm-3.

6. The hybrid conduction mechanism fin-gate field effect transistor device according to claim 1, wherein: The material of the second source region and the material of the second drain region are binary or ternary compounds of II-VI, III-V or IV-IV groups.

7. The hybrid conduction mechanism fin-gate field effect transistor device according to claim 6, characterized in that: The material of the second source region and the material of the second drain region are Si, SiGe or Ge.

8. The hybrid conduction mechanism fin-gate field effect transistor device according to claim 1, wherein: The fin-gate field-effect transistor further comprises: Sidewall spacers formed on both sides of the gate dielectric layer and the control gate along the first direction; a source metal layer, a gate metal layer, and a drain metal layer; the source metal layer and the drain metal layer are respectively formed on the surfaces of the first source region and the first drain region, and respectively fully surround the first source region and the second source region and the first drain region and the second drain region; the gate metal layer is formed on top of the control gate; an interlayer dielectric layer, covering the source metal layer, the gate metal layer, the drain metal layer and the surface of the sidewalls; The metal contact layer penetrates the interlayer dielectric layer and is respectively connected to the source metal layer, the gate metal layer and the drain metal layer.

9. A method for manufacturing a hybrid conduction mechanism fin-gate field effect transistor device, for manufacturing the hybrid conduction mechanism fin-gate field effect transistor device according to any one of claims 1 to 8, characterized in that: include: The fin-type gate field-effect transistor, the second source region and the second drain region are formed; wherein the fin-type gate field-effect transistor includes the substrate, the fin-type channel region, the first source region, the first drain region, a gate dielectric layer and a control gate; the first source region and the first drain region are arranged above the substrate along a first direction; the fin-type channel region is formed on the substrate between the first source region and the first drain region; the second source region is formed between the substrate and the first source region, and the second drain region is formed between the substrate and the first drain region, the gate dielectric layer wraps a portion of the surface of the channel layer and wraps the substrate between the first source region and the first drain region; the control gate wraps the surface of the gate dielectric layer, The first source region, the first drain region and the second drain region are doped with the first ions; the second source region is doped with second ions, and the type of the first ions is different from the type of the second ions.

10. The method for manufacturing a hybrid conduction mechanism fin-gate field effect transistor device according to claim 9, wherein: Forming the fin-gate field-effect transistor, the second source region, and the second drain region specifically includes: providing the substrate; forming a dummy gate structure and a sidewall spacer; wherein the dummy gate structure spans the substrate; and the sidewall spacer is closely attached to two sidewalls of the dummy gate structure along the first direction; Etching the substrate on both sides of the sidewall spacer along the first direction to form the fin-shaped channel region, and over-etching the substrate on both sides of the sidewall spacer along the first direction to form a first cavity and a second cavity; wherein the dummy gate structure and the sidewall spacer wrap the fin-shaped channel region; the first cavity and the second cavity are arranged in sequence along the first direction; forming the second source region and the second drain region; the second source region is formed in the first cavity, and the second drain region is formed in the second cavity; forming the first source region and the first drain region; wherein the first source region and the first drain region are formed on top of the second source region and the second drain region respectively; removing the dummy gate structure; The gate dielectric layer, the control gate, the source metal layer, the gate metal layer, the drain metal layer, the interlayer dielectric layer and the metal contact layer are formed.

11. The method for manufacturing a hybrid conduction mechanism fin-gate field effect transistor device according to claim 10, wherein: Forming the second source region and the second drain region specifically includes: forming a patterned first mask layer; the patterned first mask layer covers the second cavity, the dummy gate structure, and the surface of the sidewall; Filling the first cavity with the material of the second source region to form the second source region, and removing the patterned first mask layer; forming a patterned second mask layer; the patterned second mask layer covers the second source region, the dummy gate structure, and the surface of the sidewall spacer; The material for filling the second drain region is deposited in the second cavity to form the second drain region, and the patterned second mask layer is removed.

12. An electronic device, characterized in that: A fin-gate field-effect transistor device with a hybrid conduction mechanism comprising the device described in any one of claims 1 to 8.

13. A method for manufacturing an electronic device, characterized in that: A method for manufacturing a hybrid conduction mechanism fin-gate field effect transistor device according to any one of claims 9 to 11.

Images