An integrated heterojunction Schottky diode and a method for manufacturing the same

Abstract

The application discloses an integrated heterojunction Schottky diode and a preparation method thereof. The device comprises an N-type substrate region, an N-type multi-buffer layer formed by multiple epitaxy above the N-type substrate region, an N-type drift region formed by epitaxy above the N-type multi-buffer layer, a current expansion layer formed by epitaxy above the N-type drift region, a P-type high-concentration doped region formed by ion implantation in a groove etched on the top of the current expansion layer, and N-type polysilicon formed by chemical vapor deposition above the P-type high-concentration doped region. The heterojunction formed by the P-type high-concentration doped region and the N-type polysilicon replaces the traditional ohmic contact, and when a heavy ion is incident above the P-type high-concentration doped region, the lattice temperature of the device surface can be greatly reduced, and the reliability of the device against single-event burnout is improved.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and in particular to an integrated heterojunction Schottky diode and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) possesses excellent electrical and thermal properties, such as a wide bandgap, high critical breakdown electric field, and high thermal conductivity, making it a promising power semiconductor material widely used in aerospace devices. However, research indicates that SiC Schottky diodes are susceptible to single-event burnout (SEB) due to the natural radiation environment of space. To date, the SEB effect in SiC Schottky diodes and the device failure mechanism caused by SEB have been extensively studied through experiments and simulations. When the device is in reverse bias, high-energy ion injection generates a large number of electron-hole pairs, reducing the local resistivity and allowing for instantaneous high current flow, resulting in Joule heating. Simultaneously, ion injection generates a high electric field at the Schottky interface, altering the electric field distribution in the drift region. The combination of a strong electric field and high conduction current density leads to power dissipation, raising the lattice temperature above the melting point of SiC or the surface metal, causing leakage current degradation or triggering a catastrophic SEB effect.

[0003] According to domestic and international research, existing technologies use multi-buffer layer structures to adjust the electric field distribution between the epitaxial layer and the substrate, thereby reducing N. + / N - The junction temperature improves the device's resistance to SEB, but high temperature and high electric field still exist at the Schottky junction. + High temperatures also exist near the anode metal, and Schottky diodes with multi-buffer layer structures still have the risk of single-event burnout. Summary of the Invention

[0004] This invention provides an integrated heterojunction Schottky diode and its fabrication method to solve the problem in the prior art where the highest temperature of the Schottky contact interface of the JBS diode exceeds the melting temperature of the metal after high-energy particle incident, thereby increasing the leakage current of the device and causing single-particle burn-off leading to catastrophic failure of the device.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows:

[0006] An integrated heterojunction Schottky diode includes:

[0007] N-type substrate region;

[0008] N-type multiple buffer layer, wherein the N-type multiple buffer layer is on the upper surface of the N-type substrate region;

[0009] The N-type drift region is located on the upper surface of the N-type multi-buffer layer.

[0010] A current spreading layer, the current spreading layer being on the upper surface of the N-type drift region;

[0011] The P-type high-concentration doped region is located at the bottom of the trench on the upper surface of the current spreading layer.

[0012] N-type polycrystalline silicon, wherein the N-type polycrystalline silicon is respectively on the upper surface of the P-type high-concentration doped region and forms a heterojunction with the P-type high-concentration doped region;

[0013] Anode, the anode being located on the upper surface of the current spreading layer and connected to the N-type polysilicon;

[0014] The cathode is located on the lower surface of the N-type substrate region.

[0015] Furthermore, the ion doping concentration of the N-type drift region is 2 × 10⁻⁶. 15 cm -3 .

[0016] Furthermore, the epitaxial thickness of the current spreading layer is 3.2 μm, and the ion doping concentration is 1 × 10⁻⁶. 16 cm -3 .

[0017] Furthermore, the depth of the P-type high-concentration doped region is 0.8 μm, the width is 2 μm, and the ion doping concentration is 1 × 10⁻⁶. 19 cm -3 .

[0018] Furthermore, the N-type polycrystalline silicon has a depth of 2 μm, a width of 2 μm, a distance of 2 μm between the two N-type polycrystalline silicon wafers, and an ion doping concentration of 5 × 10⁻⁶. 18 cm -3 .

[0019] Furthermore, a method for fabricating an integrated heterojunction Schottky diode includes the following steps:

[0020] S1, The N-type substrate region required for fabricating Schottky diode devices;

[0021] S2. An N-type buffer layer is epitaxially formed on the upper surface of the N-type substrate region, and the N-type multi-buffer layer is formed repeatedly.

[0022] S3. An N-type drift region is formed on the upper surface of the N-type multi-buffer layer by epitaxy;

[0023] S4. An epitaxial current spreading layer is formed on the upper surface of the N-type drift region;

[0024] S5. Use grooving technology to etch trenches above the current spreading layer;

[0025] S6. A P-type high-concentration doped region is formed at the bottom of the trench by ion implantation;

[0026] S7. N-type polycrystalline silicon is formed on the upper surface of the P-type high-concentration doped region using a chemical vapor deposition process.

[0027] S8. Metallize the upper surface of the current spreading layer and the N-type polysilicon to form an anode, and metallize the lower surface of the N-type substrate region to form a cathode.

[0028] Beneficial effects: This invention forms a heterojunction structure by depositing polycrystalline silicon on the surface of a high-concentration doped region of P-type. After high-energy particles are incident, the electric field strength, carrier collision rate and transient current density of the Schottky interface can be significantly reduced, thereby reducing the lattice temperature of the interface between silicon carbide and metal in the device. This avoids the problem of catastrophic device failure caused by melting of the diode anode metal and degradation of leakage current, thus greatly improving the diode's resistance to SEB and increasing the reliability of the device during operation. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the cell structure of a traditional JBS diode device with a buffer layer.

[0031] Figure 2 This is a schematic diagram of the cell structure of the diode device resistant to single-particle burn-out according to the present invention.

[0032] Figure 3 This is a schematic diagram of the structure corresponding to steps S1 to S2 in the preparation method of the present invention;

[0033] Figure 4 This is a schematic diagram of the structure corresponding to step S3 in the preparation method of the present invention;

[0034] Figure 5 This is a schematic diagram of the structure corresponding to step S4 in the preparation method of the present invention;

[0035] Figure 6 This is a schematic diagram of the structure corresponding to step S5 in the preparation method of the present invention;

[0036] Figure 7This is a schematic diagram of the structure corresponding to step S6 in the preparation method of the present invention;

[0037] Figure 8 This is a schematic diagram of the structure corresponding to step S7 in the preparation method of the present invention;

[0038] Figure 9 This is a schematic diagram of the structure corresponding to step S8 in the preparation method of the present invention;

[0039] Figure 10 Simulation diagrams of the Schottky contact interface temperature under different reverse bias voltages when particles are incident from the N-type region in the conventional structure and the structure of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] This embodiment provides an integrated heterojunction Schottky diode, including:

[0042] N-type substrate region 100;

[0043] N-type multi-buffer layer 101, the N-type multi-buffer layer 101 being located on the upper surface of the N-type substrate region 100;

[0044] N-type drift region 102, the N-type drift region 102 being located on the upper surface of the N-type multi-buffer layer 102;

[0045] A current spreading layer 103 is provided on the upper surface of the N-type drift region 102.

[0046] P-type high-concentration doped region 104, the P-type high-concentration doped region 104 being at the bottom of the trench on the upper surface of the current spreading layer 103;

[0047] N-type polysilicon 105, wherein the N-type polysilicon 105 is located on the upper surface of the P-type high-concentration doped region 104 and forms a heterojunction with the P-type high-concentration doped region 104;

[0048] Anode 200 is located on the upper surface of the current spreading layer 103 and is connected to the N-type polysilicon 105.

[0049] Cathode 201, the cathode 201 being located on the lower surface of the N-type substrate region 100.

[0050] Specifically, this embodiment provides an integrated heterojunction Schottky diode device structure, such as... Figure 2 As shown, it includes: an N-type substrate region 100, an N-type multi-buffer layer 101, an N-type drift region 102, a current spreading layer 103, a P-type high-concentration doped region 104, an N-type polysilicon 105, an anode 200, and a cathode 201. Figure 1 The diagram shown is a schematic of the cell structure of a conventional JBS diode device with a buffer layer in the prior art. Figure 2 The diode device structure of the present invention is different in that: the diode structure of the present invention forms a current spreading layer 103 above the N-type drift region 102, and deposits N-type polysilicon 105 on the upper surface of the P-type high-concentration doped region 104 to form a heterojunction. The heterojunction is located in the groove in the current spreading layer 103 and is in contact with the anode 200.

[0051] Specifically, after high-energy particles are incident, the P-type high-concentration doped region 104 pinches off the Schottky diode, which can significantly reduce the electric field strength at the Schottky interface, as well as the carrier collision rate and transient current density at the Schottky interface. This, in turn, lowers the lattice temperature of the silicon carbide / metal interface in the device, preventing catastrophic failure caused by melting of the diode anode metal and degradation of leakage current, thereby improving the diode's SEB resistance. Simultaneously, using a heterojunction structure instead of the traditional ohmic contact between the P-type high-concentration doped region 104 and the metal can reduce the lattice temperature of the silicon carbide / metal interface after particle incident, improving device reliability. The current spreading layer 103 can also reduce the thickness of the space charge region and the electron concentration at the interface, thereby allowing the temperature at the interface to transfer to the device interior after high-energy particle incident. Therefore, the SEB-safe operating voltage of the Schottky diode device structure of this invention is significantly improved.

[0052] In this embodiment, simulation verification is used to verify... Figure 1 and Figure 2 The two structures shown are compared and discussed. The cell size and parameters of the traditional structure used in this simulation experiment are as follows: cell width is 8 μm, and the ion doping concentration in the drift region is 2 × 10⁻⁶. 15 cm -3 P + The thickness of the region is 0.8 μm; the cell size and parameters of the structure using the present invention are as follows: cell width is 8 μm, and the ion doping concentration of the N-type drift region 102 is 2 × 10⁻⁶. 15 cm -3 The ion doping concentration of the current spreading layer is 1×10⁻⁶. 16 cm -3In the simulation of both devices, the incident particle energy (Linear Energy Transfer, LET) was chosen to be 0.5 pC / μm. For silicon carbide, each 0.1 pC / μm equals 15.1 MeV / mg / cm². 2 The particle incident point is the device surface, meaning the particle is incident perpendicularly and penetrates the entire device. The trajectory radius of the incident particle is 0.05 μm, and the initial time for charge generation is 4 × 10⁻⁶. 12 s, the time width of the Gaussian function is 2×10 12 s. Simulation results are as follows Figure 10 As shown, from Figure 10 As can be seen from the present invention, the temperature at the silicon carbide / metal interface of the Schottky diode device remains low even when the reverse bias voltage is very high, thereby preventing the anode metal of the diode device from melting and improving the device's SEB resistance. In contrast, the temperature at the silicon carbide / metal interface of the traditional JBS device structure with a buffer layer reaches a relatively high temperature even with a small reverse bias voltage. It is evident that the heterojunction structure formed by the P-type high-concentration doped region 104 and the N-type polysilicon 105 can significantly reduce the surface temperature of the device, thereby significantly improving the device's SEB safe operating voltage and enhancing the device's reliability during operation.

[0053] Example 2

[0054] This embodiment provides a method for fabricating an integrated heterojunction Schottky diode, including the following steps:

[0055] S1, N-type substrate region 100 required for fabricating Schottky diode devices;

[0056] S2. An N-type buffer layer is epitaxially formed on the upper surface of the N-type substrate region 100, and the N-type multi-buffer layer 101 is formed repeatedly.

[0057] S3. An N-type drift region 102 is formed on the upper surface of the N-type multi-buffer layer 101 by epitaxy;

[0058] S4. A current spreading layer 103 is epitaxially formed on the upper surface of the N-type drift region 102;

[0059] S5. Use grooving technology to etch trenches above the current spreading layer 103;

[0060] S6. A P-type high-concentration doped region 104 is formed at the bottom of the trench by ion implantation;

[0061] S7. N-type polycrystalline silicon 105 is formed on the upper surface of the P-type high-concentration doped region 104 using a chemical vapor deposition process.

[0062] S8. The upper surface of the current spreading layer 103 and the N-type polysilicon 105 is metallized to form an anode 200, and the lower surface of the N-type substrate region 100 is metallized to form a cathode 201.

[0063] The ion doping concentration of the N-type drift region 102 is 2 × 10⁻⁶. 15 cm -3 ;

[0064] The current spreading layer 103 has an epitaxial thickness of 3.2 μm and an ion doping concentration of 1 × 10⁻⁶. 16 cm -3 ;

[0065] The p-type high-concentration doped region 104 has a depth of 0.8 μm, a width of 2 μm, and an ion doping concentration of 1 × 10⁻⁶. 19 cm -3 ;

[0066] The N-type polycrystalline silicon 105 has a depth of 2 μm, a width of 2 μm, a distance of 2 μm between the two N-type polycrystalline silicon 105s, and an ion doping concentration of 5 × 10⁻⁶. 18 cm -3 .

[0067] Specifically, such as Figure 3 The cell structure shown corresponds to steps S1 and S2 above. First, an N-type substrate region 100 is fabricated. Then, an N-type buffer layer is formed on the upper surface of the N-type substrate region 100 through epitaxy. Repeating the epitaxial operation forms an N-type multi-buffer layer 101. The multi-buffer layer structure can adjust the electric field distribution between the epitaxial layer and the substrate, thereby reducing the N-type buffer layer. - / N + The junction temperature improves the device's resistance to SEB.

[0068] Specifically, such as Figure 4 The cell structure shown corresponds to step S3 above, where an N-type drift region 102 is formed on the upper surface of the N-type multi-buffer layer 101 through a single epitaxial growth, wherein the ion doping concentration of the N-type drift region 102 is 2 × 10⁻⁶. 15 cm -3 .

[0069] Specifically, such as Figure 5 The cell structure shown corresponds to step S4 above, where a current spreading layer 103 is formed on the upper surface of the N-type drift region 102 through a single epitaxial layer. The epitaxial thickness of the current spreading layer 103 is 3.2 μm, and the ion doping concentration is 1 × 10⁻⁶. 16 cm -3 The current spreading layer can effectively reduce the on-resistance and on-loss of the device, reduce the heat generated by the current flow, and improve the reliability of the device.

[0070] Specifically, such as Figure 6 The cell structure shown corresponds to step S5 above. Using conventional grooving techniques, trenches are etched on both sides of the top of the current spreading layer 103. The depth of the trenches is about 3 μm and the width is 2 μm.

[0071] Specifically, such as Figure 7 The cell structure shown corresponds to step S6 above, where a P-type high-concentration doped region 104 is formed at the bottom of the trench by ion implantation, i.e., P + The P-type high-concentration doped region 104 has a depth of 0.8 μm, a width of 2 μm, and an ion doping concentration of 1 × 10⁻⁶. 19 cm -3 .

[0072] Specifically, such as Figure 8 The cell structure shown corresponds to step S7 above, where an N-type polysilicon 105 is formed on the upper surface of the P-type high-concentration doped region 104 using a chemical vapor deposition process. The N-type polysilicon 105 has a depth of 2 μm, a width of 2 μm, and a spacing of 2 μm between the two N-type polysilicon 105s on both sides. The ion doping concentration is 5 × 10⁻⁶. 18 cm -3 .

[0073] Specifically, such as Figure 9 The cell structure shown corresponds to step S8 above, where the upper surface of the current spreading layer 103 and the N-type polysilicon 105 is metallized to form an anode 200, that is, the anode 200 is in contact with both the current spreading layer 103 and the N-type polysilicon 105. In addition, the lower surface of the N-type substrate region 100 is metallized to form a cathode 201.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An integrated heterojunction Schottky diode, characterized in that, include: N-type substrate region (100); An N-type multi-buffer layer (101) is located on the upper surface of the N-type substrate region (100). N-type drift region (102), the N-type drift region (102) is on the upper surface of the N-type multi-buffer layer (102); A current spreading layer (103) is located on the upper surface of the N-type drift region (102); P-type high-concentration doped region (104), the P-type high-concentration doped region (104) is at the bottom of the trench on the upper surface of the current spreading layer (103); N-type polysilicon (105), wherein the N-type polysilicon (105) is on the upper surface of the P-type high-concentration doped region (104) and forms a heterojunction with the P-type high-concentration doped region (104); Anode (200), the anode (200) is on the upper surface of the current spreading layer (103) and is connected to the N-type polysilicon (105); Cathode (201), the cathode (201) is located on the lower surface of the N-type substrate region (100).

2. The integrated heterojunction Schottky diode according to claim 1, characterized in that, The ion doping concentration of the N-type drift region (102) is 2 × 10⁻⁶. 15 cm -3 .

3. The integrated heterojunction Schottky diode according to claim 1, characterized in that, The current spreading layer (103) has an epitaxial thickness of 3.2 μm and an ion doping concentration of 1 × 10⁻⁶. 16 cm -3 .

4. An integrated heterojunction Schottky diode according to claim 1, characterized in that, The p-type high-concentration doped region (104) has a depth of 0.8 μm, a width of 2 μm, and an ion doping concentration of 1 × 10⁻⁶. 19 cm -3 .

5. An integrated heterojunction Schottky diode according to claim 1, characterized in that, The N-type polycrystalline silicon (105) has a depth of 2 μm, a width of 2 μm, a distance of 2 μm between the two N-type polycrystalline silicon (105) wafers, and an ion doping concentration of 5 × 10⁻⁶. 18 cm -3 .

6. A method for fabricating an integrated heterojunction Schottky diode according to any one of claims 1 to 5, characterized in that, Includes the following steps: S1, N-type substrate region (100) required for fabricating Schottky diode devices; S2. An N-type buffer layer is epitaxially formed on the upper surface of the N-type substrate region (100), and the N-type multi-buffer layer (101) is formed repeatedly. S3. An N-type drift region (102) is formed on the upper surface of the N-type multi-buffer layer (101) by epitaxy; S4. A current spreading layer (103) is formed epitaxially on the upper surface of the N-type drift region (102); S5. Use grooving technology to etch trenches above the current spreading layer (103); S6. A P-type high-concentration doped region (104) is formed at the bottom of the trench by ion implantation; S7. N-type polycrystalline silicon (105) is formed on the upper surface of the P-type high-concentration doped region (104) using a chemical vapor deposition process; S8. The upper surface of the current spreading layer (103) and the N-type polysilicon (105) is metallized to form an anode (200), and the lower surface of the N-type substrate region (100) is metallized to form a cathode (201).

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