Method of operating an active-clamp flyback converter and corresponding apparatus

Abstract

Embodiments of the present disclosure relate to methods of operating an active-clamp flyback converter and corresponding apparatuses. The active flyback converter transitions between a plurality of operating states based on a comparison of a control voltage signal to a voltage threshold and a count of consecutive switching periods during which a clamp switch remains off. The plurality of operating states includes a run state, an idle state, a first burst state, and a second burst state. Each group of consecutive switching periods of the first burst state includes a determined number of switching periods during which signals are generated to turn on and off a power switch and maintain an off state of a clamp switch, and a switching period in a determined position in a group of switching periods in which signals are generated in sequence to turn on the power switch, turn off the power switch, turn on the clamp switch, and turn off the clamp switch.

Description

Technical Field

[0001] Embodiments of this disclosure relate to techniques for operating an active clamp flyback converter in burst mode.

[0002] Embodiments of this disclosure particularly relate to converters used in chargers, such as USB chargers, and adapters for smartphones, tablets, and laptops. Embodiments of this disclosure may also relate to wall plugs and smart wall sockets. Background Technology

[0003] The ongoing efforts to miniaturize consumer electronics products need to be supported by increasing the power density of internal and external power converters.

[0004] Traditionally, power density can be increased by operating at higher switching frequencies, thereby reducing the size occupied by passive components such as transformers, inductors, and filter capacitors. However, with conventional topologies, the negative impact of higher switching frequencies is lower efficiency due to increased switching losses. Furthermore, in hard-switching topologies, noise and EMI become difficult to manage at high frequencies.

[0005] In low-power offline applications, flyback topologies are the most commonly used due to their simplicity and low cost. This topology is characterized by clamping circuitry that handles energy captured in the transformer leakage inductance after the power switch is turned off, thus preventing it from participating in the input-to-output energy transfer process.

[0006] Most commonly, clamping is implemented using an RCD structure, such as... Figure 1A As shown in the image.

[0007] exist Figure 1AThe diagram shows a schematic of embodiment 10 of a flyback converter, which includes a transformer 11 comprising a primary winding and a secondary winding out of phase by 180°. The transformer 11 receives a DC input voltage Vin at the DC input terminal (specifically, the positive terminal) of the primary winding, while at its secondary winding, an output diode Dout is coupled between the negative terminal of the secondary winding and the output node Vout, and an output capacitor Cout is coupled between the output node Vout and ground GND. Vout refers both to the node forming the output voltage of the converter 10 and to the output voltage itself; the same applies to the node GND and ground potential. These components essentially embody the output portion of the flyback converter device 10 (e.g., an output rectifier) ​​while providing a flyback circuit including a power switch (specifically, a MOSFET) Q1 controlled by a controller 13, which selectively couples the negative terminal of the primary winding of the transformer 11 to ground GND. The negative terminal of the primary winding is also coupled to the input node DC via an RCD (resistor-capacitor-diode) network 14 that operates as a clamping circuit. Specifically, the clamping resistor Rsn and the clamping capacitor Csn are coupled in parallel between the DC input node and the negative terminal of the clamping diode Dsn corresponding to the clamping node CN. The other terminal of the clamping diode Dsn is coupled to the negative terminal of the primary winding.

[0008] Using this clamping circuit 14, the energy stored in the transformer leakage inductance is dissipated in the clamping resistor Rsn and converted into heat. This represents the main loss of a conventional flyback converter. The voltage drop between the clamping node CN and the input voltage Vin node is typically indicated as the clamping voltage.

[0009] Active clamp flyback (ACF) converters address all these issues by providing unconditional zero-voltage switching (ZVS) operation for all power switches and rectifiers used in the circuit. ZVS is achieved by recovering the energy stored in the transformer leakage inductance in a virtually lossless manner.

[0010] Figure 1B The basic ACF converter 20 topology is shown, which includes a transformer 11 and a corresponding Figure 1A The output section downstream of the secondary winding is shown. A MOSFET switch Q1, controlled by controller 13, remains at the primary winding, selectively coupling the negative terminal of the primary winding of transformer 11 to ground GND. However, instead of RCD network 14, an active clamping circuit 24 is provided, comprising a second MOSFET switch Q2 (clamping switch) that selectively couples the terminal of clamping capacitor Cc (clamping node CN) (the other terminal coupled to input node DC) to the negative terminal of the primary winding of transformer 11 coupled to the drain of switch Q1, which is an n-channel MOSFET.

[0011] An ACF converter, such as converter 20, can be driven by two different control schemes.

[0012] The first control scheme can be represented by complementary control. In this scheme, switches Q1 and Q2 are driven in a complementary manner; when switch Q1 is on, switch Q2 is off, and when switch Q1 is off, switch Q2 is on, as shown below. Figure 2A The timing diagram shows the gate signals SQ1 and SQ2 for Q1 and Q2. Figure 2B The diagram shows the primary current I1 flowing in the primary winding of transformer 11, the secondary current I2 flowing in the secondary winding of transformer 11, and the voltage Vm at the common node between switches Q1 and Q2, as they essentially form a half-bridge, wherein the high-side switch Q2 and the low-side switch Q1 are utilized by controller 13. Figure 2A The gate signals SQ1 and SQ2 shown are used for driving. When controlled in this way, the converter 20 can typically operate with a fixed off-time in discontinuous conduction mode (DCM) because it is easier to control the off-time to achieve ZVS for switch Q1 during conduction. Leakage energy is first stored in the clamping capacitor Cc and then recovered to the output side during the conduction of the high-side switch Q2. During the conduction of the high-side switch Q2, current cycling exists simultaneously on the primary and secondary sides, resulting in high rms current, which leads to significant power losses in the transformer windings and rectifier. Furthermore, in applications with variable output voltages (e.g., USB-PD fast chargers), converter operation is difficult to optimize and ZVS cannot be achieved across the entire output voltage range, with efficiency potentially decreasing significantly at the low end of the output voltage range.

[0013] The second control scheme can be represented by non-complementary control. With this scheme, the turn-on of the active clamp high-side switch Q2 is delayed until the energy stored in the inductance of transformer 11 is fully delivered to the load, such as... Figure 3A and Figure 3B As shown in the timing diagram. Figure 3A The signals driving Q1 and Q2 are schematically shown. In this case, Q1 and Q2 will never be turned on simultaneously. Figure 3BThe diagram illustrates the primary current I, the secondary current Io, and the voltage Vm at the common node between switches Q1 and Q2, as well as the signals driving the Q1 and Q2 switches and the MOSFET gate. As shown, when the secondary current Io reaches its minimum, the energy stored in the inductor is fully released, the SQ2 signal goes high, the secondary current rises and the primary current falls in the reverse current Ir region until the SQ2 signal goes low. This helps reduce the energy circulating in the transformer windings and the associated power losses. In fact, the recovery mechanism of the leakage inductance energy stored in the clamping capacitor is the same as in the complementary control scheme, but the time interval between the simultaneous current circulation on the primary and secondary sides is much shorter. As an input-to-output energy transfer mechanism essentially the same as that of a standard flyback converter, the non-complementary control scheme is more suitable for variable output voltage converters and achieves ZVS across the entire operating range.

[0014] Due to ZVS and leakage energy recovery, ACF converters typically exhibit higher efficiency than conventional flyback converters under heavier loads, making them the preferred choice for low-power, high-density designs where thermal issues are a primary concern.

[0015] However, adding an active clamp high-side switch Q2 to a standard flyback converter achieves soft switching (ZVS), at the cost of additional conduction losses on the primary side (complementary control has greater losses than non-complementary control). Furthermore, there are losses associated with driving the active clamp high-side switch Q2 (gate drive plus switching). All these losses are almost independent of the load. Therefore, under very light loads, these additional losses outweigh the losses saved by the ZVS of Q1. On the other hand, under very light loads, the energy stored in the leakage inductance of the flyback transformer is practically negligible, so the efficiency of the ACF may be lower than that of a conventional flyback with RCD clamping. This is especially true at low input voltages, where even a standard flyback converter may exhibit ZVS (when the input voltage is lower than the output voltage reflected to the primary side).

[0016] This could be a significant problem, as it may be difficult to meet standby energy efficiency targets defined by various regulatory bodies, such as the European Code of Conduct, Energy Star, etc.

[0017] These considerations have led some power supply manufacturers to consider so-called "hybrid clamping," a combination of active clamping and RCD clamping, as exemplified in L. Huber et al.'s "Flyback Converter with Hybrid Clamp," APEC 2018 Conference Proceedings, pp. 2098-2103. Figure 4A The figure shows an embodiment 30 of an AFC converter, which corresponds to... Figure 1AIn embodiment 20, the clamping circuit 34 includes a clamping resistor Rsn coupled in parallel with a clamping capacitor Cc between the input DC and the high-side switch Q2. It incorporates a power management circuit that configures the clamping as active clamping or RCD clamping depending on the converter's operating conditions. In the active clamping configuration, the high-side switch Q2 operates as previously described (in a complementary or non-complementary manner); in the RCD clamping configuration, the high-side switch Q2 remains in the off state.

[0018] The load level at which a favorable switch from active clamping to RCD clamping (and vice versa) occurs cannot be predicted well. It depends on many parameters of the power stage and the characteristics of the control. Power management circuitry capable of handling such intricacy would be overly complex and expensive.

[0019] However, a very common technique for optimizing efficiency under extremely light loads in all switching converters is to operate them in what is known as “burst mode.” In this operating mode, the converter operates intermittently, with a series of (burst) switching cycles separated by time intervals (idle times) during which the converter does not switch. Therefore, a very simple solution is to switch from active clamp to RCD clamp when the load becomes low enough that the converter begins operating in burst mode, and switch back to active clamp when the converter resumes continuous operation due to higher loads.

[0020] Compared to active clamping, hybrid clamping uses an additional resistor. This additional component has some impact on cost and PCB area (a critical aspect in high-density designs), particularly on no-load consumption (power input to the converter when the load is disconnected), which is one of the energy efficiency targets. Although the resistor value required in hybrid clamping is higher than that required in pure RCD clamping, there is a power loss that partially offsets the power savings from not turning on Q2 and adversely affects efficiency and no-load consumption under very light loads.

[0021] However, resistor Rsn must be installed in place to prevent the clamp capacitor voltage from drifting uncontrollably high: during each switching cycle, a small amount of charge will come from the body diode of the high-side switch Q2, and nothing will discharge it. Overcharging the clamp capacitor, even if it does not exceed its rated voltage or cause the voltage across Q1 to exceed its breakdown voltage during Q1's off period, still has a significant drawback. When the converter resumes its continuous switching activity, for many switching cycles, a large current will flow uncontrollably in switch Q2 and in the output rectifier during the high-side switch Q2's on period until the overcharged clamp capacitor voltage returns to its correct value.

[0022] To save power loss in the RCD clamping resistor, the publication "Light-Load Efficiency Improvement for Flyback Converter Based on HybridClamp Circuit" by YTYau1, WZ Jiang, and KIHwu (APEC 2016 conference proceedings, pp. 329-333) suggests the following: Figure 4B In embodiment 40 of the converter shown, which includes clamping circuit 44, a TVS (transient voltage suppressor) is used instead of resistor Rsn. As shown, the clamping resistor Rsn is replaced by TVS Tsn, and diode DT is placed in series between TVS and secondary winding to prevent reverse current from flowing through TVS Tsn.

[0023] Figure 4B This solution is relative to Figure 4A The solution offers slightly lower losses, but everything else remains the same. This slight improvement comes at the cost of two additional components, one of which (TVS) is relatively expensive, costing significantly more than a single resistor. Summary of the Invention

[0024] In one embodiment, a method includes: comparing a control signal for an active clamp flyback converter with a plurality of three or more thresholds; counting the number of consecutive switching cycles during which a clamp switch of the active clamp flyback converter remains off; and selectively switching the active clamp flyback converter between a plurality of operating states by controlling a power switch and a clamp switch of the active clamp flyback converter. The multiple operating states include: an operating state of one or more consecutive switching cycles of the active flyback converter, each switching cycle during the operating state including sequentially turning on the power switch, turning off the power switch, turning on the clamp switch, and turning off the clamp switch; an idle state of one or more consecutive switching cycles of the active flyback converter, during which the power switch and the clamp switch are off; a first burst state of one or more sets of consecutive switching cycles, each set of consecutive switching cycles of the first burst state including: a determined number of switching cycles during which the power switch is turned on and off and the clamp switch is off; and a switching cycle at a position determined in a set of switching cycles including sequentially turning on the power switch, turning off the power switch, turning on the clamp switch, and turning off the clamp switch; and a second burst state of one or more sets of consecutive switching cycles during which the power switch is turned on and off and the clamp switch is off. Selective switching is based on comparisons of a control signal with multiple three or more thresholds and counting of consecutive switching cycles during which the clamp switch remains off.

[0025] In one embodiment, a system includes: an active clamp flyback converter having a transformer, a power switch, and a clamping switch; and control circuitry coupled to the active clamp flyback converter, wherein the control circuitry, in operation: compares a control voltage of the active clamp flyback converter with a first voltage threshold, a second voltage threshold having an amplitude greater than the first voltage threshold, and a third voltage threshold having an amplitude greater than the second voltage threshold; counts the number of consecutive switching cycles during which the clamping switch remains off; and selectively switches the active clamp flyback converter between multiple operating states. Multiple operating states include: an operating state of one or more consecutive switching cycles of an active flyback converter, each switching cycle during the operating state including sequentially turning on a power switch, turning off a power switch, turning on a clamping switch, and turning off a clamping switch; an idle state of one or more consecutive switching cycles of an active flyback converter, during which the power switch and clamping switch are off; a first burst state of one or more sets of consecutive switching cycles, each set of consecutive switching cycles of the first burst state including: a determined number of switching cycles during which the power switch is turned on and off and the clamping switch is off; and a switching cycle at a position determined in a set of switching cycles including sequentially turning on a power switch, turning off a power switch, turning on a clamping switch, and turning off a clamping switch; and a second burst state of one or more sets of consecutive switching cycles during which the power switch is turned on and off and the clamping switch is off, wherein the selective switching is based on a comparison of a control signal with a voltage threshold and a count of the number of consecutive switching cycles during which the clamping switch remains off.

[0026] In one embodiment, a device includes: one or more comparators that, in operation, compare a control voltage signal of an active clamp flyback converter with a first voltage threshold, a second voltage threshold, and a third voltage threshold, wherein the magnitude of the second voltage threshold is greater than the magnitude of the first voltage threshold and the magnitude of the third voltage threshold is greater than the magnitude of the second voltage threshold; and logic circuitry coupled to the one or more comparators, wherein, in operation, the logic circuitry selectively transitions between a plurality of operating states, the plurality of operating states including: an operating state of operation for one or more consecutive switching cycles, each switching cycle during the operating state of operation including sequentially generating signals to turn on a power switch, turn off a power switch, turn on a clamp switch, and turn off a clamp switch; and an idle state of operation for one or more consecutive switching cycles of the active flyback converter. During an idle state, a signal is generated to maintain the off state of the power switch and the clamp switch; a first burst state of operation of one or more sets of continuous switching cycles, each set of continuous switching cycles of the first burst state comprising: a determined number of switching cycles during which a signal is generated to turn the power switch on and off and maintain the off state of the clamp switch; and a switching cycle at a position determined in a set of switching cycles in which signals are generated sequentially to turn the power switch on, turn off the power switch, turn on the clamp switch, and turn off the clamp switch; and a second burst state of operation of one or more sets of continuous switching cycles during which a signal is generated to turn the power switch on and off and maintain the off state of the clamp switch; and counting the number of continuous switching cycles during which the clamp switch is maintained in the off state. Selective switching is based on a comparison of a control voltage signal with a voltage threshold and the counting of the number of continuous switching cycles during which the clamp switch is maintained in the off state.

[0027] In an embodiment, the content of a non-transitory computer-readable medium enables control circuitry to control the operation of an active flyback converter device. This control includes selectively switching the active clamp flyback converter between multiple operating states by controlling a power switch and a clamp switch of the active clamp flyback converter. These multiple operating states include: an operating state of one or more consecutive switching cycles of the active flyback converter, each switching cycle during the operating state including sequentially turning on the power switch, turning off the power switch, turning on the clamp switch, and turning off the clamp switch; an idle state of one or more consecutive switching cycles of the active flyback converter, during which the power switch and the clamp switch are turned off; and a first burst state of one or more sets of consecutive switching cycles of operation, each set of consecutive switching cycles of the first burst state including... The system comprises: determining a number of switching cycles during which a power switch is turned on and off and a clamping switch is turned off; and a switching cycle at a position determined in a set of switching cycles including sequentially turning on a power switch, turning off a power switch, turning on a clamping switch, and turning off a clamping switch; and a second burst state of operation of one or more sets of consecutive switching cycles during which the power switch is turned on and off and the clamping switch is turned off; comparing a control signal for an active clamp flyback converter with a plurality of three or more thresholds; and counting the number of consecutive switching cycles during which the clamping switch remains off, wherein selective switching is based on comparisons of the control signal with a plurality of three or more thresholds and counting the number of consecutive switching cycles during which the clamping switch remains off. Attached Figure Description

[0028] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, which are provided by way of non-limiting example only, in which:

[0029] Figure 1A This is a schematic diagram of a flyback converter;

[0030] Figure 1B This is a schematic diagram of an active clamp flyback (ACF) converter;

[0031] Figure 2A This is a timing diagram illustrating example control signals used to control an ACF converter using a complementary control method;

[0032] Figure 2B The illustration shows an example current and voltage of an ACF converter controlled using a complementary control method;

[0033] Figure 3A This is a timing diagram illustrating example control signals used to control an ACF converter using a non-complementary control method;

[0034] Figure 3BThe illustration shows an example current and voltage of an ACT converter controlled using a non-complementary control method;

[0035] Figure 4A This is a schematic diagram of a hybrid clamp flyback converter;

[0036] Figure 4B This is a schematic diagram of a hybrid clamp flyback converter with a transient voltage suppressor (TVS);

[0037] Figure 5 The architecture of a converter configured to operate using embodiments of the methods described herein is illustrated schematically.

[0038] Figure 6 A state diagram representing an embodiment of the method described herein is shown;

[0039] Figure 7A and Figure 7B A time diagram of the control quantities used in embodiments of the method described herein under two different operating conditions is shown;

[0040] Figure 8 It schematically shows that it can be Figure 5 An example of a controller used in a converter;

[0041] Figure 9 and Figure 10 A time-plot of a simulation showing the time evolution of quantities in a converter operating according to an embodiment of the method described herein is shown; and

[0042] Figure 11 A state diagram representing a general embodiment of the method described herein is shown. Detailed Implementation

[0043] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. Embodiments may be practiced without one or more of these specific details, or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring aspects of the embodiments.

[0044] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification do not necessarily refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0045] The headings provided herein are for convenience only and do not explain the scope or meaning of the embodiments.

[0046] In short, the solution described herein relates to a method for operating an ACF converter during burst mode to reduce losses associated with operating the high-side switch Q2. Embodiments may include control circuitry for implementing the method, for example, implemented in an integrated form on a silicon die.

[0047] exist Figure 5 The diagram illustrates the architecture of an isolated ACF flyback DC-DC converter, which uses a converter such as converter 20 and also includes feedback control modules or circuits 52, 53 to control switches Q1, Q2 via controller 80. First, how the energy flow from input to output is controlled in this architecture is discussed here. In most DC-DC converters, the output voltage is kept constant using a closed-loop negative feedback control system to counteract operating conditions (input DC voltage Vin and output current I). out The changes in ) . For example Figure 5 As shown in the block diagram, this is achieved by increasing the output voltage V. out This is achieved by comparing the signal with a reference voltage (not shown in the figure) in the output feedback control block 52; their difference is also amplified by an error amplifier in the output control block 52 and is typically transmitted to the primary side across the isolation boundary via an optocoupler OS that ensures current isolation signal transmission. On the primary side, the optocoupler OS is coupled to a module or circuit 53 that receives the error signal and generates a control voltage Vc for a controller 80, which corresponds to controller 13 and supplies gate signals SQ1 and SQ2 under the control of the control voltage Vc, thereby implementing the burst operation method described herein.

[0048] Modules 52, 53, and 80 are configured to use the error signal calculated in module 52 to implement closed-loop negative feedback to generate a control voltage Vc. Of course, one or more conversion blocks (e.g., PID control blocks) that generate the control voltage based on the error signal can be located at module 52 (so the control voltage Vc can be sent simply via an electrically isolated signal transmission) or at module 53 (in which case the error signal can be sent via an electrically isolated signal transmission). This control voltage Vc modifies a quantity within converter 20, to which the power carried by converter 20 is substantially dependent. In a (conventional or active clamp) flyback converter, this quantity is typically the peak primary current in each switching cycle, which can be changed by altering the moment when switch Q1 is turned off, typically at the falling edge of the PWM signal driving switch Q1.

[0049] Using the described arrangement, the control voltage Vc changes with the output voltage V out Decreasing (increasing the error signal) increases it, and vice versa. This is because an increase in load during open-loop operation leads to a decrease in the output voltage V.out Therefore, in closed-loop operation, the control voltage Vc increases when the load increases and decreases when the load decreases. Thus, burst-mode operation can be implemented using a comparator with a given hysteresis value that compares the control voltage Vc to a threshold. Its operation can be explained as follows.

[0050] When the load decreases to the point where the control voltage Vc drops to a threshold (which corresponds to the first threshold Vth1 in the method described below), the converter stops switching and an idle period begins. Since no energy is delivered during the idle period, the load is only supplied by the filtering system (typically...). Figure 1B and Figure 5 The output capacitor C shown out The group (which is also used here as an energy storage device) supplies and outputs voltage V. out The decay begins. The negative feedback loops 52, 53, and 80 affect the output voltage V. out This attenuation reacts by increasing the control voltage Vc, and when it exceeds a threshold equal to the hysteresis value (which corresponds to the second threshold Vth2 in the method described below), the switching restarts and the idle time ends. Thus, the output voltage V... out Increase; therefore, the control voltage Vc decreases and once it drops below the threshold Vth1 again, the converter 20 stops switching again, and so on.

[0051] Therefore, under the control of negative feedback loops 52, 53, and 80, converter 20 operates in burst mode between an idle mode (hereinafter indicated by S2) when the converter stops switching and a normal operation mode (hereinafter indicated by S1) where switches Q1 and Q2 switch continuously. Burst mode always exists in both normal and burst operation, at least by changing signal SQ1 (which is, for example, a PWM signal) to change a quantity within converter 20 (e.g., the peak primary current in each switching cycle) based on the control voltage Vc value. The power carried by converter 20 is substantially dependent on this quantity. Burst mode is implemented by controller 80, as it is also controlled by... Figure 1A , 1B and Figure 4A , 4B The prior art controller 13 shown is implemented.

[0052] Regarding this burst-mode operation of converter 20, the method described herein provides a burst-mode operation that also includes the following steps:

[0053] The method provides: three voltage thresholds Vth1, Vth2, and Vth3 are available, where Vth1 < Vth2 < Vth3; and a comparison circuit, which may include, for example, a comparator with hysteresis using the first threshold Vth1 and the second threshold Vth2 as hysteresis thresholds and another comparator for the third threshold Vth3, which compares the control voltage Vc with the three thresholds Vth1, Vth2, and Vth3. Thus, the method provides: comparing the control voltage Vc with the three thresholds Vth1, Vth2, and Vth3, and this control voltage Vc is also used to control the output voltage V out . In normal mode or operating mode, the converter 20 performs switching according to complementary or non-complementary mode and controls V out to Vc (e.g., changing the peak current, as mentioned);

[0054] For Vc < Vth1, below the first and lowest threshold, it enters burst mode and first enters the idle mode. The switching of the converter 20 that drives the half-bridge Q1, Q2 in a complementary or non-complementary manner is stopped, and it enters the idle mode or state; as a result, the output voltage V out slightly decreases, and thus the control voltage Vc increases;

[0055] When the control voltage Vc increases and it exceeds the second threshold, Vc > Vth2, the switching of the converter 20 restarts (since it is after the idle time interval). The high-side switch Q2 conducts only in a given switching period (the p-th period or period p) in the burst, especially the first switching period in the burst, and if N x is the number of determined switching periods, then starting from such a given switching period p (which is thus the first switching period of the previous N x switching periods), every N x switching periods, in the switching period that first occurs after this determined number of switching periods N x for example, in period N x + p, 2N x + p, 3N x + p, it also conducts, which of course is compatible with the length of the burst, the number of periods n sw in the burst;

[0056] Subsequently, the output voltage V out increases and the control voltage Vc decreases; when Vc < Vthl, the switching stops again. Such repeated operation is performed if the load of the converter does not increase significantly such that the control voltage Vc remains below the third threshold Vth3, Vc < Vth3;

[0057] Normal operation, when Vc > Vth3 or the number of switching periods in the burst exceeds the threshold number nswmax When this occurs, the operating state (where the high-side switch Q2 is turned on every cycle) is restored. If the load causes the control voltage Vc to be stably contained between the first threshold and the third threshold, i.e., Vth1 < Vc < Vth3, then this dual-restoration option prevents the high-side switch Q2 from being turned on once every N x cycles for continuous operation;

[0058] Optionally, the high-side switch Q2 that is turned on only once every N x cycles (except for every first cycle) can be enabled depending on the input voltage value at the DC input. For example, only with a low input voltage value (e.g., such as in a US or Japanese power supply, e.g., 140 Vac), while at a high input voltage, the high-side switch Q2 is turned on in every cycle of the burst, just like in normal continuous operation.

[0059] In other words, in the case where Vc oscillates between Vth1 and Vth2, if the control voltage Vc is stably contained between the first threshold and the third threshold, i.e., Vth1 < Vc < Vth3, and if the load increases slightly above the level that causes burst-mode operation, then continuous operation occurs where the high-side switch Q2 is turned on once every Nx cycles. If the load (and Vc) drops from a higher value (e.g., Vc > Vth3) to within Vth1 and Vth3, the operation of the converter will be continuous and both switches will operate normally in each switching cycle. Vc needs to drop below Vth1 for the high-side switch Q2 to be turned on once every N x cycles to activate the operation.

[0060] Figure 6 The state diagram shown in Figures 7A to 7B and the timing diagram in

[0061] both illustrate this method. Figure 6 and Figure 7A 、 7B The circuit implementation of the previously disclosed method and the explanation of its operation illustrated in

[0062] are provided in detail in the description of the exemplary embodiment. Figure 6 A state diagram is shown in

[0063] which includes an operating state S1, an idle state S2, a burst state S3 where the high-side transistor is turned on, and a burst state S4 where the high-side transistor is turned off.

[0064] If Vc ≤ Vth1, then the transition T12 from state S1 to the idle state S2 occurs. In the idle state S2, RUN = 0, BM = 1, and switching stops. The variable n sw is set to 1.

[0065] Due to a significant increase in the load, if Vc > Vth3, then the reverse transition T21 from the idle state S2 to the operating state S1 occurs.

[0066] As indicated by the transition T22, when Vc < Vth2, the idle state S2 is maintained. As mentioned, this causes the output voltage V out to drop, thereby controlling the voltage Vc to rise.

[0067] The transition T23 indicates that the control voltage Vc rises above the second threshold voltage Vth2 (Vc > Vth2), so a burst state in which Q2 conducts is obtained. RUN = 1, so the converter is switching, and BM = 1, and it operates in burst mode. The variable n sw is incremented by 1.

[0068] Then, from state S3, if Vc ≤ Vth1, then the transition T32 back to the idle state S2 is executed.

[0069] If Vc > Vth3 or n sw = n swmax , where n swmax is the maximum number of threshold switching cycles determined in the burst, then the transition T31 to the operating state S1 is executed. If the load is such that Vth1 < Vc < Vth3, this prevents the converter from continuously operating with the high-side switch Q2 conducting once every N x cycles.

[0070] If the remainder of the integer division of n sw by N x ≠ 1 and n sw < n swmax , where this number n sw of switching cycles is such that the remainder of the integer division by the determined number of switching cycles N x is not 1, and this value corresponds to the position in the sequence of switching cycles where the high-side transistor is set to conduct, specifically the first position, which can therefore be a multiple of 1 or N x and it is less than the maximum threshold number of cycles n swmax , then the transition T34 from the burst state S3 in which the high-side transistor Q2 conducts to the burst state S4 in which the high-side transistor is cut off is executed. This transition T34 can also be adjusted to a logic signal revealing that the input voltage of the converter is within the range in the United States or Japan. Refer to Figure 11To elaborate further, if position p in the sudden switching cycle sequence is not 1, then evaluate whether n... sw MOD N x ≠ p, the current switching cycle number n during a sudden event sw Does this result in dividing by the predetermined number of switching cycles N? x The remainder of integer division is different from the value of a given position p in the selected burst switching cycle sequence.

[0071] In state S4, RUN=1, BM=1, and the variable n indicates the number of switching cycles. sw Increase by 1.

[0072] State S4 is maintained by periodic transition T44, and then if n sw MOD N x ≠ 1 and n sw <n swmax Then the conditions for transforming T34 are met.

[0073] Conversely, if n sw MOD N x =1 and n sw <n swmax Then the number of switching cycles corresponds to the determined number of cycles N. x Within its internal high-side transistor, conduction can be performed once or a number of N. x A multiple of n, and it is less than n. swmax The transition from state S4 back to state S3 is executed.

[0074] If Vc≤Vth1, then perform the transition T42 from state S4 to idle state S2.

[0075] If Vc > Vth3 or n sw =n swmax If the state exits state S4, the transition T41 to running state S1 will be executed.

[0076] exist Figure 7A and Figure 7B The figure shows the control voltage Vc as a function of... Figure 6 A graph showing the evolution of the state over time. Three thresholds are indicated by horizontal lines.

[0077] like Figure 7A As shown, this refers to the situation where converter 20 exits burst mode because Vc > Vth3. Converter 20 starts in operating state S1. Finally, the control voltage Vc exceeds the third voltage Vth3, and it eventually enters operating state S1 from state S4.

[0078] Figure 7B This refers to converter 20 having a switching cycle count greater than the maximum threshold number n. swmaxThe situation where the sudden mode is exited is (Vc does not exceed Vth3, but in any case, it enters the final running state S1 from S4).

[0079] Therefore, based on the above, the solution described herein refers to a method for an active clamp flyback converter operating in burst mode, the active clamp flyback converter including a transformer 11 and switching circuits Q1, Q2, such as circuit 24, driven by a controller 13, utilizing active clamping to determine the clamping voltage drop between the input terminal nodes and the clamping nodes, particularly the voltage drop across the clamping capacitors, such as the clamping nodes being coupled between the terminals of the primary winding of the transformer, the switching circuits including:

[0080] A high-side clamping switch Q2 coupled between the clamping node CN and the other terminal of the primary winding, and

[0081] A low-side transistor Q1 is coupled between another terminal of the primary winding of transformer 11 and ground GN. The high-side clamping transistor Q2 and the low-side transistor Q1 are driven to switch between on and off states according to complementary or non-complementary control.

[0082] The high-side clamping transistor Q2 and the low-side transistor Q1 are controlled by controller 13 based on the output voltage V of the converter in the control loop. out The control voltage Vc is generated by the error signal between the reference voltage and the control voltage.

[0083] The method includes a burst operation mode, wherein the high-side clamping transistor Q2 and the low-side transistor Q1 are driven in bursts of switching cycles S3 and S4, which are separated by idle time intervals during which the converter 20 does not switch.

[0084] The method includes, in burst operation modes S3 and S4;

[0085] The control voltage Vc is compared with a set of thresholds, which includes at least a first threshold Vth1, a second threshold Vth2, and a third threshold Vth3 with increments.

[0086] If the control voltage Vc is less than the first threshold for stopping switching, then enter the idle state S2;

[0087] If the control voltage Vc subsequently becomes greater than the second threshold Vth2, switching resumes, and only in the first cycle, the high-side clamping switch Q2 is turned on at the first position p of the switching cycle sequence counting from the burst p=1 of the switching cycle in the burst comprising multiple switching cycles, and if the number n of subsequent cycles counting from the first cycle in the burst... sw Exceeding the predetermined number of switching cycles N x Then the number of subsequent switching cycles N is determined.x Begin with the first cycle of the switching cycle during the outbreak;

[0088] If the control voltage Vc subsequently becomes greater than the second threshold Vth2, a burst is executed in which switching is resumed, and the burst consists of multiple switching cycles n. sw The high-side clamping switch Q2 is used only during the plurality of switching cycles n sw In a given position (first position), multiple switching cycles n during a burst. sw It is turned on in a given period p (the first period), and if the number of periods in the burst counted from the given first period exceeds the determined number of switching periods N. x Then, whenever the determined number of switching cycles N x The determined number of switching cycles N x Then, in the first switching cycle that occurs after counting from the first given cycle of the switching cycle in the burst, the high-side clamping switch Q2 is turned on;

[0089] If the control voltage Vc is greater than the third threshold Vth3 or the number of cycles in the plurality of switching cycles during a burst exceeds the determined maximum value n swmax Then it enters the normal operation mode S1.

[0090] Furthermore, the method may include: and if the number of cycles in the burst exceeds the determined number of switching cycles N. x (Each determined number of switching cycles N) x Depending on the input voltage value of the converter, especially if the input voltage is equal to or lower than a given value, the high-side clamping switch Q2 is turned on in a given switching cycle (especially the first switching cycle).

[0091] exist Figure 8 The implementation reference is shown in the figure. Figure 6 and Figure 7A , 7BExample 80 of the controller circuitry for the described method. Specifically, the method is implemented by block 81, and the other components of the circuitry 80 outside block 81 are typically standard functional blocks found in any ACF controller, such as controller 13. The “PWM generator” block 801 generates PWM (Pulse Width Modulation) signals PWM1 and PWM2, which essentially determine the on / off states of transistors or switches Q1 and Q2, respectively (they correspond to the gate signals SQ1 and SQ2). Signals PWM1 and PWM2 will never be high simultaneously. When PWM1 is high, Q1 is on, and when PWM1 is low, Q1 is off; when PWM2 is high, Q2 is on, and when PWM2 is low, Q2 is off. The generation of PWM1 and PWM2 depends on whether PWM generator 801 achieves complementarity in non-complementary control (see [link to relevant documentation]). Figure 2A , 2B and Figure 3A , 3B (SQ1 and SQ2 signals in the PWM generator). The PWM generator 801 also receives a control voltage Vc, which typically determines the instant when the signal PWM1 (the gate signal of MOSFET switch Q1) transitions from high to low to turn off the low-side switch Q1.

[0092] The signals PWM1 and PWM2 output by PWM generator 801 are processed by "dead-time generator" 802, which inserts a short time interval after either PWM1 or PWM2 signal goes low. During this time interval (called the "dead time"), the outputs SQ1 and SQ2 of block 802, which are outputs of controller 80, are both low, causing switches Q1 and Q2 to turn off. This function is used by the ACF converter to achieve ZVS when switches Q1 and Q2 are on, as it provides time to the midpoint of the Q1 / Q2 branch to achieve rail-to-rail transition.

[0093] A comparator with a hysteresis CO1 is typically used to implement burst mode operation. It receives a control voltage Vc and a first threshold Vth1 and a second threshold Vth1 as its hysteresis threshold at its input. When the control voltage Vc is greater than the first threshold Vth1, the run mode signal RUN or flag goes high, PWM generator 801 is enabled, and PWM signals PWM1 and PWM2 are provided to dead-time generator 802. Similarly, the high-impedance logic signal HI-Z, output from generator 801 to dead-time generator 802, goes low, causing switches Q1 and Q2 to be continuously driven.

[0094] When the control voltage Vc drops below the first threshold Vth1, the run mode signal RUN goes low, the PWM generator 802 is disabled, and the HI-Z signal goes high. This keeps both drive signals SQ1 and SQ2 low, causing switches Q1 and Q2 to turn off. When the control voltage Vc exceeds the second threshold Vth2 > Vth1, the hysteresis of the first comparator CO1 causes the run mode signal RUN to go high and switch to restart.

[0095] Circuit 81 is configured to regulate a signal designed to determine the on and off states of the high-side switch Q2, in order to satisfy... Figure 6 State diagram and Figure 7A , 7B The operations illustrated in the timeline.

[0096] Circuit 81 receives the control voltage Vc and the run mode signal RUN, inverted by the NOT gate NOT1, as inputs, and supplies the switch Q2 enable signal Q2EN, the regulation of which (specifically via the AND gate AND1) is provided to the gate signal SQ2 of the floating driver of the high-side switch Q2. The AND gate AND1 receives the Q2 enable signal Q2EN and the PWM signal PWM2 for the switch Q2 as inputs, or a version D2 with a dead time inserted by block 802, such as... Figure 8 In the example.

[0097] Circuit 81 includes two counters, one MOD-n swmax Counter 811 and a MOD-N x Counters 812 are disabled and held in a "reset to zero" state by applying a high logic level to their reset input R. They are shown in common area 814, as they could be implemented as a single block outputting two signals, but for clarity of this description, they are considered as separate blocks.

[0098] As long as the number of PWM cycles (e.g., rising edge) of the PWM1 signal from the last reset to zero count is less than the maximum number of cycles n. swmax MOD-n swmax The output of counter 811 is low, and the maximum number of cycles n swmax It is a number that is internally set to a fixed value; when the number of PWM cycles n is counted... sw equal to n swmax When this happens, the output of counter 811 goes high.

[0099] MOD-N in the example shown x The output of counter 812 is high during the first counting cycle after it has been reset (as discussed below, the reset signal can be delayed to allow MOD-N). xCounter 812 goes high after p cycles and remains high for the remaining N cycles. x -1 is low, where N is low. x It is internally fixed at a value below the maximum number n. swmax A number of appropriate values <n swmax The number N x Determine the frequency at which the high-side switch Q2 is turned on.

[0100] Because the number of PWM cycles n is counted sw equals N x Counter 812 will reset itself to zero. In this way, after its reset input is activated low, the first and Nth... x +1, 2N x +1 and other switching cycles (if the first conduction of switch Q2 occurs in cycle p, then in N) x +p、2N x The output of the counter (+p, etc.) is high, thus realizing the transition condition n. sw MOD N x =1 (If the first conduction of switch Q2 occurs during the p-th cycle, then n) sw MOD N x =p), such as Figure 6 The state diagram for transition T43 is shown.

[0101] Circuit 81 also includes a second comparator CO2 that compares the control voltage Vc with the third threshold voltage Vth3>Vth2>Vth1, an edge-triggered SR latch FF1, and some logic gates NOT1, OR1, OR2, OR3, AND1, which will be described below.

[0102] To describe the operation of the circuit, it is assumed here that the initial load condition of the ACF converter is Vc > Vth3 (e.g., Figure 7A , Figure 7B (As shown in the diagram). The output of the first comparator CO1, i.e., the flag RUN, is high, so the PWM generator 801 is active, the signal HI-Z is low, and the dead-time generator 802 outputs its signal SQ1 (because it is directly the gate signal of switch Q1) and D2, which is then used to obtain the gate signal SQ2 of switch Q2 through the logic gate AND1. The output of the second comparator CO2 is also high, and this is the output of the OR gate OR1, whose two inputs are coupled to the output of the second comparator CO2 and the output of the counter 811. Therefore, the reset input R of the reset latch FF1 (which is coupled to the output of the OR gate OR1) is high, while its set input S (which is the output of the NOT gate NOT1, coupled to the output of the first comparator CO1, and therefore equal to the set input S) is high. The value is low. The reset latch FF1 is set and then in its reset state, its output Q=BM, indicating burst mode, is low and the output Q̅= is inverted. It is high. It has input as... The output of OR3, which is the OR gate of counter 812 (Q2 enable signal Q2EN), is also high, and the output of AND1, which is the AND gate of dead-time generator block 802 with the output D2 of dead-time generator block 802 having the Q2 enable signal Q2EN as input and driving the high-side switch Q2, is equal to such an output O2. Therefore, the two switches Q1 and Q2 are turned on and off in each switching cycle according to the implemented control method (complementary or non-complementary).

[0103] Reverse the burst mode flag When it is high, it has the input as and The output of OR2 is also high, and both counters, whose output is the reset signal of OR2, are held in the reset state with their outputs low.

[0104] Now, suppose the converter load drops until the control voltage Vc drops below Vth1, which causes the output of the first comparator CO1 (i.e., the RUN signal) to go low. This disables the PWM generator 801, which sets the high-impedance signal HI-Z high, causing both outputs of the dead-time generator 802 to go low. Switches Q1 and Q2 then turn off, and the converter stops. Simultaneously, the output of the NOT gate goes high; the output of the second comparator CO2 also goes low, and therefore MOD-n... swmax The output of counter 811 is also low, so latch FF1 is set and its Q output (internal variable BM) goes high. When it is low, the Q2 enable signal Q2EN is equal to MOD-N. x The output of counter 812. Since the output of NOT1 is high, both counters 811 and 812 remain in their reset state.

[0105] Since the converter stops, no energy is delivered to the output, therefore the output capacitor C out Discharged by load current, and output voltage V out Attenuation. This is sensed by the control loop that responds to an increase in the control voltage Vc. When the control voltage Vc exceeds Vth2, the run mode signal RUN returns high, reactivating the PWM generator 801 and thus restarting the switching activity of Q1 and Q2.

[0106] Simultaneously, the output of NOT1 goes low, unlocking the two counters 811 and 812, which then begin counting the switching cycles. With both inputs of OR1 low, latch FF1 remains in its set state, and the burst mode signals BM and... Maintain their levels (high and low, respectively). During the first switching cycle after the RUN signal goes high, MOD-N... x The counter output is high, therefore the clamp enable signal Q2EN is high, and when the dead-time generator 802 activates its corresponding output SQ2 high, the clamp high-side switch Q2 can be turned on. In subsequent cycles, until the Nth cycle... x One cycle, MOD-N x When the output of counter 812 is low, the clamp enable signal Q2EN is also low, and the clamp high-side switch Q2 will not be turned on.

[0107] As the switching activity restarts, the energy delivered to the output replenishes the output capacitor Cout, and the output voltage Vout increases. This is sensed by the control loop that reacts to a decrease in the control voltage Vc. Since the load remains unchanged, after a period of time, the control voltage Vc again drops below the first threshold Vth1, and the run mode flag RUN goes low, stopping the converter 50 and causing the same sequence of events described earlier.

[0108] Taking into account extremely light load conditions, the total number of sudden switching cycles, n, during this time interval of switching activity. sw Below the predefined number N x Then the clamping high-side switch Q2 will only conduct once in the first cycle of the burst; if a higher load level is considered, n sw >N x Then the clamping high-side switch Q2 is turned on (1 + INT). x [Number] times, where the function INT returns the largest integer less than or equal to the argument. Conduction occurs when condition n is met. sw MOD N x =1 (n sw =1, N x +1…m N x In those periods (where m is a positive integer) +1. Figure 9 The key waveform diagram illustrates this behavior, showing the embedding when the load changes from 1% to 5% of the rated load at the point indicated by LC. Figure 8 The key waveform of the ACF converter in the control circuit shown in the figure causes the system to operate from 4 switching cycles per burst to 11 switching cycles per burst.

[0109] From this perspective, observing the described circuit, as an example, we provide the number of switching cycles n for each burst. sw The approximate relationship can be expressed as follows:

[0110]

[0111] As indicated above, C out It is the output capacitor. It is the average switching frequency during burst mode, and Qc is the charge delivered to the output per cycle, which depends on when Vc = (V th1 +V th2 The DC gain of the converter is 1 / 2, and Iout is the DC output current at the output node Vout. This is determined by the behavior of the converter operating in burst mode when the load increases.

[0112] Suppose that, starting with light load conditions where the converter operates in burst mode, as described earlier, time intervals are alternated, where the converter switches to its stop time interval, and the load is increased to a point where the control voltage Vc no longer drops below a first threshold Vth1. As a result, the converter operates continuously.

[0113] There are two possible scenarios: 1) The new load conditions cause the control voltage Vc to stabilize at a value greater than the third threshold Vth3; 2) The new load conditions cause the control voltage Vc to stabilize at a value between Vth2 and Vth3.

[0114] In the first case, when Vc > Vth3, the output of the second comparator CO2 goes high, causing the output of the OR gate OR1 to also go high, which resets the latch FF1. The burst mode flag BM goes low and is inverted. The value increases, causing the enable signal Q2EN to go high and interact with MOD-N. x The output of counter 812 is irrelevant. Therefore, when the converter runs continuously, clamp switch Q2 is driven as required in each cycle. When the burst mode flag is inverted... When the output goes high, the output of OR gate OR2 also goes high, and the two counters 811 and 812 are reset to zero and stop counting.

[0115] In the second case, the output of the second comparator CO2 remains low, and the converter 20 only operates when condition n is met. sw MOD N x During those cycles where =1, the high-side switch Q2 continues to operate until n. sw =n swmax When this happens, MOD-n swmax The output of counter 811 goes high, causing the output of OR gate OR1 to also go high. This resets latch FF1 and generates the same series of events as in the previous case, resulting in the high-side switch Q2 being driven as required in each cycle when the converter is running continuously.

[0116] The only significant difference between the two scenarios is the number of switching cycles, where the high-side Q2 starts every N from the last idle period. x It conducts once per cycle: In the first case, it is less than n. swmax In the second case, it equals n. swmax .

[0117] Figure 9 and Figure 10 The waveforms shown are: gate signals SQ1 and SQ2, midpoint voltage Vm, and output voltage V. out The control voltage Vc and clamping voltage Vclamp are referenced to the secondary winding. The clamping voltage Vclamp is multiplied by the ratio N2:N1 (which are the number of turns in the secondary winding to the primary winding), and it must be greater than the output voltage so that current flows when the high-side switch Q2 is turned on—obtained by simulating an exemplary ACF converter, the basic electrical specifications of which are provided in Table I below, also for the purpose of evaluating the benefits provided by the functionality described in this disclosure. For this purpose, a converter was also simulated, omitting this function (which also drives the high-side switch Q2 in each cycle during burst-mode operation) and using... Figure 4A The hybrid clamping shown in the figure, and furthermore, the high-side switch Q2 is not turned on at all during burst mode operation.

[0118] The input power of the converter and the voltage across the clamping capacitor Cc have been compared under low and high input voltages at light loads (1% of rated load).

[0119] The results of these simulations are shown in Tables II and III. The DC input voltage corresponding to the converter's minimum input voltage and the DC input voltage Vin corresponding to the nominal European supply voltage have been considered. dc .

[0120] Table 1

[0121] Key electrical specifications of an exemplary ACF converter

[0122]

[0123] Table 2

[0124] Converter input power [W]

[0125]

[0126] Table 3

[0127] DC voltage [V] across the clamping capacitor

[0128]

[0129] As indicated, the simulation results of the solutions described in the last column of Tables II and III refer to, for example, Figure 5 The architecture in which the controller is such Figure 8 The controller, in which the flyback converter uses a hybrid clamping circuit, such as Figure 4A The circuit 34 shown is shown.

[0130] These results confirm that the proposed solution is beneficial in terms of energy saving and controlling the voltage across the clamping capacitor.

[0131] The foregoing description represents only one possible implementation of the proposed solution. It is worth noting that the algorithm itself is suitable for design and implementation using automated synthesis tools.

[0132] In the description, the value N x and n swmax They are internally fixed. Alternatively, they can be user-programmable or determined by some self-calibration procedure (e.g., optimizing a lookup table of these numbers based on a determined converter operating condition diagram or making them dependent on the number of switching cycles n counted in a burst). sw (lookup table).

[0133] Turning on the high-side transistor during the first cycle of the burst is an exemplary embodiment of this method. However, in general, if the control voltage subsequently becomes greater than the second threshold Vth2, switching can be resumed, wherein the high-side clamping switch Q2 operates over multiple switching cycles n. sw >p is turned on during the p-th switching cycle of the burst, and if the number of cycles in the burst is n sw Exceeding the determined number of switching cycles N x For p-1, each determined number of switching cycles N x Starting from the p-th cycle in the burst. In other words, given the determined number of switching cycles N. x This method provides to turn on the high-side clamping switch Q2 in the p-th cycle of a burst, and then there are more than N in the burst. x +p-1 cycles, every N x Each cycle begins from the p-th cycle.

[0134] One possible embodiment may include providing logic circuitry that defines the minimum number of switching cycles Nmin to be performed in each burst, for example, Nmin = 3, and then, if in subsequent N... x After one cycle, the burst continues for a sufficient number of switching cycles, and the high-side clamp switch Q2 is turned on for a determined period p, where p can be 1, 2, or 3, meaning p <= Nmin. For example, if p = 2 and Nmin x=8, then the high-side clamping switch Q2 is turned on during the second, tenth, and eighteenth cycles, etc. More generally, at index m N x During the period of +p, at least m N x +p <n swmax .

[0135] Therefore, in general, the methods described herein may include, in a burst operation mode,

[0136] The control voltage Vc is compared to a set of thresholds, which includes at least a first threshold Vth1, a second threshold Vth2, and a third threshold Vth3, representing increments.

[0137] If, during normal operation mode S1, the control voltage Vc is less than the first threshold Vth1, the switching stops and the system enters idle state S2.

[0138] If the control voltage Vc subsequently becomes greater than the second threshold Vth2, then a series of switching cycles n are executed. sw The sudden event, in which the high-side clamping switch Q2 only occurs during multiple switching cycles n sw The multiple switching cycles n in a burst at a given position p in sw If a given period p is turned on, and if the number of periods n in the burst is counted starting from said given period p... sw Exceeding the determined number of switching cycles N x Then, whenever the determined number of switching cycles N x The determined number of switching cycles N x Then, in the first switching cycle that occurs, when counting begins from a given cycle p in the switching cycle of the burst, the high-side clamping switch Q2 is turned on;

[0139] If the control voltage Vc is greater than the third threshold Vth3 or the number of cycles in the plurality of switching cycles during a burst exceeds the determined maximum value n swmax Then it enters the normal operation mode S1.

[0140] exist Figure 11 The diagram shown here corresponds to the state diagram. Figure 6 The state diagram is shown in the figure, but the position of the high-side transistor on S3 and Q2 maintaining the burst state for a given period is indicated as the general position p, which is not necessarily the first period after Vc>Vth2. Therefore, the state diagram also includes the running state S1, the idle state S2, the burst state S3 with the high-side transistor on, and the burst state S4 with the high-side transistor off.

[0141] Transition T11 indicates that if Vc > Vth1, the state machine stays in the operating state S1, which corresponds to the operating flag RUN = 1, the converter is switching, and the burst mode flag BM = 0, and it operates in the normal mode of switching Q1 and Q2 in a complementary or non-complementary manner.

[0142] If Vc ≤ Vth1, a transition T12 from state S1 to the idle state S2 occurs. In the idle state S2, RUN = 0, BM = 1, and switching stops. The variable n sw is set to 1.

[0143] Due to a significant increase in the load, if Vc > Vth3, a reverse transition T21 from the idle state S2 to the operating state S1 occurs.

[0144] As indicated by transition T22, when Vc < Vth2, the idle state S2 is maintained. As mentioned, this causes the output voltage Vout to drop, thereby causing the control voltage Vc to rise.

[0145] Transition T23 indicates that the control voltage Vc rises above the second threshold voltage Vth2, Vc > Vth2, and n sw MOD N x = p, thus obtaining the burst state S3 where Q2 is conducting. RUN = 1, so the converter is switching, and BM = 1, and it operates in burst mode. The variable n indicating the number of switching cycles sw is incremented by 1. <统一格式,将 等类似的编号标签原样保留即可

[0146] If the control voltage Vc is greater than the second threshold Vth2 but the counted number of switching cycles n sw such that n sw MOD N x ≠ p, a transition T24 to the burst state S4 with high-side cutoff is executed; also in this state RUN = 1, so the converter is switching, and BM = 1, and it operates in burst mode. The variable n indicating the number of switching cycles sw is incremented by 1. This transition T24 can also be adjusted to a logic signal revealing that the input voltage of the converter is within the range of the United States or Japan.

[0147] Then, the operation process restarts from state S3. If Vc ≤ Vth1 and the counted number of switching cycles n sw is greater than the minimum number of switching cycles n swmin in the burst, a transition T32 back to the idle state S2 is executed.

[0148] If Vc > Vth3 or n sw = n swmax , n swmaxis the maximum number of switching periods determined in the burst, then the transition T31 to the operating state S1 is executed. If the load causes Vth1 < Vc < Vth3, as described above and as Figure 6 shown in x , this prevents the converter from continuously operating with the high-side switch Q2 conducting once every N

[0149] If n sw MOD N x ≠ p and n sw < n swmax , then the number of switching periods does not correspond to the determined number of periods N x at which the high-side transistor conducts once or a multiple of the number N x and it is less than the maximum number of periods n swmax , then the transition T34 from the burst state S3 with the high-side transistor Q2 conducting to the burst state S4 with the high-side transistor turned off is executed. This transition T34 can also be conditioned as a logic signal revealing that the input voltage of the converter is within the US or Japanese range.

[0150] As previously described, in state S4, RUN = 1, BM = 1, and the variable n sw indicating the number of switching periods is incremented by 1.

[0151] State S4 is maintained by the period transition T44, and then if n sw MOD N x ≠ p and n sw < n swmax , then the condition for the transition T34 / T24 is satisfied.

[0152] Conversely, if n sw MOD N x = p and n sw < n swmax , then the number of switching periods corresponds to the determined number of periods N x at which the high-side transistor conducts once or a multiple of the number N x and it is less than n swmax , and the transition from state S4 back to S3 is executed.

[0153] If Vc ≤ Vth1 and the counted number of switching periods n sw is greater than the minimum number of switching periods n swmin in the burst, then the transition T42 from state S4 to the idle state S2 is executed.

[0154] If Vc > Vth3 or n sw = n swmaxIf the state exits S4, the transition to running state S1 is executed via T41. Therefore, the described solution has several advantages over existing technical solutions.

[0155] The proposed solution operates the ACF converter in burst mode, minimizing the losses associated with driving the high-side switch Q2, while preventing the clamp voltage from drifting uncontrollably to a high position without an external resistor.

[0156] The proposed solution advantageously provides the voltage of the sensing reference ground, and therefore, compared to the solution for sensing the voltage of the reference high voltage line, it does not require additional pins or additional components.

[0157] Of course, without prejudice to the principles of this disclosure, the details of the construction and embodiments may vary considerably from the content described and illustrated herein by way of example only, without departing from the scope of this disclosure.

[0158] A method for operating an active clamp flyback converter in burst mode can be summarized (refer to the example in the accompanying drawings) as including a transformer (11) and switching circuits (Q1, Q2), wherein an active clamping circuit (24) determines a clamping voltage drop between an input terminal node (Vin) and a clamping node (CN) coupled between terminals of the primary winding of the transformer (11), the switching circuit including a high-side clamping switch (Q2) coupled between the clamping node (CN) and the other terminal of the primary winding, and a low-side switch (Q1) coupled between the other terminal of the primary winding of the transformer (11) and ground (GND), the high-side clamping switch (Q2) and the low-side switch (Q1) being driven to switch between an on state and an off state, particularly according to complementary or non-complementary control, the high-side clamping switch (Q2) and the low-side switch (Q1) being controlled by a controller (13; 80) based on the output voltage (V) of the converter by a control loop. outThe control voltage (Vc) generated by the error signal between the reference voltage and the control voltage is used for control. The method includes a normal operating mode (S1) and a burst operating mode. In the normal operating mode, the controller (13; 80) continuously performs switching of the switches (Q1, Q2). In the burst operating mode, the controller (13; 80) drives the high-side clamp switch (Q2) and the low-side switch (Q1) in bursts (S3, S4) of switching cycles separated by idle time intervals (S2). During the idle time interval (S2), the converter (20) does not perform the switching of the reference voltage. The switching of switches (Q1, Q2) includes: implementing a burst operation mode (S3, S4) by comparing a control voltage (Vc) with a set of thresholds, the set of thresholds including at least a first threshold (Vth1), a second threshold (Vth2), and a third threshold (Vth3) with incrementing values; and if, in normal operation mode (S1), the control voltage (Vc) is less than the first threshold (Vth1), switching is stopped and an idle state is entered (S2); if the control voltage (Vc) subsequently becomes greater than the second threshold (Vth2), then multiple switching cycles (n) are executed. sw The sudden occurrence of ), in which the high-side clamping switch (Q2) only occurs during multiple switching cycles (n sw The multiple switching cycles (n) in a burst at a given position (p) in ) sw In a given period (p), it is turned on, and if multiple switching periods (n) in a burst counting from said given period (p) are connected. sw The number of cycles in the sequence exceeds the predetermined number of switching cycles (N). x ), then whenever the predetermined number of switching cycles (N) x The predetermined number of switching cycles (N) is counted starting from a given cycle (p) in the first switching cycle that occurs after the burst. x When the control voltage (Vc) is greater than the third threshold (Vth3) or the number of cycles in the plurality of switching cycles in the burst exceeds the determined maximum value (n), the high-side clamping switch (Q2) is turned on. swmax If the signal is 0, then the system will enter normal operating mode (S1).

[0159] The method may include: depending on the input voltage value of the converter, particularly if the input voltage is equal to or lower than a given value, whenever the predetermined number of switching cycles (N) is reached. x Following the first cycle that occurs, the predetermined number of switching cycles (N) is counted starting from a given cycle (p) of the switching cycle in the burst. x When the high-side clamping switch (Q2) is activated.

[0160] The method may include performing a series of switching cycles (n) if the control voltage (Vc) subsequently becomes greater than a second threshold (Vth2).sw A burst of switching cycles, wherein the high-side clamping switch (Q2) is turned on only in the first cycle (p) of a switching cycle in a burst comprising multiple switching cycles, and if the number of cycles (n) counted from the first cycle (p) in the burst... sw Exceeding the predetermined number of switching cycles (N) x ), then whenever the predetermined number of switching cycles (N) x Following this, in the first switching cycle that occurs, the predetermined number of switching cycles (N) is counted starting from the first cycle (p) of the switching cycle in the burst. x When the high-side clamping switch (Q2) is activated, the high-side clamping switch is turned on.

[0161] The method may include executing a finite state machine, which includes a running state (S1), an idle state (S2), a burst state where the high-side switch is turned on (S3), and a burst state where the high-side switch is turned off (S4). In the running state (S1), if the control voltage (Vc) is greater than a first threshold (Vth1), the state machine remains (T11) in the running state (S1), where the converter is switching. If the control voltage (Vc) is less than or equal to the first threshold (Vth1), a transition (T12) occurs from state (S1) to the idle state (S2). In the idle state (S2), switching stops. In the idle state (S2), a counter counts the number of switching cycles (n). sw After counting, the high-side switch is turned on in the sudden state (S3) and the high-side switch is turned off in the sudden state (S4) can be reset; when the control voltage (Vc) is lower than the second threshold (Vth2), the idle state (T22) is maintained (S2); if the control voltage (Vc) is greater than the second threshold (Vth2) and the number of switching cycles (n) is greater than the second threshold (Vth2), the idle state (S2) is maintained. sw This makes dividing by the predetermined number of switching cycles (N) x If the remainder of the integer division of ) corresponds to the value of the given position (p), specifically corresponding to 1, then a transition to the burst state (S3) with the high-side switch turned on is executed (T23); if the control voltage (Vc) is greater than the third threshold (Vth3), then a reverse transition from the idle state S2 to the running state S1 occurs (T21). In the burst state, the high-side switch is turned on (S3), during which the converter switches the low-side switch (Q1) and the high-side switch (Q2). If the control voltage (Vc) is lower than or equal to the first threshold (Vth1), then a transition back to the idle state (S2) is executed (T32). If the control voltage (Vc) is greater than the third threshold (Vth3) or the number of cycles in the burst (n) sw ) equals the maximum number of switching cycles (n) determined during the burst. swmax Then, the transition to the running state (S1) (T31) is executed if the current switching cycle number (n) in the sudden event... swThis makes dividing by the predetermined number of switching cycles (N) x The remainder of an integer division of is different from the value at the given position, in particular not equal to 1, and it is less than the maximum number of cycles (n). swmax Then, a transition (T34) is performed from a burst state where the high-side switch is turned on (S3) to a burst state where the high-side transistor is turned off (S4). In the burst state where the high-side switch is turned off (S4), the converter only switches the low-side switch (Q1) during this period. Then, if the number of switching cycles currently counted in the burst (n) is... sw This makes dividing by the predetermined number of switching cycles (N) x The remainder of an integer division of ) is different from the value at the given position (p), in particular not equal to 1, and it is below the maximum number of cycles (n). swmax If the high-side switch is cut off (S4) for a sudden state (T44), then the counted number of switching cycles (n) will remain unchanged. sw This makes dividing by the predetermined number of switching cycles (N) x The remainder of an integer division of ) corresponds to the value at the given position (p), specifically to 1, and it is less than the maximum number of cycles (n) in the burst. swmax If the control voltage (Vc) is lower than or equal to the first threshold (Vth1), then the transition to the idle state (S2) is executed (T43); if the control voltage (Vc) is greater than the third threshold (Vth3) or the counted number of cycles n, then the transition to the idle state (S2) is executed (T42). sw Equal to the determined maximum number of switching cycles (n) swmax If ), then the transition to running state S1 (T41) will be executed.

[0162] An active clamp flyback converter can be summarized as including a transformer (11) and a switching circuit (Q1, Q2) driven by a controller (13), wherein an active clamping circuit (24) determines a clamping voltage drop between an input terminal node (Vin) and a clamping node (CN) coupled between the terminals of the primary winding of the transformer (11), the switching circuit including a high-side clamping switch (Q2) coupled between the clamping node (CN) and the other terminal of the primary winding, and a low-side switch (Q1) coupled between the other terminal of the primary winding of the transformer (11) and ground (GND), the high-side clamping switch (Q2) and the low-side transistor (Q1) being driven to switch between on and off states, particularly according to complementary or non-complementary control, the high-side clamping transistor (Q2) and the low-side transistor (Q1) being controlled by the controller (13; 80) based on the output voltage (V) of the converter by the control loop. outThe controller (13, 80) is controlled by a control voltage (Vc) generated from the error signal between the reference voltage and the reference voltage. The controller (13, 80) is configured to operate according to a mode including a normal operating mode (S1) and a burst operating mode. In the normal operating mode, the controller (13; 80) continuously performs switching of the switches (Q1, Q2). In the burst operating mode, the controller (13; 80) drives the high-side clamp switch (Q2) and the low-side switch (Q1) in bursts (S3, S4) of switching cycles separated by idle time intervals (S2). The converter (20) does not switch during the idle time interval (S2). The controller (80) is configured to operate in the burst operating modes (S3, S4).

[0163] The controller (80) may include a first comparator (CO1) with hysteresis, configured to compare a control voltage (Vc) with a first (Vth1) threshold and a second (Vth2) threshold to determine a run mode logic signal (RUN), which enables a PWM generator (801) to operate. The PWM generator (801) is configured to generate a PWM low-side signal (PWM1) and a PWM high-side signal (PWM2) that are at least not simultaneously at a high logic level, and from which signals (SQ1) commanding the low-side switch (Q1) and the high-side switch (Q2) can be obtained. The circuit (81) is configured to generate an enable signal (Q2EN) for a command signal (SQ2) of a high-side switch (Q2) based on a running mode signal (RUN), a control voltage (Vc), and a PWM low-side signal (PWM1) received as input. The circuit includes a second comparator (CO2) configured to compare the control voltage (Vc) with a third (Vth3) threshold. When the control voltage (Vc) is greater than the third (Vth3) threshold, the output signal of the second comparator enables (Q2EN) the command signal (SQ2) of the high-side switch (Q2).

[0164] The circuit (81) may include a first counter (811) and a second counter (812) that receive a first PWM signal (PWM1) as input. The first counter (811) is configured to count (n) its PWM cycles for the first PWM signal (PWM1). sw ) reaches the maximum number of cycles (n) swmax When the output logic state of the high-side switch (Q2) is changed to the value of the command signal (SQ2) for enabling (Q2EN) the high-side switch (Q2), the second counter (812) is configured to maintain its output in the logic state of the command signal (SQ2) for enabling (Q2EN) the high-side switch (Q2) during a given period (p) of the burst (particularly the first period), and after said given period, until its count (n) of the PWM period of the first PWM signal (PWM1).sw The predetermined number of switching cycles (N) has been reached. x When +p-1), its output logic state is changed.

[0165] The switch can be a power MOSFET transistor switch.

[0166] In one embodiment, a method includes: comparing a control signal for an active clamp flyback converter with a plurality of three or more thresholds; counting the number of consecutive switching cycles during which the clamp switch of the active flyback converter remains off; and selectively switching the active clamp flyback converter between a plurality of operating states by controlling the power switch and the clamp switch of the active clamp flyback converter. The multiple operating states include: an operating state of one or more consecutive switching cycles of the active flyback converter, each switching cycle during the operating state including sequentially turning on the power switch, turning off the power switch, turning on the clamp switch, and turning off the clamp switch; an idle state of one or more consecutive switching cycles of the active flyback converter, during which the power switch and the clamp switch are off; a first burst state of one or more sets of consecutive switching cycles, each set of consecutive switching cycles of the first burst state including a determined number of switching cycles of the power switch being turned on and off and the clamp switch being off; and a switching cycle in a position determined in a set of switching cycles including sequentially turning on the power switch, turning off the power switch, turning on the clamp switch, and turning off the clamp switch; and a second burst state of one or more sets of consecutive switching cycles of the operation, during which the power switch is turned on and off and the clamp switch is off. Selective switching is based on comparisons of control signals with multiple three or more thresholds and a count of the number of consecutive switching cycles during which the clamp switch remains off.

[0167] In one embodiment, the control signal is a control voltage, and a plurality of three or more thresholds include a first threshold voltage, a second threshold voltage with an amplitude greater than the first threshold voltage, and a third threshold voltage with an amplitude greater than the second threshold voltage. In another embodiment, the method includes: in an idle state of operation, transitioning to an operating state in response to a control voltage greater than the third threshold voltage; in a first burst state of operation, transitioning to an operating state in response to the following condition: the control voltage is greater than the third threshold voltage; or a count equals a maximum threshold number; in a second burst state of operation, transitioning to an operating state in response to the following condition: the control voltage is greater than the third threshold voltage; or a count equals a maximum threshold number. In yet another embodiment, the method includes: in an operating state of operation, transitioning to an idle state of operation in response to a control voltage less than or equal to the first threshold voltage; in a first burst state of operation, transitioning to an idle state of operation in response to a control voltage less than or equal to the first threshold voltage; in a second burst state of operation, transitioning to an idle state of operation in response to a control voltage less than or equal to the first threshold voltage.

[0168] In one embodiment, the method includes: in an idle state of operation, transitioning to a first burst state of operation in response to a control voltage greater than a second threshold voltage; in the first burst state of operation, transitioning to a second burst state of operation in response to the following conditions: a count modulo a determined number of cycles is not equal to the number representing a determined position; and the count is less than a maximum threshold; and in the second burst state of operation, transitioning to the first burst state of operation in response to the following conditions: a count modulo a determined number of cycles is equal to the number representing a determined position; and the count is less than a maximum threshold number. In another embodiment, the method includes: in the first burst state of operation, transitioning to an idle state of operation in response to a control voltage less than or equal to a first threshold voltage; in the first burst state of operation, transitioning to an operating state of operation in response to the following conditions: a control voltage greater than a third threshold voltage; or a count equal to a maximum threshold number; in the second burst state of operation, transitioning to an idle state of operation in response to a control voltage less than or equal to a first threshold voltage; in the second burst state of operation, transitioning to an operating state of operation in response to the following conditions: a control voltage greater than a third threshold voltage; or a count equal to a maximum threshold number.

[0169] In this embodiment, the determined position is the first position in the group of consecutive switching cycles of the first sudden state.

[0170] In one embodiment, the method includes: transitioning to an idle state of operation in response to a control voltage being less than or equal to a first threshold voltage during operation; transitioning to an idle state of operation in response to a first burst state of operation in response to the following conditions: the control voltage is less than or equal to the first threshold voltage; and the count is greater than a minimum threshold count during operation; and transitioning to an idle state of operation in response to a second burst state of operation in response to the following conditions: the control voltage is less than or equal to the first threshold voltage; and the count is greater than a minimum threshold count during operation. In another embodiment, the method includes: transitioning to a first burst state of operation in response to the following conditions during an idle state of operation: the control voltage is greater than a second threshold voltage; and the count modulo a determined number of cycles is equal to the number representing a determined position; transitioning to a second burst state of operation in response to the following conditions during the first burst state of operation: the count modulo a determined number of cycles is not equal to the number representing a determined position; and the count is less than a maximum threshold; and transitioning to the first burst state of operation in response to the following conditions during the second burst state of operation: the count modulo a determined number of cycles is equal to the number representing a determined position; and the count is less than a maximum threshold count during operation. In an embodiment, the method includes: in a first burst state of operation, transitioning to an idle state of operation in response to the following conditions: a control voltage is less than or equal to a first threshold voltage; and a count is greater than a minimum threshold count; in the first burst state of operation, transitioning to an operating state of operation in response to the following conditions: a control voltage is greater than a third threshold voltage; or a count is equal to a maximum threshold count; in a second burst state of operation, transitioning to an idle state of operation in response to the following conditions: a control voltage is less than or equal to a first threshold voltage; and a count is greater than a minimum threshold count; in the second burst state of operation, transitioning to an operating state of operation in response to the following conditions: a control voltage is greater than a third threshold voltage; or a count is equal to a maximum threshold count. In an embodiment, the method includes: in the idle state of operation, transitioning to a second burst state of operation in response to the following conditions: a control voltage is greater than a second threshold voltage; and a count modulo a determined number is not equal to the number representing the determined position. In an embodiment, in the operating state of operation, the power switch and the clamping switch operate according to a non-complementary control scheme.

[0171] In one embodiment, a system includes: an active clamp flyback converter having a transformer, a power switch, and a clamping switch; and control circuitry coupled to the active clamp flyback converter, wherein the control circuitry, in operation, compares a control voltage of the active clamp flyback converter with a first voltage threshold, a second voltage threshold having an amplitude greater than the first voltage threshold, and a third voltage threshold having an amplitude greater than the second voltage threshold; counts the number of consecutive switching cycles during which the clamping switch remains off; and selectively switches the active clamp flyback converter between multiple operating states. Multiple operating states include: an operating state of one or more consecutive switching cycles of an active flyback converter, each switching cycle during the operating state including sequentially turning on a power switch, turning off a power switch, turning on a clamping switch, and turning off a clamping switch; an idle state of one or more consecutive switching cycles of an active flyback converter, during which the power switch and clamping switch are off; a first burst state of one or more sets of consecutive switching cycles of operation, each set of consecutive switching cycles of the first burst state including: a determined number of switching cycles in which the power switch is turned on and off and the clamping switch is off; and a switching cycle in a position determined in a set of switching cycles including sequentially turning on a power switch, turning off a power switch, turning on a clamping switch, and turning off a clamping switch; and a second burst state of one or more sets of consecutive switching cycles of operation, during which the power switch is turned on and off and the clamping switch is off, wherein the selective switching is based on a comparison of a control signal with a voltage threshold and a count of the number of consecutive switching cycles during which the clamping switch remains off.

[0172] In one embodiment, the control circuit includes: a first comparator with hysteresis configured to compare a control voltage with a first threshold and a second threshold to determine an operating mode logic signal, the operating mode logic signal enabling a pulse width modulation (PWM) signal generator configured to generate a PWM power switch signal and a PWM clamp switch signal, and to obtain a command signal for the power switch and the clamp switch from the operating mode logic signal; and a burst control circuit configured to generate an enable signal for a command signal of the clamp switch based on the operating mode signal, the control voltage, and the PWM clamp switch signal received as input. The burst control circuit includes a second comparator configured to compare the control voltage with a third threshold, the output signal of which enables the command signal of the clamp switch when the control voltage is greater than the third threshold. In another embodiment, the burst control circuit includes a first counter and a second counter receiving the PWM power switch signal as input, the first counter configured to change its output logic state to the value of enabling the command signal of the clamp switch when its count of PWM cycles of the first PWM signal reaches a maximum threshold number of cycles, and the second counter configured to enable the command signal of the clamp switch during the determined burst period. In this embodiment, the power switch and the clamping switch are power MOSFET transistor switches.

[0173] In one embodiment, a device includes: one or more comparators that, in operation, compare a control voltage signal of an active clamp flyback converter with a first voltage threshold, a second voltage threshold, and a third voltage threshold, wherein the magnitude of the second voltage threshold is greater than the magnitude of the first voltage threshold and the magnitude of the third voltage threshold is greater than the magnitude of the second voltage threshold; and logic circuitry coupled to the one or more comparators, wherein, in operation, the logic circuitry selectively transitions between a plurality of operating states, the plurality of operating states including: an operating state of one or more consecutive switching cycles of operation, each switching cycle during the operating state of operation including sequentially generating signals to turn on a power switch, turn off a power switch, turn on a clamp switch, and turn off a clamp switch; and an idle state of operation of the one or more consecutive switching cycles of the active flyback converter. The system comprises: an idle state, during which a signal is generated to maintain the off state of the power switch and the clamping switch; a first burst state of operation for one or more sets of continuous switching cycles, each set of continuous switching cycles comprising: a determined number of switching cycles during which a signal is generated to turn the power switch on and off and maintain the off state of the clamping switch; and a switching cycle at a position determined in a set of switching cycles in which signals are generated sequentially to turn the power switch on, turn off the power switch, turn on the clamping switch, and turn off the clamping switch; and a second burst state of operation for one or more sets of continuous switching cycles, during which a signal is generated to turn the power switch on and off and maintain the off state of the clamping switch; and counting the number of continuous switching cycles during which the clamping switch is maintained in the off state. Selective switching is based on a comparison of a control voltage signal with a voltage threshold and the counting of the number of continuous switching cycles, maintaining the off state of the clamping switch during the continuous switching cycles.

[0174] In one embodiment, in the idle state of operation, the logic circuit transitions to the running state in response to a control voltage greater than a third threshold voltage; in the first burst state of operation, the logic circuit transitions to the running state of operation in response to the following conditions: the control voltage is greater than the third threshold voltage; or the count equals the maximum threshold number; and in the second burst state of operation, the logic circuit transitions to the running state of operation in response to the following conditions: the control voltage is greater than the third threshold voltage; or the count equals the maximum threshold number. In another embodiment, in the running state of operation, the logic circuit transitions to the idle state of operation in response to a control voltage less than or equal to a first threshold voltage; in the first burst state of operation, the logic circuit transitions to the idle state of operation in response to a control voltage less than or equal to the first threshold voltage; and in the second burst state of operation, the logic circuit transitions to the idle state of operation in response to a control voltage less than or equal to the first threshold voltage. In an embodiment, during an idle state of operation, the logic circuit transitions to a first burst state of operation in response to a control voltage greater than a second threshold voltage; in the first burst state of operation, the logic circuit transitions to a second burst state of operation in response to the following conditions: the count modulo a determined number of cycles is not equal to the number representing the determined positions; and the count is less than a maximum threshold; and in the second burst state of operation, the logic circuit transitions to the first burst state of operation in response to the following conditions: the count modulo a determined number of cycles is equal to the number representing the determined positions; and the count is less than a maximum threshold number. In an embodiment, the logic circuit includes a finite state machine that controls the transitions between multiple operating states during operation.

[0175] In an embodiment, the content of a non-transitory computer-readable medium enables control circuitry to control the operation of an active flyback converter device. This control includes selectively switching the active clamp flyback converter between multiple operating states by controlling a power switch and a clamp switch of the active clamp flyback converter. These multiple operating states include: an operating state of one or more consecutive switching cycles of the active flyback converter, each switching cycle during the operating state including sequentially turning on the power switch, turning off the power switch, turning on the clamp switch, and turning off the clamp switch; an idle state of one or more consecutive switching cycles of the active flyback converter, during which the power switch and the clamp switch are turned off; and a first burst state of one or more sets of consecutive switching cycles of operation, each set of consecutive switching cycles of the first burst state including... The system comprises: determining a number of switching cycles during which a power switch is turned on and off and a clamping switch is turned off; and a switching cycle at a position determined in a set of switching cycles including sequentially turning on a power switch, turning off a power switch, turning on a clamping switch, and turning off a clamping switch; and a second burst state of operation of one or more sets of consecutive switching cycles during which the power switch is turned on and off and the clamping switch is turned off; comparing a control signal for an active clamp flyback converter with a plurality of three or more thresholds; and counting the number of consecutive switching cycles during which the clamping switch remains off, wherein selective switching is based on comparisons of the control signal with a plurality of three or more thresholds and counting the number of consecutive switching cycles during which the clamping switch remains off. In an embodiment, the control signal is a control voltage, and the plurality of three or more thresholds include a first threshold voltage, a second threshold voltage with an amplitude greater than the amplitude of the first threshold voltage, and a third threshold voltage with an amplitude greater than the amplitude of the second threshold voltage. In an embodiment, the content includes instructions executed by the control circuitry.

[0176] Some embodiments may take the form of or include a computer program product. For example, according to an embodiment, a computer-readable medium is provided that includes a computer program adapted to perform one or more of the methods or functions described above. The medium may be a physical storage medium, such as, for example, a read-only memory (ROM) chip, or a disk, such as a digital multifunction disc (DVD-ROM), a compact disc (CD-ROM), a hard disk, a memory, a network, or a portable media article to be read by a suitable drive or via a suitable connection, including encoding with one or more barcodes or other relevant codes stored on one or more such computer-readable media and readable by a suitable reader device.

[0177] Furthermore, in some embodiments, some or all of the methods and / or functionality may be implemented or provided in other ways, such as at least in part in firmware and / or hardware, including but not limited to one or more application-specific integrated circuits (ASICs), digital signal processors, discrete circuits, logic gates, standard integrated circuits, controllers (e.g., by executing appropriate instructions, and including microcontrollers and / or embedded controllers), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and devices employing RFID technology and various combinations thereof.

[0178] The various embodiments described above can be combined to provide further embodiments. If desired, aspects of the embodiments can be modified to employ the concepts of various patents, applications, and publications to provide even more advanced embodiments.

[0179] These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of the equivalents enjoyed by the claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A method for operating an active clamp flyback converter, comprising: The control signal of the active clamp flyback converter is compared with multiple three or more thresholds; The number of consecutive switching cycles is counted, during which the clamping switch of the active flyback converter remains off; as well as The active clamp flyback converter can be selectively switched between multiple operating states by controlling the power switch and the clamp switch, the multiple operating states including: The operating state of one or more consecutive switching cycles of the active flyback converter, each switching cycle during the operating state of the operation includes sequentially turning on the power switch, turning off the power switch, turning on the clamping switch, and turning off the clamping switch; The active flyback converter operates in an idle state during one or more consecutive switching cycles, during which the power switch and the clamping switch are turned off. A first burst state of one or more sets of consecutive switching cycles, wherein each set of consecutive switching cycles in the first burst state includes: A defined number of switching cycles, during which the power switch is turned on and off and the clamping switch is turned off; and The switching cycle in the position determined by the set of switching cycles including sequentially turning on the power switch, turning off the power switch, turning on the clamping switch, and turning off the clamping switch; and A second burst state of operation involving one or more consecutive switching cycles, during which the power switch is turned on and off and the clamping switch is turned off. The selective switching is based on a comparison of the control signal with the plurality of three or more thresholds and a count of consecutive switching cycles during which the clamp switch remains off.

2. The method of claim 1, wherein the control signal is a control voltage, and the plurality of three or more thresholds include a first threshold voltage, a second threshold voltage with an amplitude greater than that of the first threshold voltage, and a third threshold voltage with an amplitude greater than that of the second threshold voltage.

3. The method according to claim 2, comprising: In the idle state of operation, the system transitions to the operating state in response to the control voltage being greater than the third threshold voltage; In the first sudden state of operation, the operation transitions to the operating state in response to the following conditions: The control voltage is greater than the third threshold voltage; or The count is equal to the maximum threshold number; and In the second burst state of operation, the operation transitions to the operating state in response to the following conditions: The control voltage is greater than the third threshold voltage; or The count is equal to the maximum threshold number.

4. The method according to claim 2, comprising: In the operating state, the system transitions to the idle state in response to the control voltage being less than or equal to the first threshold voltage. In the first burst state of operation, the system transitions to the idle state of operation in response to the control voltage being less than or equal to the first threshold voltage. as well as In the second burst state of operation, the system transitions to the idle state of operation in response to the control voltage being less than or equal to the first threshold voltage.

5. The method according to claim 2, comprising: In the idle state of operation, the system transitions to the first burst state of operation in response to the control voltage being greater than the second threshold voltage; In the first burst state of operation, the operation transitions to the second burst state in response to the following conditions: The count modulo the determined number of periods is not equal to the number representing the determined positions; and The count is less than the maximum threshold number; and In the second burst state of operation, the operation transitions to the first burst state in response to the following conditions: The count modulo the determined number of periods is equal to the number representing the determined positions; and The count is less than the maximum threshold number.

6. The method according to claim 5, comprising: In the first burst state of operation, the system transitions to the idle state of operation in response to the control voltage being less than or equal to the first threshold voltage. In the first sudden state of operation, the operation transitions to the operating state in response to the following conditions: The control voltage is greater than the third threshold voltage; or The count is equal to the maximum threshold number; In the second burst state of operation, the system transitions to the idle state of operation in response to the control voltage being less than or equal to the first threshold voltage. In the second burst state of operation, the operation transitions to the operating state in response to the following conditions: The control voltage is greater than the third threshold voltage; or The count is equal to the maximum threshold number.

7. The method of claim 1, wherein the determined position is a first position in the set of consecutive switching cycles of the first sudden state.

8. The method according to claim 2, comprising: In the operating state, the system transitions to the idle state in response to the control voltage being less than or equal to the first threshold voltage. In the first burst state of operation, the operation transitions to the idle state in response to the following conditions: The control voltage is less than or equal to the first threshold voltage; and The count is greater than the minimum threshold count; and In the second burst state of operation, the operation transitions to the idle state in response to the following conditions: The control voltage is less than or equal to the first threshold voltage; and The count is greater than the minimum threshold count.

9. The method according to claim 2, comprising: During the idle state of operation, the operation transitions to the first burst state in response to the following conditions: The control voltage is greater than the second threshold voltage; and The count modulo the determined number of cycles is equal to the number representing the determined position; In the first burst state of operation, the operation transitions to the second burst state in response to the following conditions: The count modulo the determined number of periods is not equal to the number representing the determined positions; and The count is less than the maximum threshold number; and In the second burst state of operation, the operation transitions to the first burst state in response to the following conditions: The count modulo the determined number of periods is equal to the number representing the determined positions; and The count is less than the maximum threshold number.

10. The method of claim 9, comprising: In the first burst state of operation, the operation transitions to the idle state in response to the following conditions: The control voltage is less than or equal to the first threshold voltage; and The count is greater than the minimum threshold count; In the first sudden state of operation, the operation transitions to the operating state in response to the following conditions: The control voltage is greater than the third threshold voltage; or The count is equal to the maximum threshold number; In the second burst state of operation, the operation transitions to the idle state in response to the following conditions: The control voltage is less than or equal to the first threshold voltage; and The count is greater than the minimum threshold count; In the second burst state of operation, the operation transitions to the operating state in response to the following conditions: The control voltage is greater than the third threshold voltage; or The count is equal to the maximum threshold number.

11. The method of claim 10, comprising: During the idle state of operation, the operation transitions to the second burst state in response to the following conditions: The control voltage is greater than the second threshold voltage; and The count modulo a certain number is not equal to the number representing the determined position.

12. The method of claim 2, wherein, in the operating state, the power switch and the clamping switch operate according to a non-complementary control scheme.

13. A system for operating an active clamp flyback converter, comprising: An active clamp flyback converter with a transformer, power switch and clamping switch; as well as A control circuit, coupled to the active clamp flyback converter, wherein the control circuit, in operation: The control voltage of the active clamp flyback converter is compared with a first threshold voltage, a second threshold voltage with an amplitude greater than that of the first threshold voltage, and a third threshold voltage with an amplitude greater than that of the second threshold voltage. The number of consecutive switching cycles is counted, during which the clamp switch remains off; as well as The active clamp flyback converter selectively transitions between multiple operating states, including: The operating state of one or more consecutive switching cycles of the active flyback converter, each switching cycle during the operating state of the operation includes sequentially turning on the power switch, turning off the power switch, turning on the clamping switch, and turning off the clamping switch; The active flyback converter operates in an idle state during one or more consecutive switching cycles, during which the power switch and the clamping switch are turned off. A first burst state of one or more sets of consecutive switching cycles, wherein each set of consecutive switching cycles in the first burst state includes: A defined number of switching cycles, during which the power switch is turned on and off and the clamping switch is turned off; and The switching cycle in the position determined by the set of switching cycles including sequentially turning on the power switch, turning off the power switch, turning on the clamping switch, and turning off the clamping switch; and A second burst state of operation of one or more sets of consecutive switching cycles, during which the power switch is turned on and off and the clamping switch is turned off, wherein the selective switching is based on a comparison of the control signal with a threshold voltage and a count of the number of consecutive switching cycles during which the clamping switch remains off.

14. The system of claim 13, wherein the control circuit comprises: A first comparator with hysteresis is configured to compare the control voltage with a first threshold voltage and a second threshold voltage to determine an operating mode logic signal that enables a pulse width modulation (PWM) signal generator to operate. The PWM signal generator is configured to generate a PWM power switch signal and a PWM clamp switch signal, and to obtain command signals from the operating mode logic signal that command the power switch and the clamp switch. A burst control circuit is configured to generate an enable signal for the command signal of the clamp switch based on the operating mode signal, the control voltage, and the PWM clamp switch signal received as input. The burst control circuit includes a second comparator configured to compare the control voltage with the third threshold voltage, wherein when the control voltage is greater than the third threshold voltage, the output signal of the second comparator enables the command signal of the clamp switch.

15. The system of claim 14, wherein the burst control circuit includes a first counter and a second counter that receive the PWM power switching signal as input. The first counter is configured to change its output logic state to the value of the command signal that enables the clamp switch when it counts the PWM cycles of the first PWM signal to a maximum threshold number of cycles. The second counter is configured to enable the command signal of the clamp switch during the determined burst period.

16. The system of claim 13, wherein the power switch and the clamping switch are power MOSFET transistor switches.

17. An apparatus for operating an active clamp flyback converter, comprising: One or more comparators, which in operation compare a control voltage signal of an active clamp flyback converter with a first threshold voltage, a second threshold voltage, and a third threshold voltage, wherein the amplitude of the second threshold voltage is greater than the amplitude of the first threshold voltage and the amplitude of the third threshold voltage is greater than the amplitude of the second threshold voltage; as well as A logic circuit coupled to the one or more comparators, wherein the logic circuit, in operation: Selective transitions between multiple operating states, including: An operating state of one or more consecutive switching cycles, wherein each switching cycle during the operating state includes sequentially generating signals to turn on a power switch, turn off the power switch, turn on a clamping switch, and turn off the clamping switch; The idle state of one or more consecutive switching cycles of the active flyback converter, during which a signal is generated to maintain the off state of the power switch and the clamping switch; A first burst state of one or more sets of consecutive switching cycles, wherein each set of consecutive switching cycles in the first burst state includes: A predetermined number of switching cycles are defined, during which signals are generated to turn the power switch on and off and to maintain the clamping switch in the off state; and The switching cycle in the set of switching cycles that sequentially generate signals to turn on the power switch, turn off the power switch, turn on the clamp switch, and turn off the clamp switch; and A second burst state of operation for one or more consecutive switching cycles, during which signals are generated to turn the power switch on and off and maintain the clamping switch in the off state; and The number of consecutive switching cycles is counted, during which the clamp switch is maintained in the off state, wherein the selective switching is based on a comparison of the control voltage signal with a threshold voltage and the counting of the consecutive switching cycles, during which the clamp switch is maintained in the off state.

18. The apparatus according to claim 17, wherein: In the idle state of operation, the logic circuit transitions to the operating state in response to the control voltage being greater than the third threshold voltage; In the first burst state of operation, the logic circuit transitions to the operating state in response to the following conditions: The control voltage is greater than the third threshold voltage; or The count is equal to the maximum threshold number; and In the second burst state of operation, the logic circuit transitions to the operating state in response to the following conditions: The control voltage is greater than the third threshold voltage; or The count is equal to the maximum threshold number.

19. The apparatus according to claim 17, wherein: In the operating state, the logic circuit transitions to the idle state in response to the control voltage being less than or equal to the first threshold voltage. In the first burst state of operation, the logic circuit transitions to the idle state of operation in response to the control voltage being less than or equal to the first threshold voltage; as well as In the second burst state of operation, the logic circuit transitions to the idle state of operation in response to the control voltage being less than or equal to the first threshold voltage.

20. The apparatus according to claim 17, wherein: In the idle state of operation, the logic circuit transitions to the first burst state of operation in response to the control voltage being greater than the second threshold voltage; In the first burst state of operation, the logic circuit transitions to the second burst state of operation in response to the following condition: The count modulo the determined number of periods is not equal to the number representing the determined positions; and The count is less than the maximum threshold number; and In the second burst state of operation, the logic circuit transitions to the first burst state of operation in response to the following condition: The count modulo the determined number of periods is equal to the number representing the determined positions; and The count is less than the maximum threshold number.

21. The device of claim 17, wherein the logic circuitry includes a finite state machine that controls transitions between the plurality of operating states during operation.

22. A non-transitory computer-readable medium having content that enables control circuitry to control the operation of an active flyback converter device, the control comprising: The active clamp flyback converter can be selectively switched between multiple operating states by controlling its power switch and clamp switch, the multiple operating states including: The operating state of one or more consecutive switching cycles of the active flyback converter, each switching cycle during the operating state of the operation includes sequentially turning on the power switch, turning off the power switch, turning on the clamping switch, and turning off the clamping switch; The active flyback converter operates in an idle state during one or more consecutive switching cycles, during which the power switch and the clamping switch are turned off. A first burst state of one or more sets of consecutive switching cycles, wherein each set of consecutive switching cycles in the first burst state includes: A defined number of switching cycles, during which the power switch is turned on and off and the clamping switch is turned off; and The switching cycle at the position determined in the set of switching cycles including sequentially turning on the power switch, turning off the power switch, turning on the clamping switch, and turning off the clamping switch; and A second burst state of operation of one or more sets of consecutive switching cycles, during which the power switch is turned on and off and the clamping switch is turned off; The control signal of the active clamp flyback converter is compared with multiple three or more thresholds; and The number of consecutive switching cycles is counted, during which the clamp switch remains off, wherein the selective switching is based on a comparison of the control signal with the plurality of three or more thresholds and the count of the consecutive switching cycles, during which the clamp switch remains off.

23. The non-transitory computer-readable medium of claim 22, wherein the control signal is a control voltage, and the plurality of three or more thresholds include a first threshold voltage, a second threshold voltage with an amplitude greater than that of the first threshold voltage, and a third threshold voltage with an amplitude greater than that of the second threshold voltage.

24. The non-transitory computer-readable medium of claim 22, wherein the content includes instructions executed by the control circuitry.

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