A low-segment parasitic correction method for SAR ADC segmented structure

Abstract

The present invention discloses a method for correcting low-segment parasitic capacitance in a segmented SAR ADC. This correction method adds an additional reference source to a traditional segmented SAR ADC to eliminate the effects of parasitic capacitance in the low-segment array after bridge capacitor segmentation. This method increases the number of bits of the low-segment capacitance, reduces the capacitance per unit capacitor, and ultimately reduces the total capacitance of the capacitor array to reduce power consumption. After power is applied, this correction method automatically performs corrections based on digital logic. First, the comparator offset is measured to avoid the impact of comparator offset on the correction result. Subsequently, the output voltage of the adjustable reference source is approximated to eliminate the effects of parasitic capacitance. The result is stored in a register, and the correction code in the register is read during normal conversion, thereby eliminating the effects of parasitic capacitance. The present invention can be widely applied to SAR ADC designs to reduce capacitor area and power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog-to-digital converters, and in particular relates to a low-segment parasitic correction method for a SAR ADC segmented structure. Background Art

[0002] An analog-to-digital converter (ADC) is a core module that converts continuous analog signals into discrete digital signals in the digital domain. It is widely used in industrial control, wireless communications, instrumentation, and other fields. ADCs primarily have four architectures: flash, pipeline, sigma-delta, and successive approximation register (SAR). Each has its own advantages and applications.

[0003] Flash ADCs offer a simple structure and fast conversion speed, but they consume high power, and their circuit size grows exponentially with increasing precision. Therefore, they are suitable for high-speed, low-precision applications. Pipeline ADCs, derived from flash ADCs, have each stage equivalent to a 1- to 2-bit ADC. The conversion residual is amplified and passed to the next stage, with each stage operating in parallel in a pipelined fashion. This results in high speed, and the circuit size grows linearly with increasing precision. However, due to non-ideal factors such as amplifier gain error and comparator offset, high-precision applications require correction and consume high power. Furthermore, the pipeline approach introduces latency, making it difficult to obtain instantaneous conversion results. Sigma-Delta ADCs achieve higher precision through oversampling and noise shaping, but this comes at the expense of speed. Sigma-Delta ADCs offer advantages such as high resolution, low noise, and low power consumption, and are generally used in low-speed, high-precision applications. SAR ADCs offer a certain level of speed and accuracy. Furthermore, thanks to their miniaturization, their power consumption and area can be optimized simultaneously with process advancements, making them widely used in high-precision, low-power, and small-size applications. Currently, high-precision SAR ADCs can reach 18 bits, while low-power SAR ADCs can consume as little as nW. High-speed SAR ADCs can achieve sampling rates exceeding GHz. These advantages make them one of the most widely used ADC architectures. Low-power SAR ADCs are widely used in wearable devices, battery-powered equipment, biomedical equipment, and other fields.

[0004] like Figure 1As shown in the figure, the SAR ADC includes the following parts: a sample and hold circuit, a DAC array, SAR logic, a comparator, and a reference voltage VREF and a driver. In the sampling stage, the sample and hold circuit samples the analog input voltage, and then the switch disconnects and enters the hold stage for quantization and conversion; in practical applications, the two upper plates VINP and VINN of the capacitor array are compared through a comparator. If the voltage value VINP > VINN, the encoding of the current bit is 1; conversely, if VINP < VINN, the encoding of the current bit is 0; then the SAR logic controls the movement to the next bit and repeats the above operations until the comparison of the last bit is completed to obtain the entire A / D conversion encoding. The core idea of the working principle of the SAR ADC is the dichotomy method, and each time the change in the output voltage of the DAC is 1 / 2 n , gradually approaching the analog input voltage to achieve A / D conversion.

[0005] However, since the above comparison method requires the relationship between the high-order capacitor and the low-order capacitor to be an integer multiple of 2, the capacitance size will increase exponentially. To solve this problem, the capacitance ratio can be scaled by inserting bridge capacitors to reduce the area and drive of the capacitor array. However, due to the inevitable parasitic capacitance to the ground during the production process, the low-order capacitor array after the bridge capacitor is segmented will be affected by this factor, which in turn affects the linearity of the SAR ADC; since the more bits of the low-order capacitor, the more obvious the influence of the parasitic capacitance, this limits the number of bits of the low-order capacitor. A correction method can be used to correct this error, so as to achieve a smaller capacitor array to reduce power consumption.

[0006] There are generally two classification methods for correction: one is divided into analog correction and digital correction, and the other is divided into front-end correction and back-end correction. Analog correction is to change the weight of the capacitor of this bit through an analog method to achieve error correction; digital correction is to directly adjust the output encoding by changing the digital weight of this bit; front-end correction means that after the chip is powered on, a certain time is first given for the chip to measure and obtain the correction code value, and these correction code values are read during the subsequent conversion process; back-end correction means that the code value correction is synchronized during the conversion process; generally, the two classification methods form four correction schemes: analog front-end correction, analog back-end correction, digital front-end correction, and digital back-end correction. Summary of the Invention

[0007] In view of the above, the present invention provides a method for correcting the low-order segment parasitic capacitance of the SAR ADC segmentation structure, which adopts an analog front-end correction scheme, that is, by changing the magnitude of the reference voltage of the lower plate of the low-order capacitor array to change the weight of the low-order capacitor array.

[0008] A method for correcting low-segment parasitics in a segmented SAR ADC structure. The SAR ADC includes a differential DAC array, a comparator, and a reference voltage source. The reference voltage source includes a reference voltage VREF and an adjustable voltage VREFB. The adjustable voltage VREFB is a programmable variable reference voltage generated by modifying a given reference voltage VREF. The adjustable voltage VREFB is used to correct the effect of capacitance parasitics generated by the low-segment array during the manufacturing process on weight errors.

[0009] The differential DAC array includes a high-segment capacitor array and a low-segment capacitor array, which are connected via a bridge capacitor; the high-segment capacitor array, i.e., the MSB segment, has a total of m bits, and the low-segment capacitor array, i.e., the LSB segment, has a total of n bits, the lower plate of the LSB segment is connected to VREFB or ground, and the lower plate of the MSB segment is connected to VREF or ground, where m and n are natural numbers greater than 1;

[0010] The proposed correction method first utilizes a differential DAC array through analog sequential comparison to obtain the comparator offset voltage code. This code is then used to adjust VREFB, connected to the lower plate of the LSB segment, to eliminate the impact of the LSB segment's parasitic capacitance, which inevitably occurs during the manufacturing process, on the linearity of the SAR ADC. Without a correction algorithm, the greater the number of LSB segments and the smaller the unit capacitance of the LSB segment, the greater the impact of parasitic capacitance. Therefore, to avoid the impact of parasitic capacitance, the number of LSB segments needs to be reduced and the unit capacitance increased. However, with a correction algorithm, the number of LSB segments can be increased, while the unit capacitance of the LSB segment can be reduced, thereby reducing the total capacitance and, consequently, power consumption.

[0011] Furthermore, the MSB segment and the LSB segment are both differential structures of P and N poles, wherein the P pole includes two groups of capacitors SPH and SPL, and the N pole includes two groups of capacitors SNH and SNL; the four groups of capacitors SPH, SPL, SNH and SNL in the MSB segment have m capacitors in each group and the size of each capacitor is 2 i-1 C, 1≤i≤m; four groups of capacitors SPH, SPL, SNH and SNL in the LSB segment, each group has n capacitors and the size of each capacitor is 2 j-1 C, 1≤j≤n, C is the unit capacitance value.

[0012] Furthermore, during the calibration process, a register is used to store the comparator offset voltage code, and during the conversion process, the code in the register is read and converted to correct the comparator offset to eliminate the influence of the comparator offset on the calculation result.

[0013] Furthermore, the specific process of obtaining the comparator offset voltage code is as follows:

[0014] A1. Use the P-pole capacitor to perform successive comparisons. The specific process is as follows:

[0015] During the sampling phase, the state of the P-pole of the differential DAC array is initialized. The upper plates of all capacitors are connected to the common-mode voltage VCM, the lower plates of all SPH and SNH capacitors are connected to VREF, and the lower plates of all SPL and SNL capacitors are grounded.

[0016] In the conversion and comparison phase, the connection between the upper plate of the capacitor and VCM is disconnected, and the switch state of the lower plate of the capacitor remains unchanged; the output results are compared using a comparator. If the comparison result shows that the P terminal is greater than the N terminal, the voltage at the P terminal needs to be reduced, so that the lower plate of SPH is switched from VREF to ground; if the comparison result shows that the N terminal is greater than the P terminal, the voltage at the P terminal needs to be increased, so that the lower plate of SPL is switched from ground to VREF; according to the above comparison from high to low, the quantization result is recorded and stored in the register;

[0017] A2. Use the N-pole capacitor to perform successive comparisons. The specific process is as follows:

[0018] During the sampling phase, the state of the N-pole of the differential DAC array is initialized. The upper plates of all capacitors are connected to the common-mode voltage VCM, the lower plates of all SPH and SNH capacitors are connected to VREF, and the lower plates of all SPL and SNL capacitors are grounded.

[0019] In the conversion and comparison phase, the connection between the upper plate of the capacitor and VCM is disconnected, and the switch state of the lower plate of the capacitor remains unchanged; the output results are compared using a comparator. If the comparison result shows that the N terminal is greater than the P terminal, the voltage at the N terminal needs to be reduced, so that the lower plate of SNH is switched from VREF to ground; if the comparison result shows that the P terminal is greater than the N terminal, the voltage at the N terminal needs to be increased, so that the lower plate of SNL is switched from ground to VREF; according to the above comparison from high to low, the quantization result is recorded and stored in the register;

[0020] A3. Repeat steps A1 and A2 multiple times, sum and average the quantization results, and obtain the comparator offset voltage codes corresponding to the P-terminal correction and the N-terminal correction.

[0021] Furthermore, the VREFB connected to the lower plate of the LSB segment is adjusted to eliminate the parasitic effects. In the process, the comparator offset coding is used to eliminate the influence of the comparator offset. The specific process is as follows:

[0022] B1. Correct the P-pole parasitic capacitance. The specific process is as follows:

[0023] During the sampling phase, the upper plates of all capacitors are connected to the common-mode voltage VCM, the lower plates of the LSB segment SPH are grounded, the lower plate of the lowest-order capacitor in the MSB segment SPH is connected to VREF, and the lower plates of the remaining capacitors are grounded; the lower plate of the LSB segment SPL is grounded, the lower plate of the MSB segment SPL is connected to VREF, the lower plates of all SNHs are grounded, and the lower plates of all SNLs are connected to VREF;

[0024] During the conversion and comparison phase, the upper plate of the capacitor is disconnected from VCM, and the lower plate of the lowest-order capacitor in the LSB segment SPH is connected to VREFB, while the lower plates of the remaining capacitors remain unchanged. The lower plate of the LSB segment SPL is connected to VREFB, and the lower plate of the lowest-order capacitor in the MSB segment SPL is grounded, while the lower plates of the remaining capacitors remain unchanged. All SNH and SNL lower plate switches read the corresponding N-terminal corrected comparator offset voltage code to perform switching operations.

[0025] According to the comparison result of the comparator, the value of VREFB is adjusted from high to low to obtain the correction code value of VREFB: if the comparison result shows that the N end is smaller than the P end, the gain coefficient of VREFB is reduced and the correction code value of the corresponding bit is set to 0; if the comparison result shows that the N end is larger than the P end, the gain coefficient of VREFB is increased and the correction code value of the corresponding bit is set to 1;

[0026] B2. Correct the N-pole parasitic capacitance. The specific process is as follows:

[0027] During the sampling phase, the upper plates of all capacitors are connected to the common-mode voltage VCM, the lower plates of the LSB segment SNH are grounded, the lower plate of the lowest-order capacitor in the MSB segment SNH is connected to VREF, and the lower plates of the remaining capacitors are grounded; the lower plate of the LSB segment SNL is grounded, the lower plate of the MSB segment SNL is connected to VREF, the lower plates of all SPHs are grounded, and the lower plates of all SPLs are connected to VREF;

[0028] During the conversion and comparison phase, the upper plate of the capacitor is disconnected from VCM, and the lower plate of the lowest-order capacitor in the LSB segment SNH is connected to VREFB, while the lower plates of the remaining capacitors remain unchanged. The lower plate of the LSB segment SNL is connected to VREFB, and the lower plate of the lowest-order capacitor in the MSB segment SNL is grounded, while the lower plates of the remaining capacitors remain unchanged. All SPH and SPL lower plate switches read the comparator offset voltage code corresponding to the P-terminal correction and perform switching operations.

[0029] According to the comparison result of the comparator, the value of VREFB is adjusted from high to low to obtain the correction code value of VREFB: if the comparison result is that the P end is less than the N end, the gain coefficient of VREFB is reduced and the correction code value of the corresponding bit is set to 0; if the comparison result is that the P end is greater than the N end, the gain coefficient of VREFB is increased and the correction code value of the corresponding bit is set to 1;

[0030] B3. Repeat steps B1 and B2 multiple times to eliminate the effects of thermal noise on the comparison results. Record the comparison results in a register and calculate the average value, which is used as the voltage value of VREFB in the SAR ADC conversion phase.

[0031] Based on the above technical solution, the present invention has the following beneficial technical effects:

[0032] 1. The present invention can correct the parasitic capacitance of the low segment of the segmented capacitor by simply adding an additional buffer with adjustable gain to generate VREFB. Moreover, since the driving buffer does not need to drive the high bit, the driving capability requirement is much lower than that of the main driving buffer of VREF.

[0033] 2. The correction method of the present invention can increase the number of bits of low-segment capacitors, thereby reducing the capacitance value of the capacitors, thereby reducing the circuit area and power consumption.

[0034] 3. The correction method of the present invention can be applied to low-power SAR ADCs. By adjusting the number of correction bits of VREFB, corrections of different accuracies can be achieved, which has good practicality and portability. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of the structural principle of traditional SAR ADC.

[0036] Figure 2 Schematic diagram of the structural principle of the SAR ADC of the present invention.

[0037] Figure 3 Schematic diagram of the structure of the differential DAC array in the SAR ADC of the present invention. DETAILED DESCRIPTION

[0038] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] It is not difficult to conclude from the weight error analysis that the parasitic capacitance of the MSB segment will not affect the nonlinearity of the conversion result, while the parasitic capacitance of the LSB segment will affect the nonlinearity of the conversion result. Assume that the voltage generated by the change of the lowest bit of the capacitance of the MSB segment on the upper plate is dV o1 The voltage change of the highest bit of the LSB segment on the upper plate is dV o2 , and the bridge capacitance is a unit capacitance C μ , then the weight error Among them C Lt is the total capacitance of the LSB segment, C dis the parasitic capacitance, k is the size of the lowest capacitance, generally 1, which is a unit capacitance C μ According to the capacitor linearization condition, k(C u +C Lt )=2 L C μ ,therefore:

[0040]

[0041] If VREF=VREFB, the weight error is C d / 2 L C μ If VREFB>VREF, this weight error can be eliminated, which is the theoretical basis of the correction algorithm of the present invention. Since the latter weight error is a fixed value and basically does not change with the conversion process, foreground correction can be performed.

[0042] like Figure 2 As shown, the present invention first transforms the reference voltage source, adding an adjustable voltage VREFB to the base reference voltage. By using an analog method, the weight of the low-segment capacitor array VREFB is changed by comparing and changing the value of the low-segment capacitor array VREFB one by one, thereby eliminating the parasitic effect of the low-segment capacitor array on the ground. This correction is automatically tested and corrected within a period of time after power-on. After the correction is completed, the correction code value is stored in a register. During the conversion process, the register value is read to adjust the voltage of VREFB and perform analog-to-digital conversion. This can eliminate the effect of parasitic capacitance on the linearity of the conversion result, thereby increasing the number of bits in the LSB segment and reducing the capacitance of the unit capacitor to reduce the total capacitance value, thereby reducing power consumption.

[0043] In this embodiment, the DAC adopts a bridge capacitor structure, such as Figure 3 As shown, it consists of a high-order 5-bit capacitor array and a low-order 4-bit capacitor array connected in series via bridge capacitors. The top plate is connected to VINP and VINN, respectively, which connect to the sampling switch and comparator. The bottom plate uses a VCM-based connection method. During the sampling phase, SPH and SNH are all connected to VREF, and SPL and SNL are all connected to GND. This connection method has the advantage of reducing power consumption. During the conversion phase, if the comparator output is 1, that is, VINP > VINN, it indicates that the voltage at VINP needs to be reduced and the voltage at VINN needs to be increased. In this case, the corresponding position of SPH is connected to GND, and the corresponding position of SNL is connected to VREF. Conversely, if the comparator output is 0, that is, VINN > VINP, it indicates that the voltage at VINN needs to be reduced and the voltage at VINP needs to be increased. In this case, the corresponding position of SNH is connected to GND, and the corresponding position of SNP is connected to VREF. During the conversion process, the voltage on one side of VINN and VINP increases and the voltage on the other side decreases by the same amount, and the input common mode of the comparator remains unchanged.

[0044] The present invention's algorithm for eliminating parasitic capacitance in the low-end of a low-power SAR ADC requires generating an adjustable reference voltage source, VREFB, and connecting it to the lower plate of the low-end capacitor array. The comparator offset voltage correction process is as follows: The capacitors in the MSB segment are connected to the capacitor array but do not participate in the operation.

[0045] (1) First, use the P-terminal capacitor to calibrate the comparator offset. Initialize the DAC array state by connecting all top plates to VCM (or a voltage close to VCM) and all SPH and SNH terminals of the bottom plate to VREF, and all SPL and SNL terminals to GND.

[0046] (2) The sampling switch disconnects the upper plate from VCM, while the voltage level connected to the lower plate remains unchanged.

[0047] (3) Use a comparator to compare the output results. If the comparison result shows that the P terminal is greater than the N terminal, the voltage at the P terminal needs to be reduced, that is, the high-bit SPH is switched from VREF to GND. If the comparison result shows that the N terminal is greater than the P terminal, the voltage at the P terminal needs to be increased, that is, the high-bit SPL is switched from GND to VREF. This comparison is performed bit by bit from high to low, and the quantization results are recorded and stored in a register.

[0048] (4) Use the N-terminal capacitor to calibrate the comparator offset. Synchronize the operation on the P-terminal to the operation on the N-terminal, and repeat the above steps to obtain the offset result.

[0049] (5) To eliminate the influence of noise, repeat steps (1) to (4) multiple times, and sum and average the results to obtain the final offset code value.

[0050] The steps for calculating the VREFB required to correct for parasitic capacitance are as follows. The VREFB voltage on the lower plate of the LSB segment is adjusted using the correction code value to eliminate the impact of the LSB segment parasitic capacitance, which is unavoidable during the capacitor manufacturing process, on ADC linearity. During the correction process, the comparator offset is corrected using the comparator offset code value stored in the register to eliminate the impact of the comparator offset on the calculation result.

[0051] (1) First, the parasitic capacitance of the P terminal is corrected. In the first sampling phase, the upper plates of the P and N terminals are connected to the common mode voltage VCM. The lower plates of the SPH LSB segment are all grounded, the lowest bit of the MSB segment is connected to VREF, and the remaining bits are grounded. The capacitors of the SPL LSB segment are all grounded, and the capacitors of the MSB segment are all connected to VREF. At this time, all capacitors of SNH are grounded, and all capacitors of SNL are connected to VREF.

[0052] (2) During the conversion and comparison phase, the top plate is disconnected from the common-mode voltage VCM. The lowest LSB of the SPH segment is connected to VREFB, while the remaining bits remain unchanged. The entire SPL LSB segment is connected to VREFB, and the lowest MSB segment is grounded, while the remaining bits remain unchanged. The SNH and SNL segments read the previously corrected comparator offset values ​​and perform the comparator offset correction.

[0053] (3) According to the comparison result of the comparator, the value of VREFB is changed successively to obtain the code value of VREFB correction.

[0054] (4) Correct the parasitic capacitance at the N-terminal, swap the operations of the SP and SN switches, and repeat the above steps.

[0055] (5) Repeat steps (1) to (4) multiple times to eliminate the influence of thermal noise on the comparison results. The final result is recorded in the register and averaged to obtain the final result.

[0056] In normal operating mode, the steps to add correction code and SAR logic conversion are as follows:

[0057] (1) The upper plate of the P-terminal capacitor is connected to VINP, the upper plate of the N-terminal capacitor is connected to VINN, SPL and SNL are all connected to GND, the lower plates of the high-end capacitor SPH and SNH are all connected to VREF, and the lower plates of the low-end capacitor SPH and SNH are all connected to VREFB.

[0058] (2) VREFB outputs the corresponding voltage according to the code value measured during the previous calibration work.

[0059] (3) The connection between the sampling switch and the input signals VINN and VINP is disconnected, and the comparator compares VINP with VINN at this time, and the comparison result is used as the result of the highest bit.

[0060] (4) Execute the VCM-Based SAR logic comparison step. If the comparison result shows that the P terminal is greater than the N terminal, the voltage of the P terminal needs to be reduced, that is, the corresponding bit SPH is switched from VREF / VREFB to GND, and the voltage of the N terminal is increased, that is, the corresponding bit SNL is changed from GND to VREF / VREFB; conversely, if the comparison result shows that the N terminal is greater than the P terminal, the voltage of the P terminal needs to be increased, that is, the corresponding bit SPL is switched from GND to VREF / VREFB, and the voltage of the N terminal needs to be reduced, that is, the corresponding bit SNH is switched from VREF / VREFB to GND.

[0061] (5) Compare bit by bit from high to low and execute SAR logic, record the quantization results, and store them in the register.

[0062] Under the correction algorithm of the present invention, after simulation and testing of a 10-bit SAR ADC, the effective number of bits of the conversion result can reach nearly 10 bits, and low-power operation is achieved, which meets the design requirements.

[0063] Table 1 provides a table showing the weighted error caused by parasitic capacitance for a 10-bit ADC prototype under different parasitic capacitance conditions, along with the effective number of bits before and after correction. It can be seen that before correction, the effective number of bits degrades as the parasitic capacitance ratio increases, reaching 9.88, 9.26, 8.73, and 7.76 bits at 0 LSB, 0.5 LSB, 1 LSB, and 2 LSB, respectively. After correction, the results are all corrected to above 9.8 bits, approaching the value without parasitic capacitance.

[0064] Table 1

[0065] Parasitic capacitance Weight Error Effective number of digits (uncorrected) Effective number of digits (after correction) 0LSB 0％ 9.88 —— 0.5LSB 3.6％ 9.26 9.84 1LSB 7.2％ 8.73 9.82 2LSB 14.5％ 7.76 9.84

[0066] The above description of the embodiments is intended to facilitate understanding and application of the present invention by those skilled in the art. It will be apparent that those skilled in the art can readily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without requiring inventive effort. Therefore, the present invention is not limited to the above embodiments, and improvements and modifications made by those skilled in the art based on the disclosure of the present invention should fall within the scope of protection of the present invention.

Claims

1. A SAR ADC segmented structure low-segment parasitic correction method, characterized by: The SAR ADC includes a differential DAC array, a comparator, and a reference voltage source. The reference voltage source includes a reference voltage VREF and an adjustable voltage VREFB. The adjustable voltage VREFB is a programmable variable reference voltage generated by modifying a given reference voltage VREF. It is used to correct the impact of capacitance parasitics generated by the low-end array during the manufacturing process on weight errors. The calibration method first uses a differential DAC array to obtain the comparator offset voltage code through analog comparison. Then, VREFB connected to the lower plate of the LSB segment is adjusted according to the code to eliminate the influence of the LSB segment parasitic capacitance on the SAR ADC linearity caused by the inevitable LSB segment parasitic capacitance during the manufacturing process. In the process, the comparator offset code is used to eliminate the influence of the comparator offset. The specific process is as follows: Step B1. Correct the P-pole parasitic capacitance. The specific process is as follows: During the sampling phase, the upper plates of all capacitors are connected to the common-mode voltage VCM, the lower plates of the LSB segment SPH are grounded, the lower plate of the lowest-order capacitor in the MSB segment SPH is connected to VREF, and the lower plates of the remaining capacitors are grounded; the lower plate of the LSB segment SPL is grounded, the lower plate of the MSB segment SPL is connected to VREF, the lower plates of all SNHs are grounded, and the lower plates of all SNLs are connected to VREF; During the conversion and comparison phase, the upper plate of the capacitor is disconnected from VCM, and the lower plate of the lowest-order capacitor in the LSB segment SPH is connected to VREFB, while the lower plates of the remaining capacitors remain unchanged. The lower plate of the LSB segment SPL is connected to VREFB, and the lower plate of the lowest-order capacitor in the MSB segment SPL is grounded, while the lower plates of the remaining capacitors remain unchanged. All SNH and SNL lower plate switches read the corresponding N-terminal corrected comparator offset voltage code to perform switching operations. According to the comparison result of the comparator, the value of VREFB is adjusted from high to low to obtain the correction code value of VREFB: if the comparison result shows that the N end is smaller than the P end, the gain coefficient of VREFB is reduced and the correction code value of the corresponding bit is set to 0; if the comparison result shows that the N end is larger than the P end, the gain coefficient of VREFB is increased and the correction code value of the corresponding bit is set to 1; Step B2. Correct the N-pole parasitic capacitance. The specific process is as follows: During the sampling phase, the upper plates of all capacitors are connected to the common-mode voltage VCM, the lower plates of the LSB segment SNH are grounded, the lower plate of the lowest-order capacitor in the MSB segment SNH is connected to VREF, and the lower plates of the remaining capacitors are grounded; the lower plate of the LSB segment SNL is grounded, the lower plate of the MSB segment SNL is connected to VREF, the lower plates of all SPHs are grounded, and the lower plates of all SPLs are connected to VREF; During the conversion and comparison phase, the upper plate of the capacitor is disconnected from VCM, and the lower plate of the lowest-order capacitor in the LSB segment SNH is connected to VREFB, while the lower plates of the remaining capacitors remain unchanged. The lower plate of the LSB segment SNL is connected to VREFB, and the lower plate of the lowest-order capacitor in the MSB segment SNL is grounded, while the lower plates of the remaining capacitors remain unchanged. All SPH and SPL lower plate switches read the comparator offset voltage code corresponding to the P-terminal correction and perform switching operations. According to the comparison result of the comparator, the value of VREFB is adjusted from high to low to obtain the correction code value of VREFB: if the comparison result is that the P end is less than the N end, the gain coefficient of VREFB is reduced and the correction code value of the corresponding bit is set to 0; if the comparison result is that the P end is greater than the N end, the gain coefficient of VREFB is increased and the correction code value of the corresponding bit is set to 1; Step B3. Repeat steps B1 and B2 multiple times to eliminate the impact of thermal noise on the comparison result. The comparison result is recorded in a register and averaged, which is used as the voltage value of VREFB in the SAR ADC conversion phase.

2. The SAR ADC segmented structure low-segment parasitic correction method according to claim 1, wherein: The differential DAC array includes a high-segment capacitor array and a low-segment capacitor array, which are connected through a bridge capacitor; the high-segment capacitor array, i.e., the MSB segment, has a total of m bits, and the low-segment capacitor array, i.e., the LSB segment, has a total of n bits, the lower plate of the LSB segment is connected to VREFB or ground, and the lower plate of the MSB segment is connected to VREF or ground, where m and n are natural numbers greater than 1.

3. The SAR ADC segmented structure low-segment parasitic correction method according to claim 2, characterized in that: The MSB segment and the LSB segment are both differential structures of the P and N poles, wherein the P pole contains two groups of capacitors SPH and SPL, and the N pole contains two groups of capacitors SNH and SNL; the four groups of capacitors SPH, SPL, SNH and SNL in the MSB segment have m capacitors in each group and the size of each capacitor is C, 1≤i≤m; the four groups of capacitors SPH, SPL, SNH and SNL in the LSB segment, each group has n capacitors and the size of each capacitor is C, 1≤j≤n, C is the unit capacitance value.

4. The SAR ADC segmented structure low-segment parasitic correction method according to claim 1, wherein: During the calibration process, a register is used to store the comparator offset voltage code. During the conversion process, the code in the register is read and converted, and the comparator offset is corrected to eliminate the influence of the comparator offset on the calculation result.

5. The SAR ADC segmented structure low-segment parasitic correction method according to claim 3, characterized in that: The specific process of obtaining the comparator offset voltage code is as follows: Step A1. Use the P-pole capacitor to perform a successive comparison. The specific process is as follows: During the sampling phase, the state of the P-pole of the differential DAC array is initialized. The upper plates of all capacitors are connected to the common-mode voltage VCM, the lower plates of all SPH and SNH capacitors are connected to VREF, and the lower plates of all SPL and SNL capacitors are grounded. During the conversion comparison phase, the connection between the upper plate of the capacitor and VCM is disconnected, and the switch state of the lower plate of the capacitor remains unchanged; Use a comparator to compare the output results. If the comparison result shows that the P terminal is greater than the N terminal, the voltage at the P terminal needs to be reduced so that the lower plate of the SPH is switched from VREF to ground. If the comparison result shows that the N terminal is greater than the P terminal, the voltage at the P terminal needs to be increased so that the lower plate of the SPL is switched from ground to VREF. Compare each bit from high to low and record the quantization result, which is then stored in a register. Step A2. Perform successive comparisons using the N-pole capacitor. The specific process is as follows: During the sampling phase, the state of the N-pole of the differential DAC array is initialized. The upper plates of all capacitors are connected to the common-mode voltage VCM, the lower plates of all SPH and SNH capacitors are connected to VREF, and the lower plates of all SPL and SNL capacitors are grounded. During the conversion comparison phase, the connection between the upper plate of the capacitor and VCM is disconnected, and the switch state of the lower plate of the capacitor remains unchanged; Use a comparator to compare the output results. If the comparison result shows that the N terminal is greater than the P terminal, the voltage at the N terminal needs to be reduced, so that the lower plate of SNH is switched from VREF to ground. If the comparison result shows that the P terminal is greater than the N terminal, the voltage at the N terminal needs to be increased, so that the lower plate of SNL is switched from ground to VREF. Compare each bit from high to low and record the quantization result, which is stored in the register. Step A3. Repeat steps A1 and A2 multiple times, sum and average the quantization results, and obtain the comparator offset voltage codes corresponding to the P-terminal correction and the N-terminal correction.

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