Communication methods and optical modules

Abstract

This application provides a communication method and an optical module. The method includes: a first optical module determining a first delay; and the first optical module sending the first delay to an interface chip. The communication method and optical module provided by this application can report the delay of the optical module to the interface chip to improve the accuracy of master-slave clock synchronization, thereby further improving the clock accuracy of network devices.

Description

[0001] This application is a divisional application of Chinese patent application No. 201910059723.1, filed on January 22, 2019, entitled "Communication Method and Optical Module". Technical Field

[0002] This application relates to the field of communication technology, and in particular to a communication method and an optical module. Background Technology

[0003] In mobile communication networks, base stations based on the Time Division Duplex (TDD) standard need to meet strict time synchronization requirements; otherwise, the wireless signals transmitted by the base station will interfere with other base stations, causing base stations in adjacent areas to malfunction.

[0004] Currently, time synchronization between different base stations can be achieved through clock protocols. For example, the Institute of Electrical and Electronics Engineers (IEEE) 1588V2 protocol is a precision clock synchronization protocol standard for network measurement and control systems. Also known as the Precision Time Protocol (PTP), 1588V2 can synchronize the time of multiple network devices with microsecond-level accuracy. Currently, time synchronization between network devices in the 1588V2 protocol uses a master-slave clock approach. By encoding time information and utilizing network symmetry and delay measurement techniques, master-slave time synchronization is achieved through bidirectional interaction of message packets. Specifically, the master and slave clocks stamp messages when sending and receiving them, respectively, to calculate the time difference between them. The slave clock then calibrates its local time based on this calculated time difference.

[0005] Currently, how to further improve the accuracy of master-slave clock time synchronization, thereby further improving the clock accuracy of network devices, is a technical problem that urgently needs to be solved. Summary of the Invention

[0006] This application provides a communication method and an optical module that can report the delay of the optical module to the interface chip to improve the accuracy of master-slave clock time synchronization, thereby further improving the clock accuracy of network devices.

[0007] The first aspect of this application provides a communication method, including:

[0008] The first optical module determines the first time delay;

[0009] The first optical module sends the first delay to the interface chip.

[0010] In this scheme, since a delay reporting register access interface is defined in the first optical module, the first optical module can report the first delay to the MAC layer or PHY layer through this delay reporting register access interface. This first delay can be compensated into the timestamp of the message recorded by the MAC layer or PHY layer to improve the accuracy of master-slave clock time synchronization, thereby further improving the clock accuracy of the network device.

[0011] In one possible implementation, the first optical module is a gray light optical module, which includes an optical transmitter with an input interface and an output interface. The first optical module determines a first time delay, which includes:

[0012] The first optical module receives the first data stream through the input interface;

[0013] The first optical module sends the first data stream to the second network device through the output interface;

[0014] The first optical module determines the first delay as the transmission delay of the first data stream in the optical transmitter.

[0015] In this scheme, the first delay can be the delay of the first data stream being transmitted in the optical transmitter of the first optical module. Alternatively, since the optical transmitter includes different processing circuits, the aforementioned first delay can also be the delay caused by the different processing circuits in the optical transmitter processing the first data stream.

[0016] Specifically, the aforementioned first delay can be the delay of the first data stream being transmitted from the input interface of the optical transmitter to the output interface of the optical transmitter, or it can be the delay caused by at least one processing circuit included in the optical transmitter when processing the first data stream. Of course, it can also be the sum of the delay caused by at least one processing circuit included in the optical transmitter when processing the first data stream and the default value or design value.

[0017] In one possible implementation, the first optical module is a colored optical module in a first network device, and the first optical module includes an optical transmitter and a first optical receiver;

[0018] Before the first optical module determines the first time delay, the method further includes:

[0019] The first optical module receives a first data stream through the optical transmitter, and the transmission delay of the first data stream in the optical transmitter is the second delay;

[0020] The first optical module sends the first data stream to the second optical receiver of the second optical module in the second network device through the optical transmitter, and the transmission delay of the first data stream in the second optical receiver is the third delay;

[0021] The sum of the second delay and the third delay is the first delay;

[0022] The first optical module receives a second data stream sent by the second network device through the first optical receiver, and the second data stream carries indication information.

[0023] The first optical module determines the first time delay, including:

[0024] The first optical module determines the first time delay based on the instruction information.

[0025] In this case, the first optical module is the color optical module in the first network device, and the second optical module is the color optical module in the second network device. The first optical module includes an optical transmitter and a first optical receiver. After receiving a first data stream through the optical transmitter, the first optical module transmits the first data stream to the second optical receiver of the second optical module in the second network device. Thus, based on the first data stream, a second transmission delay and a third transmission delay of the first data stream in the first optical module can be measured.

[0026] Furthermore, after determining the second delay of the first data stream within itself, the first optical module sends this second delay along with the first data stream to the second optical module. After determining the third delay of the first data stream within itself, the second optical module adds the second and third delays together to determine the first delay. After determining the first delay, the second optical module sends a second data stream to the first optical module, which carries indication information. Based on this indication information, the first optical module can then determine the first delay.

[0027] In one possible implementation, the indication information includes the first delay.

[0028] In one possible implementation, if the first optical module does not support delay measurement, the first delay is the design value.

[0029] In this scheme, if the first optical module does not have the function of measuring time delay, the aforementioned first time delay can be a pre-set design value, or a simulation value obtained through simulation, or of course, a default value.

[0030] In one possible implementation, the method further includes:

[0031] When the first data stream is transmitted to the first circuit, the first optical module extracts the first indication signal carried in the first data stream;

[0032] When the first data stream is transmitted to the second circuit, the first optical module extracts the second indication signal carried in the first data stream;

[0033] The first optical module determines the first time delay based on the first indication signal and the second indication signal.

[0034] In one possible implementation, determining the first time delay based on the first indication signal and the second indication signal includes:

[0035] Measure the phase difference between the first indication signal and the second indication signal;

[0036] The first time delay is determined based on this phase difference;

[0037] Both the first indication signal and the second indication signal can be alignment identifier AM indication signals, or the first indication signal can be an AM indication signal and the second indication signal can be a digital signal processing (DSP) frame header signal.

[0038] In the above scheme, when the first data stream is transmitted to the first circuit, a first indication signal carried in the first data stream is extracted, and when the first data stream is transmitted to the second circuit, a second indication signal carried in the first data stream is extracted. Then, by using a high-precision phase detection algorithm, the phase difference between the first and second indication signals is measured, thereby determining the first time delay, which improves the accuracy of the determined time delay.

[0039] The first circuit and the second circuit can be any two different circuits in the first optical module.

[0040] Furthermore, the first indication signal and the second indication signal can be AM indication signals, or the first indication signal can be an AM indication signal and the second indication signal can be a digital signal processing (DSP) frame header signal. Alternatively, the aforementioned first and second indication signals can also be other easily identifiable signals, such as identifiers inserted in the first data stream.

[0041] In one possible implementation, the interface chip includes at least one of a physical layer PHY chip and a media access control layer MAC chip.

[0042] A second aspect of this application provides an optical module, used as a first optical module, comprising:

[0043] The processor is used to determine the first delay;

[0044] The processor is also used to send the first delay to the interface chip.

[0045] In one possible implementation, the first optical module is a gray light optical module, which includes an optical transmitter. The optical transmitter includes the processor, an input interface, and an output interface, wherein:

[0046] The optical transmitter is used to receive a first data stream through the input interface;

[0047] The optical transmitter is also used to send the first data stream to a second network device through the output interface;

[0048] The processor is also configured to determine the first delay as the time delay at which the first data stream is transmitted in the optical transmitter.

[0049] In one possible implementation, the first optical module is a colored optical module in a first network device, the first optical module including an optical transmitter and a first optical receiver, the first optical receiver including the processor;

[0050] The optical transmitter is used to receive a first data stream, the first data stream being transmitted in the optical transmitter with a second delay;

[0051] The optical transmitter is also used to send the first data stream to the second optical receiver of the second optical module in the second network device, wherein the first data stream is transmitted in the second optical receiver with a third delay.

[0052] The sum of the second delay and the third delay is the first delay;

[0053] The first optical receiver is used to receive a second data stream sent by the second network device, the second data stream carrying indication information;

[0054] The processor is specifically used to determine the first delay based on the instruction information.

[0055] In one possible implementation, the indication information includes the first delay.

[0056] In one possible implementation, if the first optical module does not support delay measurement, the first delay is the design value.

[0057] In one possible implementation, the light emitter includes a first circuit and a second circuit; the processor is further configured to:

[0058] When the first data stream is transmitted to the first circuit, the first indication signal carried in the first data stream is extracted;

[0059] When the first data stream is transmitted to the second circuit, the second indication signal carried in the first data stream is extracted;

[0060] The first time delay is determined based on the first indication signal and the second indication signal.

[0061] In one possible implementation, the processor is also used for:

[0062] Measure the phase difference between the first indication signal and the second indication signal;

[0063] The first time delay is determined based on this phase difference;

[0064] Wherein, both the first indication signal and the second indication signal are alignment identifier AM indication signals, or the first indication signal is an AM indication signal and the second indication signal is a digital signal processing (DSP) frame header signal.

[0065] In one possible implementation, the interface chip includes at least one of a physical layer PHY chip and a media access control layer MAC chip.

[0066] The communication method and optical module provided in this application, after determining the first delay, will send the determined first delay to the interface chip. Since a delay reporting register access interface is defined in the first optical module, the first optical module can report the first delay to the MAC layer or PHY layer through this interface, thereby compensating for the first delay in the timestamp of the message recorded by the MAC layer or PHY layer. This improves the accuracy of master-slave clock synchronization, and further enhances the clock accuracy of the network device. Attached Figure Description

[0067] Figure 1 This is a schematic diagram of an application scenario provided by an embodiment of this application;

[0068] Figure 2 A schematic diagram for calculating the time difference between the master and slave clocks;

[0069] Figure 3 A flowchart illustrating a communication method provided in an embodiment of this application;

[0070] Figure 4 This is a schematic diagram of the optical module.

[0071] Figure 5 This is a schematic diagram of the gray light module.

[0072] Figure 6 This is a schematic diagram of the structure of the colored light module;

[0073] Figure 7 This is a schematic diagram of the oDSP chip in the gray light module;

[0074] Figure 8This is a schematic diagram of the oDSP chip in the color light module;

[0075] Figure 9 This is a schematic diagram of the structure of an optical module provided in an embodiment of this application;

[0076] Figure 10 This is a schematic diagram of another optical module provided in an embodiment of this application;

[0077] Figure 11 This is a schematic diagram of another optical module provided in an embodiment of this application. Detailed Implementation

[0078] The following explanations of some terms used in this application are provided to facilitate understanding by those skilled in the art.

[0079] 1) An optical module mainly consists of photoelectric conversion devices and electrical signal processing devices. An optical module includes an optical transmitter and an optical receiver. The electrical signal processing devices include clock and data recovery (CDR) chips or optical digital signal processing (oDSP) chips. Optical modules typically perform photoelectric conversion and / or electro-optical conversion. For example, the transmitting optical module converts an electrical signal into an optical signal and transmits the converted optical signal through optical fiber to the receiving optical module, which then converts the optical signal back into an electrical signal for processing.

[0080] 2) Network equipment can be devices used to communicate with mobile devices. Network equipment can be routers, switches, packet transport network (PTN) equipment, optical transport network (OTN) equipment, passive optical network (PON) equipment, or synchronous digital hierarchy (SDH) equipment, etc. It can also be access points (APs) in WLANs, base stations (BTSs) in GSM or CDMAs, base stations (nodeBs, NBs) in WCDMAs, evolved base stations (eNBs or eNodeBs) in LTEs, network relay stations or network access points, or in-vehicle equipment, wearable devices, and network equipment in future 5G networks or future evolved PLMN networks, or new generation base stations (gNodeBs) in NR systems, etc.

[0081] 3) Delay reporting register access interface, also known as register access interface or delay reporting interface. It is used to report the delay of message transmission in the optical transmitter of the first optical module to the interface chip, or to report the delay of message transmission in the optical transmitter of the first optical module and in the optical receiver of the second optical module to the interface chip.

[0082] 4) In this application, "at least one" can refer to one or more, and "more than" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. The scope described by "above" or "below" includes boundary points.

[0083] 5) The unit in this application refers to a functional unit or logical unit. It can be in software form, where its function is implemented by a processor executing program code; or it can be in hardware form.

[0084] Those skilled in the art will understand that the communication method provided in this application embodiment can be applied to application scenarios where optical modules report latency to interface chips. The interface chip includes at least one of a physical layer (PHY) chip and a media access control (MAC) chip. In mobile communication networks, base stations based on Time Division Duplex (TDD) systems need to meet strict time synchronization requirements; otherwise, the wireless signals transmitted by the base station will interfere with other base stations, causing base stations in adjacent areas to malfunction. To achieve time synchronization between base stations, it is usually necessary to enable network protocols to transmit time information. This application embodiment uses the 1588V2 protocol to transmit time information as an example for illustration. Of course, other protocols can also be used to transmit time information. For example, clock level information can be represented by the synchronous status message (SSM) information in the SDH protocol.

[0085] Figure 1 This is a schematic diagram of an application scenario provided in an embodiment of this application, such as... Figure 1 As shown, a time source device is typically deployed in the core layer of the wireless network. It receives satellite time via the Global Positioning System (GPS) or BeiDou as a reference source. Then, it transmits time information to the transmission device 101 through external time auxiliary interfaces such as Pulse per Second and Time of Day (1PPS+TOD) or PTP interfaces (Ethernet interfaces with 1588V2 protocol enabled). The transmission device 101 transmits the time information down the core layer hop by hop through the PTP interface to the aggregation layer device 102. The aggregation layer device 102 then transmits the time information down the access layer device 103 hop by hop. The access layer device 103 transmits the time information to the connected base station 104 through external time auxiliary interfaces such as 1PPS+TOD or PTP interfaces, thereby achieving time synchronization of all base stations in the network.

[0086] Among them, the transmission device 101, the aggregation layer device 102, and the access layer device 103 can be network devices such as routers, switches, PTN devices, OTN devices, or PON devices.

[0087] It is worth noting that the transmission device 101, the aggregation layer device 102, and the access layer device 103 can also synchronize their time using the scheme described in the embodiments of this application.

[0088] Below, using the 1588V2 protocol as an example, we will explain in detail how time synchronization between base stations is achieved: The 1588V2 protocol, also known as PTP, is a precise time synchronization protocol that can achieve time synchronization among multiple network devices. Its core idea is to use a master-slave clock approach, encoding time information and utilizing network symmetry and delay measurement technology to achieve master-slave time synchronization through bidirectional interaction of message packets. Specifically, the master and slave clocks stamp messages when sending and receiving them, respectively, thereby calculating the time difference between the master and slave clocks. The slave clock then calibrates its local time based on the calculated time difference.

[0089] Figure 2 A diagram illustrating the calculation of the time difference between master and slave clocks, as shown below. Figure 2 As shown, the master node sends a synchronization message (Sync) to the slave node and records the sending timestamp t1 in its register. Upon receiving the synchronization message, the slave node records the received timestamp t2. Additionally, the master node sends a follow_up message to the slave node, including timestamp t1. The slave node then sends a delay request message (Delay_Req) ​​to the master node, carrying timestamp t3. Upon receiving the delay request message, the master node records the received timestamp t4 and sends t4 in a delay reply message (Delay_Resp) to the slave node. The clock in the master node is the master clock, and the clock in the slave node is the slave clock.

[0090] Using the times t1, t2, t3 and t4 mentioned above, the slave clock can calculate the delay and offset between the slave clock and the master clock according to the following formulas (1) and (2). The slave clock can calibrate its local timestamp through the delay and offset, thereby achieving synchronization between the master and slave clocks.

[0091] Delay=(t2-t1+t4-t3) / 2 (1)

[0092] Offset = (t2 - t1 - t4 + t3) / 2 (2)

[0093] According to the 1588V2 protocol principle, the stamping reference plane for the master and slave clocks is located at the physical medium dependent interface (MDI) sublayer of the PTP port. However, since the stamping event is triggered by the PTP packet header, the MDI layer cannot complete PTP packet header recognition, and therefore cannot complete the stamping. Therefore, in practical implementations, stamping is often performed at the media access control (MAC) layer or the physical layer (PHY) layer to record the packet's timestamp. The time delay between the MAC layer or PHY layer and the MDI layer of the optical module is measured and compensated into the recorded timestamp, thus realizing the MDI layer stamping function. The MDI layer of the optical module refers to the port of the optoelectronic conversion device within the optical module.

[0094] However, the current Ethernet protocol, IEEE 802.3, only defines a register interface for delay reporting at the MAC or PHY layer to report the transmission delay of messages within those layers. However, the delay between the MAC or PHY layer and the MDI layer of the optical module comprises two parts: the transmission delay within the MAC or PHY layer and the transmission delay within the optical module itself. Therefore, the delay compensated for in the recorded timestamps in existing technologies only includes the transmission delay within the MAC or PHY layer. This results in inaccurate timestamps recorded by the MDI layer, leading to low master-slave clock synchronization accuracy and consequently, low clock accuracy in network devices.

[0095] This application, considering the aforementioned problems, proposes a communication method in which a first optical module, after determining a first delay, sends the determined first delay to the interface chip. Since a delay reporting register access interface is defined in the first optical module, the first optical module can report the first delay to the MAC layer or PHY layer through this interface. This compensates for the delay caused by the transmission of the message within the optical module by adding it to the recorded timestamp of the message, thereby improving the accuracy of master-slave clock synchronization and further enhancing the clock accuracy of the network device.

[0096] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0097] Figure 3 This is a schematic flowchart illustrating a communication method provided in an embodiment of this application. Figure 3 As shown, the method in this embodiment may include:

[0098] Step 301: The first optical module determines the first time delay.

[0099] According to formula (2) above, if the delays in the receiving and transmitting directions of the optical module are symmetrical, the calculated result of the offset before and after PTP timestamp correction is the same. For this type of optical module, delay reporting and correction are not required. Therefore, in practical applications, delay reporting and correction are only needed for optical modules with asymmetrical delays in the receiving and transmitting directions. Therefore, before introducing how the first optical module determines the first delay, the structure of existing optical modules and the delay symmetry of optical modules will be introduced first.

[0100] Figure 4 This is a schematic diagram of the optical module's components, such as... Figure 4 As shown, the optical module 100 includes two parts: an optical transmitter 110 and an optical receiver 120. Furthermore, the optical module 100 can generally be divided into a "digital domain" and an "analog domain." The "digital domain" is composed of CDR or oDSP chips, mainly implementing analog and digital signal processing. When the processing circuits in the receiving and transmitting directions are asymmetrical, time delay asymmetry will be introduced. The "analog domain" includes the transmitter optical subassembly (TOSA) and the receiver optical subassembly (ROSA), including gold fingers, printed circuit board (PCB) traces, and optoelectronic conversion devices. It is generally designed with symmetrical transmission and reception, resulting in relatively fixed and symmetrical transmission and reception delays, which have virtually no impact on clock synchronization accuracy. Therefore, when determining the time delay in the optical module, usually only the time delay in the "digital domain" is considered.

[0101] It is understandable that if the optical module uses a CDR chip, since the CDR chip processes the data stream through purely analog signal circuits, the transmit and receive delays in the optical module are symmetrical, and therefore, delay determination and reporting are unnecessary. For example, if the optical module uses a CDR chip, the delay of the optical module can be determined using the method described in this application embodiment, or the delay of the optical module can be designed to a default value or a design value.

[0102] If the optical module uses an oDSP chip, the asymmetry and uncertainty in transmit and receive delays caused by the oDSP chip will affect the accuracy of the network device's clock. Therefore, it is necessary to determine the transmission delay of the message in the optical module and report this delay to the interface chip to improve the accuracy of the network device's clock. A specific example will illustrate this below.

[0103] Figure 5 This is a schematic diagram of the gray light module, as shown below. Figure 5As shown, the gray light module includes an optical transmitter 170 and an optical receiver 180. The optical transmitter 170 includes an oDSP chip 130 and a TOSA 25, and the optical receiver 180 includes an oDSP chip 140 and a ROSA 26. The TOSA 25 and ROSA 26 are connected to optical fibers.

[0104] The oDSP chip 130 includes, in sequence, a serializing / deserializing circuitry (Serdes) 11, a channel alignment circuit 12, a first-in-first-out (FIFO) circuit 13, a mapping circuit 14, a digital signal processing (DSP) circuit 15, a FIFO circuit 16, and a digital-to-analog converter (DAC) 17. The oDSP chip 140 includes, in sequence, a serializing / deserializing circuit (Serdes) 18, a channel distribution circuit 19, a FIFO circuit 20, a demapping circuit 21, a DSP circuit 22, a FIFO circuit 23, and an analog-to-digital converter (ADC) 24.

[0105] For example, the mapping circuit 14 can be implemented using a four-level pulse amplitude modulation (PAM4) circuit or a bit interleaving (BitMux) circuit. Similarly, the demapping circuit 21 can be implemented using a PAM4 circuit or a bit deinterleaving (BitDeMux) circuit.

[0106] The circuits in oDSP chips 130 and 140 mentioned above can cause asymmetry and uncertainty in transmit and receive delays, potentially introducing delays on the order of approximately 10 nanoseconds (ns). This can lead to low accuracy in clock synchronization between base stations, thereby affecting the clock accuracy of network equipment. Therefore, by determining the transmission delay of packets within the gray light optical module and reporting this delay to the interface chip, the clock accuracy of network equipment can be further improved.

[0107] Figure 6 This is a schematic diagram of the structure of the colored light module, as shown below. Figure 6As shown, the color light module includes an optical transmitter 190 and an optical receiver 200. The optical transmitter 190 includes an oDSP chip 150 and an integrated tunable laser assembly (ITLA) 49. The optical receiver 200 includes an oDSP chip 160 and a dual filter switch 50. The ITLA 49 and the dual filter switch 50 are connected to optical fibers.

[0108] The oDSP chip 150 includes a serializing / deserializing circuitry (Serdes) 31, a channel alignment circuit 32, a FIFO circuit 33, a mapping circuit 34, a FIFO circuit 35, a forward error correction (FEC) circuit 36, a DSP circuit 37, a FIFO circuit 38, and a DAC 39 connected in sequence. The oDSP chip 160 includes a serializing / deserializing circuitry (Serdes) 40, a channel distribution circuit 41, a FIFO circuit 42, a demapping circuit 43, a FIFO circuit 44, an FEC circuit 45, a DSP circuit 46, a FIFO circuit 47, and an ADC 48 connected in sequence.

[0109] For example, the mapping circuit 34 can be implemented using a framer or a bitmux circuit. Similarly, the demapping circuit 43 can be implemented using a deframer or a bitdemux circuit.

[0110] Because the oDSP chip 150 and oDSP chip 160 of the color optical module have added FEC circuits compared to the gray optical module, there are more uncertainties in the transmission and reception delay, and the impact on synchronization accuracy is about 10 ns. Therefore, the above-mentioned color optical module determines the transmission delay of the message in the color optical module and reports the delay to the interface chip, which can further improve the clock accuracy of the network device.

[0111] Based on the above, the process of determining the first time delay of the first optical module will be described below, taking the gray light optical module and the colored light optical module as examples.

[0112] Combination Figure 5 As shown, when the first optical module is a gray light optical module, the first optical module includes an optical transmitter 170, which includes an input interface and an output interface. The first optical module can receive the first data stream through the input interface and send the first data stream to the second network device through the output interface. The first optical module will determine the transmission delay of the first data stream in the optical transmitter as the first delay.

[0113] The first delay can be the delay of the first data stream transmitted in the optical transmitter 170 of the first optical module. It is understood that, with reference to... Figure 5 As shown, since the optical transmitter 170 includes different processing circuits, the aforementioned first delay can also be the delay caused by the different processing circuits in the optical transmitter processing the first data stream.

[0114] Specifically, such as Figure 5 As shown, the aforementioned first delay can be the delay of the first data stream being transmitted from the input interface of the optical transmitter 170 to the output interface of the optical transmitter 170. This first delay can also be the delay caused by at least one processing circuit included in the optical transmitter 170 processing the first data stream. Alternatively, the first delay can be the sum of the delay caused by at least one processing circuit included in the optical transmitter 170 processing the first data stream and a default value or design value. For example, the first delay can be the delay of the first data stream being transmitted from the serial / parallel circuit 11 to the optical TOSA module 25, or it can be the delay caused by each processing circuit in the oDSP chip 130 processing the first data stream, or it can be the sum of the delay caused by the channel alignment circuit 12, FIFO circuit 13, mapping circuit 14, DSP circuit 15, and FIFO circuit 16 in the oDSP chip 130 processing the first data stream, plus a default value or design value.

[0115] For example, since the delay of the oDSP chip in the first optical module is asymmetrical and uncertain, in practical applications, when calculating the delay of the first optical module, it is usually only necessary to determine the delay corresponding to the oDSP chip.

[0116] The following describes in detail the method for determining the delay of the first data stream in the oDSP chip of the gray optical module. Specifically, when the first data stream is transmitted to the first circuit, the first optical module extracts the first indication signal carried in the first data stream, and when the first data stream is transmitted to the second circuit, it extracts the second indication signal carried in the first data stream, and determines the first delay based on the first and second indication signals. Since the structure of the first data stream does not change during the mapping process on the receiving path and the demapping process on the transmitting path, in one possible implementation, the first delay can be measured based on the alignment marker (AM) indication signal; that is, the first and second indication signals can be AM indication signals. Of course, in other possible implementations, the first and second indication signals can also be other easily identifiable signals, such as identifiers inserted in the first data stream. This application does not limit the specific form of the first and second indication signals, as long as they can be identified at the input and output interfaces.

[0117] Furthermore, when determining the first time delay based on the first indication signal and the second indication signal, the first time delay can be determined by measuring the phase difference between the first indication signal and the second indication signal and based on the phase difference.

[0118] Furthermore, the first circuit and the second circuit can be any two different circuits in the oDSP chip, such as the first circuit being... Figure 5 The channel alignment circuit 12 and the second circuit shown can be a FIFO circuit 16. In this case, the time delay of the first data stream from the channel alignment circuit 12 to the FIFO circuit 16 can be determined based on the phase difference between the first indicator signal and the second indicator signal. For the time delay of other circuits, default values ​​or design values ​​can be used. Alternatively, the first circuit can also be a FIFO circuit 13, and the second circuit can also be a FIFO circuit 16, etc. In this case, the time delay of the first data stream from the FIFO circuit 13 to the FIFO circuit 16 can be determined based on the phase difference between the first indicator signal and the second indicator signal. Similarly, for the time delay of other circuits, default values ​​or design values ​​can be used.

[0119] The following explanation will be based on the example of the first circuit being the channel alignment circuit 12, the second circuit being the DAC 17, and both the first and second indicator signals being AM indicator signals.

[0120] Specifically, Figure 7 This is a schematic diagram of the oDSP chip in the gray light module, as shown below. Figure 7As shown, since Serdes11 and DAC 17, or Serdes18 and ADC 24, mainly implement the conversion between serial and parallel data, the delay of Serdes11 and DAC 17, or Serdes18 and ADC 24, is relatively fixed after each power-on of the first optical module and the link state stabilizes. It is not affected by factors such as fiber optic cable insertion / removal or module insertion / removal. Therefore, the corresponding delays of Serdes11 and DAC17, or Serdes18 and ADC 24 (e.g., ...) are... Figure 7 The paths A, F, C, and D in the simulation can be pre-set design values, simulation values ​​obtained through simulation, or default values.

[0121] In addition, the mapping circuit 14 and demapping circuit 21 mainly implement the mapping and demapping processing of multiple low-speed channels to high-speed channels. Since the mapping adopts a bit interleaving method, it will not change the structure of the first data stream, and the delay of each bit of data will be the same. However, under the influence of factors such as fiber optic plugging and unplugging, module plugging and unplugging, and PVT (process, voltage, temperature) changes, the read and write clock phases of the synchronous processing FIFO circuits 13 and 16 or FIFO circuits 20 and 23 will change, making the delay of each FIFO circuit not fixed, thus introducing delay asymmetry. Therefore, the delay of the oDSP chip needs to be measured every time the link of the first optical module is successfully established and the clock state changes. In one possible implementation, when measuring the delay of the message in the oDSP chip, it is usually only necessary to measure the delay of the message in the oDSP chip. Figure 7 The time delay corresponding to path B or path E shown in the figure.

[0122] In other words, taking the measurement of the delay of a message in the oDSP chip of an optical transmitter as an example, in practical applications, when measuring the first delay of the first data stream from the input interface to the output interface of the optical transmitter, only the delay of the first data stream in path B can be measured. After measuring the delay corresponding to path B, the delay corresponding to path B, the delay corresponding to path A, and the delay corresponding to path C are added together to obtain the transmission delay of the first data stream in the optical transmitter.

[0123] For example, the explanation will be given using AM indicator signals as both the first and second indicator signals. Figure 7As shown, the first data stream arrives at the channel alignment circuit 12 through multiple channels. After the channel alignment circuit 12 performs channel alignment processing on the first data stream in the multiple channels, the channel selection module 55 selects one of the multiple channels and detects the AM indicator signal 1 carried in the first data stream from the selected channel, and sends the detected AM indicator signal 1 to the TX delay measurement module 56. In addition, in order to correctly extract the AM indicator signal from the output interface of the optical transmitter, the AM indicator signal needs to be marked. The marked AM indicator signal will be carried in the first data stream for continued transmission. When the first data stream is detected to be output from the FIFO circuit 16, that is, transmitted to the DAC 17, the AM extraction module 53 extracts the AM indicator signal 2 carried in the first data stream from the channel where the AM indicator signal 1 was detected according to the aforementioned marking, and sends the detected AM indicator signal 2 to the TX delay measurement module 56. In this way, the TX delay measurement module 56 can determine the delay of the first data stream in path B by measuring the phase difference between the AM indicator signal 1 and the AM indicator signal 2 using a high-precision phase detection algorithm. The measurement accuracy depends on the accuracy of the phase detection algorithm. Under normal circumstances, the accuracy of the measured delay can reach the level of hundreds of ps.

[0124] Among them, AM indicator signal 1 and AM indicator signal 2 mentioned above are the same AM indicator signal.

[0125] For example, after determining the delay of the first data stream in path B, the delay of the first data stream in the optical transmitter can be obtained by acquiring the delays of path A and path C, and adding the delays of path A, path C and path B respectively.

[0126] Additionally, it is worth noting that, in order to improve the accuracy of delay determination, when performing channel alignment processing and selecting one of the multiple channels to extract the AM indicator signal, the channel that arrives at the channel alignment module last in the first data stream can be selected to extract the AM indicator signal.

[0127] Those skilled in the art will understand that the transmission delay of the first data stream in the optical receiver of the first optical module can be the sum of the delays of paths D, E, and F. The delays of paths D and F are similar to those of paths C and A in the optical transmitter; they can be pre-set design values, simulation values ​​obtained through simulation, or default values. The delay of path E is determined similarly to that of path B in the transmission direction. When the first data stream is transmitted to the first circuit, the AM detection module 54 extracts the AM indicator signal 3 carried by the first data stream, and when the first data stream is transmitted to the second circuit, the AM extraction module extracts the AM indicator signal 4 carried by the first data stream. The RX delay measurement module 57 determines the delay of path E by measuring the phase difference between the AM indicator signal 3 and the AM indicator signal 4. The first circuit can be a FIFO circuit, and the second circuit can be a serial / parallel circuit 18. The channel selection process and the AM indicator signal extraction process can be referred to the description in the optical transmitter section, and will not be repeated here.

[0128] Furthermore, considering the differences in chip implementation, when the gray light module lacks the function to measure the delays of path B and path E, the delays of path B and path E can be preset design values, simulated values ​​obtained through simulation, or even default values. Additionally, since the actual delays of path B and path E change each time the link of the first optical module is successfully established and after a change in clock state, the preset design values, simulated values, or default values ​​will not be accurate enough. To solve this problem, in practical applications, taking the preset design values ​​as an example, the average value of the design values ​​can be calculated and used as the delay of path B and path E; alternatively, the minimum and maximum design values ​​can be determined, and both can be used as the delays of path B and path E, so that both values ​​are reported to the interface chip. The method for determining simulated values ​​and default values ​​is similar to that for determining design values, and will not be elaborated here.

[0129] Continue to refer to Figure 6As shown, when the first optical module is a colored optical module, due to the presence of overhead processing circuits such as a framer and FEC inside the colored optical module, the overhead addition and deletion processing will change the structure of the original data stream, resulting in different processing delays for each bit of data during the processes of adding overhead (transmitter end) and deleting overhead (receiver end). Since each bit of data received by the first optical module may be a PTP message stamping signal, this non-fixed delay makes it impossible to measure the delay when the first optical module is used as a transmitter or as a receiver independently. However, those skilled in the art will understand that the delay changes introduced by data mapping at the transmitter end and the delay changes introduced by data demapping at the receiver end are opposite processes; that is, the sum of the processing delays for the same bit of data at the transmitter and receiver ends is fixed. Based on this, in the embodiments of this application, the first optical module and the second optical module can be paired to measure the delay.

[0130] The first optical module is a color optical module in the first network device, and the second optical module is a color optical module in the second network device. The first optical module includes an optical transmitter and a first optical receiver. The first optical module receives a first data stream through the optical transmitter, wherein the transmission delay of the first data stream in the optical transmitter is a second delay. Then, the first optical module sends the first data stream to the second optical receiver of the second optical module in the second network device through the optical transmitter, wherein the transmission delay of the first data stream in the second optical receiver is a third delay. The sum of the second delay and the third delay is the aforementioned first delay. The first optical module receives a second data stream sent by the second network device through the first optical receiver. The second data stream carries indication information. Accordingly, when the first optical module determines the first delay, it can do so based on the indication information carried in the second data stream.

[0131] Specifically, Figure 8 This is a schematic diagram of the oDSP chip in the color light module, as shown below. Figure 8 As shown, the first optical module 67 is a colored optical module in the first network device. The first optical module includes an optical transmitter 210 and an optical receiver 220. After receiving the first data stream through the optical transmitter 210, the first optical module 67 transmits the first data stream to the second optical receiver 230 of the second optical module 96 in the second network device through the optical transmitter 210. In this way, based on the first data stream, the second delay of the first data stream transmission in the optical transmitter 210 of the first optical module 67 and the third delay of the first data stream transmission in the second optical receiver 230 of the second optical module 96 can be measured.

[0132] The second optical module 96 includes an optical transmitter 240 and an optical receiver 230. The optical transmitter 240 includes an oDSP chip 97 and an ITLA 82, and the optical receiver 230 includes an oDSP chip 95 and a dual filter switch 70. The ITLA 82 and the dual filter switch 70 are connected to optical fibers.

[0133] The oDSP chip 97 includes a serializing / deserializing circuitry (Serdes) 93, a channel alignment circuit 91, a FIFO circuit 90, a mapping circuit 89, a FIFO circuit 88, a forward error correction (FEC) circuit 87, a DSP circuit 86, a FIFO circuit 85, and a DAC 83 connected in sequence. The oDSP chip 95 includes an ADC 71, a FIFO circuit 73, a DSP circuit 74, an FEC circuit 75, a FIFO circuit 76, a demapping circuit 77, a FIFO circuit 78, a channel distribution circuit 79, and a serializing / deserializing circuit (Serdes) 81 connected in sequence.

[0134] For example, the mapping circuit 89 can be implemented using a framer or a bitmux circuit. Similarly, the demapping circuit 77 can be implemented using a deframer or a bitdemux circuit.

[0135] Understandably, reference Figure 8 As shown, since the transmitter 210 in the first optical module includes different processing circuits, the aforementioned second delay can be the delay caused by the different processing circuits in the transmitter 210 processing the first data stream. Similarly, the optical receiver 230 in the second optical module also includes different processing circuits; therefore, the aforementioned third delay can be the delay caused by the different processing circuits in the optical receiver 230 processing the first data stream.

[0136] Specifically, such as Figure 8As shown, the aforementioned second delay can be the delay of the first data stream being transmitted from the input interface of the optical transmitter 210 to the output interface of the optical transmitter 210, or it can be the delay caused by at least one processing circuit included in the optical transmitter 210 processing the first data stream. Alternatively, it can be the sum of the delay caused by at least one processing circuit included in the optical transmitter 210 processing the first data stream and a default value or design value. For example, the second delay can be the delay of the first data stream being transmitted from the serial / parallel circuit 31 to the TOSA module 49, or it can be the delay caused by each processing circuit in the oDSP chip 190 processing the first data stream, or it can be the sum of the delay caused by the channel alignment circuit 32, FIFO circuit 33, mapping circuit 34, FIFO circuit 35, FEC circuit 36, DSP circuit 37, and FIFO circuit 38 in the oDSP chip 190 processing the first data stream, plus a default value or design value.

[0137] The aforementioned third delay can be the delay of the first data stream being transmitted from the input interface of the second optical receiver 230 to the output interface of the second optical receiver 230, or the delay caused by at least one processing circuit included in the second optical receiver 230 processing the first data stream. Alternatively, it can be the sum of the delay caused by at least one processing circuit included in the second optical receiver 230 processing the first data stream and a default value or design value. For example, the third delay can be the delay of the first data stream being transmitted from the dual filter switch 70 to the serial / parallel circuit 81, or the delay caused by each processing circuit in the oDSP chip 95 processing the first data stream, or the delay caused by the DAC 71, FIFO circuit 73, DSP circuit 74, FEC circuit 75, FIFO circuit 76, demapping circuit 77, FIFO circuit 78, and channel distribution circuit 79 in the oDSP chip 95 processing the first data stream, plus a default value or design value.

[0138] Similar to the gray light module, due to the asymmetry and uncertainty of the time delay of the oDSP chip in the first and second optical modules, in practical applications, when calculating the time delay of the first and second optical modules, it is usually only necessary to determine the time delay corresponding to the oDSP chip in the first and second optical modules.

[0139] The following sections will detail the latency of the first data stream in the oDSP chip of the first optical module and the latency of the first data stream in the oDSP chip of the second optical module.

[0140] Specifically, when the first data stream is transmitted in the first optical module, the first optical module extracts the first indication signal carried in the first data stream when the first data stream is transmitted to the first circuit, and extracts the second indication signal carried in the first data stream when the first data stream is transmitted to the second circuit. Then, based on the first indication signal and the second indication signal, the second delay of the first data stream transmitted in the optical transmitter 210 in the first optical module 67 can be determined.

[0141] Furthermore, when the first data stream is transmitted in the second optical module, the second optical module extracts the third indication signal carried in the first data stream when the first data stream is transmitted to the third circuit, and extracts the fourth indication signal carried in the first data stream when the first data stream is transmitted to the fourth circuit. Then, based on the third indication signal and the fourth indication signal, the third delay of the first data stream transmitted in the second optical receiver 230 in the second optical module 96 can be determined.

[0142] The first circuit and the second circuit can be any two different circuits in the oDSP chip 190, such as the first circuit being... Figure 8 The channel alignment circuit 32 and the second circuit shown can be a FIFO circuit 38. In this case, the time delay of the first data stream from the channel alignment circuit 32 to the FIFO circuit 38 can be determined based on the phase difference between the first indicator signal and the second indicator signal. For the time delay of other circuits, default values ​​or design values ​​can be used. Alternatively, the first circuit can also be a FIFO circuit 33, and the second circuit can also be a FIFO circuit 38, etc. In this case, the time delay of the first data stream from the FIFO circuit 33 to the FIFO circuit 38 can be determined based on the phase difference between the first indicator signal and the second indicator signal. Similarly, for the time delay of other circuits, default values ​​or design values ​​can be used.

[0143] Similarly, the third and fourth circuits can be any two different circuits in the oDSP chip 95, such as the third circuit being... Figure 8 The FIFO circuit 73 and the fourth circuit shown can be a serial / parallel circuit 81. In this case, the time delay of the first data stream from the FIFO circuit 73 to the serial / parallel circuit 81 can be determined based on the phase difference between the first and second indicator signals. For the time delays of other circuits, default values ​​or design values ​​can be used. Alternatively, the third circuit can also be a signal processing circuit 74, and the fourth circuit can also be a serial / parallel circuit 81, etc. In this case, the time delay of the first data stream from the signal processing circuit 74 to the serial / parallel circuit 81 can be determined based on the phase difference between the first and second indicator signals. Similarly, for the time delays of other circuits, default values ​​or design values ​​can be used.

[0144] Continue to refer to Figure 8As shown, taking the transmission direction of the first data stream from the first optical module 67 to the second optical module 96 as an example, the time delays of paths A1 and C1 in the first optical module 67, and the time delays of paths D2 and F2 in the second optical module 96, are similar to the time delays corresponding to Serdes11 and DAC17, or Serdes18 and ADC24 in the gray light optical module. These can be pre-set design values, simulation values ​​obtained through simulation, or even default values. Therefore, when measuring the second time delay of the first data stream at the optical transmitter 210 of the first optical module 67, it is only necessary to measure the time delay corresponding to path B1; similarly, when measuring the third time delay of the first data stream at the second optical receiver 230 of the second optical module 96, it is only necessary to measure the time delay corresponding to path E2.

[0145] Specifically, when measuring the time delay corresponding to path B1, the following example illustrates the circuit configuration: the first circuit is the channel alignment circuit 32, the second circuit is the DAC 39, the first indicator signal is the AM indicator signal, and the second indicator signal is the DSP frame header indicator signal. Figure 8 As shown, the first data stream arrives at the channel alignment circuit 32 in the first optical module 67 through multiple channels. After the channel alignment circuit 32 performs channel alignment processing on the first data stream from the multiple channels, the channel selection module 64 selects one of the channels. When the first data stream is transmitted to the channel alignment circuit 32, the AM detection module 60 detects the AM indicator signal 1 carried in the first data stream from the selected channel and sends the detected AM indicator signal 1 to the TX delay measurement module 65. In addition, in order to correctly extract the AM indicator signal at the output interface of the second receiver 230 of the second optical module 96, the AM indicator signal also needs to be marked. The marked AM indicator signal will be carried in the first data stream for continued transmission. At the output interface of the optical transmitter 210 of the first optical module 67, the DSP frame header indication signal 1 is periodically extracted. For example, after the first data stream is transmitted to the DAC 39, the DSP frame header extraction module 61 extracts the DSP frame header indication signal 1 carried in the first data stream and sends the extracted DSP frame header indication signal 1 to the TX delay measurement module 65. The TX delay measurement module 65 then uses a high-precision phase detection algorithm to measure the phase difference between the AM indication signal 1 and the DSP frame header indication signal 1, thereby determining the delay of the first data stream in path B1. The measurement accuracy depends on the accuracy of the phase detection algorithm; typically, the measured delay accuracy can reach the level of hundreds of ps.

[0146] It is worth noting that since the period of the AM indicator signal is different from that of the DSP frame header indicator signal, there is no fixed phase relationship between them. To facilitate paired measurements, it is necessary to select two adjacent signals from the AM and DSP frame header indicator signals for measurement. For example, if the period of the AM indicator signal is 3ms and the period of the DSP frame header indicator signal is 1.2ms, then in the first data stream, there may be two DSP frame header indicator signals before an AM indicator signal appears. In this case, the AM indicator signal and the adjacent DSP frame header indicator signal can be selected for measurement, such as the AM indicator signal and a second DSP frame header indicator signal, and the phase difference between these two signals can be measured.

[0147] In addition, in order to correctly extract the DSP frame header indication signal from the input interface of the second optical receiver 230 of the second optical module 96, identification information needs to be added to the DSP frame header signal, and the first data stream with the added identification information is sent to the second optical module 96 through the optical fiber.

[0148] Similarly, when measuring the time delay corresponding to path E2, the following example illustrates the circuit configuration: the third circuit is a FIFO circuit 73, the fourth circuit is a serial / parallel circuit 81, the third indicator signal is a DSP frame header indicator signal, and the fourth indicator signal is an AM indicator signal. Figure 8 As shown, after the first optical module 67 sends the first data stream to the second optical receiver 230 of the second optical module 96 through the optical transmitter 210, the first data stream passes through the ADC 71 in the second optical module 96 and is transmitted to the FIFO circuit 73. Based on the identification information added to the DSP frame header indication signal in the optical transmitter 210 of the first optical module 67, the DSP frame header indication signal 2 is extracted by the DSP frame header pre-detection module 72 and sent to the RX delay measurement module 94. At this time, the first data stream will continue to be transmitted. After the first data stream is detected to be transmitted to the serial / parallel circuit 81, the AM extraction module 80 will extract the AM indicator signal 2 carried in the first data stream from the channel according to the identification information added to the AM in the optical transmitter 210 of the first optical module 67, and send the extracted AM indicator signal 2 to the RX delay measurement module 94. In this way, the RX delay measurement module 94 can determine the delay of the first data stream in path E2 by measuring the phase difference between the DSP frame header indicator signal 2 and the AM indicator signal 2 using a high-precision phase detection algorithm. The measurement accuracy depends on the accuracy of the phase detection algorithm. Under normal circumstances, the accuracy of the measured delay can reach the level of hundreds of ps.

[0149] Among them, AM indicator signal 1 and AM indicator signal 2 are the same AM indicator signal, and DSP frame header indicator signal 1 and DSP frame header indicator signal 2 are the same indicator signal.

[0150] In addition, the second and fourth indication information can also adopt other easily identifiable data identifiers, such as inserting a new identifier into the first data stream. The specific form of the second and fourth indication information is not limited in this embodiment.

[0151] For example, after determining the delay of the first data stream in path B1, the second delay of the first data stream transmitted in the optical transmitter of the first optical module can be obtained by acquiring the delays of path A1 and path C1 and adding the delays of path A1, path C1 and path B1 respectively.

[0152] For example, after determining the delay of the first data stream in path E2, the third delay of the first data stream transmitted in the second optical receiver of the second optical module can be obtained by acquiring the delays of path D2 and path F2 and adding the delays of path D2, path E2 and path F2 respectively.

[0153] It should be noted that after the first optical module determines the second delay of the first data stream in the optical transmitter 210, it will carry the second delay in the first data stream and send it to the second receiver 230 of the second optical module 96. After the second optical module determines the third delay of the first data stream in the second receiver 230, it will add the obtained second delay and third delay together and determine the first delay as the sum.

[0154] In one possible implementation, after determining the first delay, the second optical receiver 230 of the second optical module sends a second data stream to the first optical receiver 220 of the first optical module 67. This second data stream carries indication information, allowing the first optical module to determine the first delay based on this indication information. In another possible implementation, the indication information includes the first delay, and the first optical module 67 can directly determine the first delay after receiving the indication information from the second data stream through the first optical receiver 220.

[0155] It is worth noting that, similar to the gray light module, if the colored light module does not have the function of measuring the delay of path B1 and path E2, the delay of path B1 and path E2 can also be a preset design value, or a simulation value obtained through simulation, or of course, a default value.

[0156] Those skilled in the art will understand that when the second optical module 96 sends a first data stream to the first optical receiver 220 of the first optical module 67 via the optical transmitter 240, the first delay can be the sum of the transmission delay of the first data stream in the optical transmitter 240 of the second optical module 96 and the transmission delay of the first data stream in the first optical receiver 220 of the first optical module 67. Specifically, the transmission delay of the first data stream in the optical transmitter 240 of the second optical module 96 is the sum of the delays corresponding to paths A2, B2, and C2, and the delay of the first data stream in the first optical receiver 220 of the first optical module 67 is the sum of the delays corresponding to paths D1, E1, and F1. The delays of paths A2, C2, D1, and F1, similar to the delays of paths A1, C1, D2, and F2 mentioned above, can be preset design values, simulation values ​​obtained through simulation, or default values. The time delays of path B2 in the optical transmitter 240 of the second optical module 96 and path E1 in the first optical receiver 220 of the first optical module 67 are determined in a similar manner to the aforementioned determination of the time delays of path B1 in the optical transmitter 210 of the first optical module 67 and path E2 in the second optical receiver 230 of the second optical module 96, and will not be repeated here.

[0157] Step 202: The first optical module sends the first delay to the interface chip.

[0158] In this embodiment, since a delay reporting register access interface is defined in the first optical module, after determining the first delay, the first optical module will send the first delay to the interface chip through the delay reporting register access interface of the first optical module, so that the interface chip can compensate for the first delay in the recorded timestamp. In this way, the timestamp recorded by the MDI layer includes the delay of the message transmission in the optical module, making the timestamp recorded by the MDI layer more accurate. This can improve the master-slave clock time synchronization accuracy and further improve the clock accuracy of the network device.

[0159] In one possible implementation, the interface chip includes at least one of a PHY chip and a MAC chip.

[0160] In one possible implementation, the latency reporting register access interface of the first optical module can be defined as shown in the table below:

[0161]

[0162]

[0163] The interface bit width indicates the number of bits in the interface signal. For optical modules that do not support delay reporting, the reporting value of the delay reporting register access interface is a fixed value of 0. Optical modules that support delay reporting can be further divided into two types: those that do not support delay measurement and those that do. For optical modules that do not support delay measurement, the first reported delay is the design value of the oDSP chip; for optical modules that support delay measurement, the first reported delay is the measured value obtained through indication information.

[0164] Furthermore, if the first optical module is a gray-light optical module, after determining the first delay, it can report the first delay to the interface chip according to the interface defined above. Upon receiving the first delay, the interface chip can compensate for this first delay along with the transmission delay of the message in the MAC or PHY layer by adding it to the timestamp recorded in the MAC or PHY layer. This significantly reduces the asymmetric error introduced by the optical module, making the timestamp recorded by the MDI layer more accurate. This, in turn, improves the master-slave clock synchronization accuracy, thereby further enhancing the clock accuracy of the network equipment.

[0165] If the first optical module is a colored optical module, the first delay is the sum of the transmission delay of the first data stream in the optical transmitter of the first optical module and the transmission delay of the first data stream in the second optical receiver of the second optical module. In one implementation, if the second optical module sends the measured first delay to the first optical module via the second data stream, the first optical module can report the first delay to the interface chip through the delay reporting register access interface defined in the first optical module. At this time, the second optical module can report the first delay to the interface chip through the delay reporting register access interface defined in the second optical module, or it can report 0, or report a special identifier; of course, the second optical module can also report nothing.

[0166] In another implementation, if the second optical module reports the first delay to the interface chip through the delay reporting register access interface defined in the second optical module, the first optical module can also report the first delay to the interface chip through the delay reporting register access interface defined in the first optical module. It can also report 0 or report a special identifier. Of course, the first optical module can also report nothing.

[0167] In another implementation, the first optical module and the second optical module can divide the first delay into two parts according to a preset rule. The first part is reported to the interface chip by the first optical module through the delay reporting register access interface defined in the first optical module, and the second part is reported to the interface chip by the second optical module through the delay reporting register access interface defined in the second optical module.

[0168] The communication method provided in this application embodiment involves a first optical module determining a first delay and then sending that first delay to the interface chip. Since a delay reporting register access interface is defined in the first optical module, it can report the first delay to the MAC layer or PHY layer through this interface. This first delay is then added to the timestamp of the message recorded by the MAC layer or PHY layer, thereby improving the accuracy of master-slave clock synchronization and further enhancing the clock accuracy of the network device.

[0169] The communication method provided by the embodiments of this application has been described above. The optical module provided by the embodiments of this application will be described below.

[0170] The optical module provided in this application embodiment is used as a first optical module and can be used to perform actions related to the first optical module in the above method embodiment. The optical module includes a processor 101.

[0171] Processor 101 is used to determine the first delay;

[0172] The processor 101 is also used to send the first delay to the interface chip.

[0173] The optical module provided in this application embodiment, after determining the first delay, will send the determined first delay to the interface chip. Since a delay reporting register access interface is defined in the optical module, the optical module can report the first delay to the MAC layer or PHY layer through this delay reporting register access interface. The first delay can be compensated into the timestamp of the message recorded by the MAC layer or PHY layer, thereby improving the accuracy of master-slave clock time synchronization, and thus further improving the clock accuracy of network devices.

[0174] Figure 9 A schematic diagram of the structure of an optical module provided in an embodiment of this application is shown below. Figure 9 The first optical module 10 is a gray light optical module, which includes: an optical transmitter 102, wherein the optical transmitter 102 includes the processor 101, an input interface 1021, and an output interface 1022, wherein:

[0175] The optical transmitter 102 is used to receive a first data stream through the input interface 1021;

[0176] The optical transmitter 102 is also used to send the first data stream to the second network device through the output interface 1022;

[0177] The processor 101 is further configured to determine the delay in which the first data stream is transmitted in the optical transmitter 102 as the first delay.

[0178] Figure 10For a schematic diagram of another optical module provided in an embodiment of this application, see [link to schematic diagram]. Figure 10 The first optical module 20 is a colored optical module in the first network device. The first optical module 20 includes an optical transmitter 103 and a first optical receiver 104. The first optical receiver 104 includes the processor 101, wherein:

[0179] The optical transmitter 103 is used to receive a first data stream, and the delay in which the first data stream is transmitted in the optical transmitter 103 is a second delay;

[0180] The optical transmitter 103 is also used to send the first data stream to the second optical receiver of the second optical module in the second network device, wherein the delay in which the first data stream is transmitted in the second optical receiver is a third delay.

[0181] Wherein, the sum of the second delay and the third delay is the first delay;

[0182] The first optical receiver 104 is used to receive a second data stream sent by the second network device, the second data stream carrying indication information;

[0183] The processor 101 is specifically used to determine the first delay based on the indication information.

[0184] As an example, the indication information includes the first delay.

[0185] As an example, when the optical module does not support latency measurement, the first latency is the design value.

[0186] Figure 11 For another structural schematic diagram of an optical module provided in this application embodiment, see [link to schematic diagram]. Figure 11 ,exist Figure 10 Based on the illustrated embodiment, the light emitter 103 includes a first circuit 1031 and a second circuit 1302, and the processor 101 is further configured to:

[0187] When the first data stream is transmitted to the first circuit, the first indication signal carried in the first data stream is extracted;

[0188] When the first data stream is transmitted to the second circuit, the second indication signal carried in the first data stream is extracted;

[0189] The first time delay is determined based on the first indication signal and the second indication signal.

[0190] As one embodiment, the processor 101 is further configured to:

[0191] Measure the phase difference between the first indication signal and the second indication signal;

[0192] The first time delay is determined based on the phase difference;

[0193] Wherein, both the first indication signal and the second indication signal are alignment identifier AM indication signals, or the first indication signal is an AM indication signal and the second indication signal is a digital signal processing (DSP) frame header signal.

[0194] As one embodiment, the interface chip includes at least one of a physical layer PHY chip and a media access control layer MAC chip.

[0195] The processor 101 described above can be one or more integrated circuits configured to implement the above methods, such as an oDSP, or one or more application-specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), etc. Alternatively, the processor can also be a central processing unit (CPU) or other processor capable of calling programs.

[0196] The optical module provided in this application embodiment can execute the corresponding method embodiment described above. Its implementation principle and technical effect are similar, and will not be repeated here.

[0197] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, can implement the process related to the first optical module in the communication method provided in the above method embodiments.

[0198] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0199] Furthermore, various aspects or features of the embodiments of this application can be implemented as methods, apparatus, or articles of manufacture using standard programming and / or engineering techniques. The term "article of manufacture" as used in this application encompasses a computer program accessible from any computer-readable device, carrier, or medium. For example, computer-readable media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks, or magnetic tapes), optical discs (e.g., compact discs (CDs), digital versatile discs (DVDs), etc.), smart cards, and flash memory devices (e.g., erasable programmable read-only memory (EPROMs), cards, sticks, or key drives, etc.). Additionally, the various storage media described herein may represent one or more devices and / or other machine-readable media for storing information. The term "machine-readable medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing, and / or carrying instructions and / or data.

[0200] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0201] It should be understood that in various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application.

[0202] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0203] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0204] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0205] If the aforementioned function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application embodiment, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a server, or an access network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A communication method, characterized in that, The method is executed by a first optical module, which includes a latency reporting interface, and includes: A first delay is determined, which includes the delay in transmitting the first data stream in the optical transmitter of the first optical module; The first delay is sent through the delay reporting interface; The first optical module includes a digital domain and an analog domain; the digital domain includes a clock and data recovery chip or an optical digital signal processing chip; the analog domain includes an optical transmitting sub-module and an optical receiving sub-module, or includes an integrated tunable laser array and a dual filter switcher.

2. The method according to claim 1, characterized in that, When the simulation domain includes an optical transmitting submodule and an optical receiving submodule, the first optical module is a gray light optical module, the optical transmitter includes an input interface and an output interface, and the first optical module determines a first time delay, including: The first optical module receives the first data stream through the input interface; The first optical module sends the first data stream to the second network device through the output interface; The first optical module determines the transmission delay of the first data stream in the optical transmitter as the first delay.

3. The method according to claim 1, characterized in that, When the analog domain includes an integrated tunable laser array and a dual filter switch, the first optical module is a colored light optical module in the first network device, and the first optical module includes the optical transmitter and the first optical receiver. Before the first optical module determines the first delay, the method further includes: The first optical module receives the first data stream through the optical transmitter, and the transmission delay of the first data stream in the optical transmitter is the second delay; The first optical module sends the first data stream to the second optical receiver of the second optical module in the second network device through the optical transmitter, and the transmission delay of the first data stream in the second optical receiver is the third delay; Wherein, the sum of the second delay and the third delay is the first delay; The first optical module receives a second data stream sent by the second network device through the first optical receiver, and the second data stream carries indication information; The first optical module determines the first time delay, including: The first optical module determines the first time delay based on the indication information.

4. The method according to claim 2 or 3, characterized in that, The first optical module includes a first circuit and a second circuit, and the method further includes: When the first data stream is transmitted to the first circuit, the first optical module extracts the first indication signal carried in the first data stream; When the first data stream is transmitted to the second circuit, the first optical module extracts the second indication signal carried in the first data stream; The first optical module determines the first time delay based on the first indication signal and the second indication signal.

5. The method according to claim 4, characterized in that, Determining the first time delay based on the first indication signal and the second indication signal includes: Measure the phase difference between the first indication signal and the second indication signal; The first time delay is determined based on the phase difference; Wherein, both the first indication signal and the second indication signal are alignment identifier AM indication signals, or the first indication signal is an AM indication signal and the second indication signal is a digital signal processing (DSP) frame header signal.

6. The method according to any one of claims 1-3 and 5, characterized in that, Sending the first delay through the delay reporting interface includes: The first delay is sent to the interface chip through the delay reporting interface, and the interface chip includes at least one of a physical layer PHY chip and a media access control layer MAC chip.

7. An optical module, used as a first optical module, characterized in that, include: A processor is configured to determine a first delay, the first delay including the delay of the optical transmitter of the first optical module transmitting the first data stream; The delay reporting interface is used to send the first delay; The first optical module includes a digital domain and an analog domain; the digital domain includes a clock and data recovery chip or an optical digital signal processing chip; the analog domain includes an optical transmitting sub-module and an optical receiving sub-module, or includes an integrated tunable laser array and a dual filter switcher.

8. The optical module according to claim 7, characterized in that, When the simulation domain includes an optical transmitting submodule and an optical receiving submodule, the first optical module is a gray light optical module, and the optical transmitter includes the processor, an input interface, and an output interface, wherein: The optical transmitter is used to receive the first data stream through the input interface; The optical transmitter is also used to send the first data stream to the second network device through the output interface; The processor is further configured to determine the delay in which the first data stream is transmitted in the optical transmitter as the first delay.

9. The optical module according to claim 7, characterized in that, When the analog domain includes an integrated tunable laser array and a dual filter switcher, the first optical module is a colored optical module in the first network device. The first optical module includes the optical transmitter and the first optical receiver, and the first optical receiver includes the processor. The optical transmitter is used to receive a first data stream, and the delay in which the first data stream is transmitted in the optical transmitter is a second delay; The optical transmitter is also used to send the first data stream to the second optical receiver of the second optical module in the second network device, wherein the transmission delay of the first data stream in the second optical receiver is a third delay; Wherein, the sum of the second delay and the third delay is the first delay; The first optical receiver is configured to receive a second data stream sent by the second network device, the second data stream carrying indication information; The processor is specifically configured to determine the first delay based on the indication information.

10. The optical module according to claim 8 or 9, characterized in that, The light emitter includes a first circuit and a second circuit; the processor is further configured to: When the first data stream is transmitted to the first circuit, the first indication signal carried in the first data stream is extracted; When the first data stream is transmitted to the second circuit, the second indication signal carried in the first data stream is extracted; The first time delay is determined based on the first indication signal and the second indication signal.

11. The optical module according to claim 10, characterized in that, The processor is also used for: Measure the phase difference between the first indication signal and the second indication signal; The first time delay is determined based on the phase difference; Wherein, both the first indication signal and the second indication signal are alignment identifier AM indication signals, or the first indication signal is an AM indication signal and the second indication signal is a digital signal processing (DSP) frame header signal.

12. The optical module according to any one of claims 7-9, characterized in that, The latency reporting interface is used to report the first latency to the interface chip, which includes at least one of a physical layer PHY chip and a media access control layer MAC chip.

13. The optical module according to any one of claims 7-9, characterized in that, The delay in transmitting the first data stream by the optical transmitter of the first optical module includes any one or more of the following: The time delay of the first data stream from the input interface of the transmitter to the output interface of the optical transmitter; The delay caused by at least one processing circuit included in the optical transmitter when processing the first data stream; The sum of the delay caused by at least one processing circuit in the optical transmitter when processing the first data stream and the default value or design value; Pre-set design values; Simulation values ​​obtained through simulation; or default value.

14. A network device, characterized in that, Includes a first optical module, the first optical module comprising: A processor is configured to determine a first delay, the first delay including the delay of the optical transmitter of the first optical module transmitting the first data stream; The delay reporting interface is used to send the first delay; The first optical module includes a digital domain and an analog domain; the digital domain includes a clock and data recovery chip or an optical digital signal processing chip; the analog domain includes an optical transmitting sub-module and an optical receiving sub-module, or includes an integrated tunable laser array and a dual filter switcher.

15. The network device according to claim 14, characterized in that, When the simulation domain includes an optical transmitting submodule and an optical receiving submodule, the first optical module is a gray light optical module, and the optical transmitter includes the processor, an input interface, and an output interface, wherein: The optical transmitter is used to receive the first data stream through the input interface; The optical transmitter is also used to send the first data stream to the second network device through the output interface; The processor is further configured to determine the delay in which the first data stream is transmitted in the optical transmitter as the first delay.

16. The network device according to claim 14, characterized in that, When the analog domain includes an integrated tunable laser array and a dual filter switcher, the first optical module is a colored optical module in the first network device. The first optical module includes the optical transmitter and the first optical receiver, and the first optical receiver includes the processor. The optical transmitter is used to receive a first data stream, and the delay in which the first data stream is transmitted in the optical transmitter is a second delay; The optical transmitter is also used to send the first data stream to the second optical receiver of the second optical module in the second network device, wherein the transmission delay of the first data stream in the second optical receiver is a third delay; Wherein, the sum of the second delay and the third delay is the first delay; The first optical receiver is configured to receive a second data stream sent by the second network device, the second data stream carrying indication information; The processor is specifically configured to determine the first delay based on the indication information.

17. The network device according to claim 15 or 16, characterized in that, The light emitter includes a first circuit and a second circuit; the processor is further configured to: When the first data stream is transmitted to the first circuit, the first indication signal carried in the first data stream is extracted; When the first data stream is transmitted to the second circuit, the second indication signal carried in the first data stream is extracted; The first time delay is determined based on the first indication signal and the second indication signal.

18. The network device according to claim 17, characterized in that, The processor is also used for: Measure the phase difference between the first indication signal and the second indication signal; The first time delay is determined based on the phase difference; Wherein, both the first indication signal and the second indication signal are alignment identifier AM indication signals, or the first indication signal is an AM indication signal and the second indication signal is a digital signal processing (DSP) frame header signal.

19. The network device according to any one of claims 14-16, 18, characterized in that, It also includes interface chips, The latency reporting interface is used to send the first latency to the interface chip, which includes at least one of a physical layer PHY chip and a media access control layer MAC chip.

20. The network device according to any one of claims 14-16, 18, characterized in that, The delay in transmitting the first data stream by the optical transmitter of the first optical module includes any one or more of the following: The time delay of the first data stream from the input interface of the transmitter to the output interface of the optical transmitter; The delay caused by at least one processing circuit included in the optical transmitter when processing the first data stream; The sum of the delay caused by at least one processing circuit in the optical transmitter when processing the first data stream and the default value or design value; Pre-set design values; Simulation values ​​obtained through simulation; or default value.

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